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arch,cpu: Replace StaticInst::_num${TYPE}DestRegs members with an array.

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The array is indexed using the register class.

Change-Id: I6cfd9735afa03e386e01e9e255fd6e55b7ba7272
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49712
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-08-20 19:30:16 -07:00
parent 2d012222c2
commit 967bada8db
4 changed files with 27 additions and 70 deletions
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43
src/cpu/static_inst.hh
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@@ -105,25 +105,12 @@ class StaticInst : public RefCounted, public StaticInstFlags
OpClass _opClass;
/// See numSrcRegs().
int8_t _numSrcRegs = 0;
uint8_t _numSrcRegs = 0;
/// See numDestRegs().
int8_t _numDestRegs = 0;
uint8_t _numDestRegs = 0;
/// The following are used to track physical register usage
/// for machines with separate int & FP reg files.
//@{
int8_t _numFPDestRegs = 0;
int8_t _numIntDestRegs = 0;
int8_t _numCCDestRegs = 0;
//@}
/** To use in architectures with vector register file. */
/** @{ */
int8_t _numVecDestRegs = 0;
int8_t _numVecElemDestRegs = 0;
int8_t _numVecPredDestRegs = 0;
/** @} */
std::array<uint8_t, MiscRegClass + 1> _numTypedDestRegs = {};
public:
@@ -135,21 +122,29 @@ class StaticInst : public RefCounted, public StaticInstFlags
/// machines with vector and predicate register files.
//@{
/// Number of source registers.
int8_t numSrcRegs() const { return _numSrcRegs; }
uint8_t numSrcRegs() const { return _numSrcRegs; }
/// Number of destination registers.
int8_t numDestRegs() const { return _numDestRegs; }
uint8_t numDestRegs() const { return _numDestRegs; }
/// Number of floating-point destination regs.
int8_t numFPDestRegs() const { return _numFPDestRegs; }
uint8_t numFPDestRegs() const { return _numTypedDestRegs[FloatRegClass]; }
/// Number of integer destination regs.
int8_t numIntDestRegs() const { return _numIntDestRegs; }
uint8_t numIntDestRegs() const { return _numTypedDestRegs[IntRegClass]; }
/// Number of vector destination regs.
int8_t numVecDestRegs() const { return _numVecDestRegs; }
uint8_t numVecDestRegs() const { return _numTypedDestRegs[VecRegClass]; }
/// Number of vector element destination regs.
int8_t numVecElemDestRegs() const { return _numVecElemDestRegs; }
uint8_t
numVecElemDestRegs() const
{
return _numTypedDestRegs[VecElemClass];
}
/// Number of predicate destination regs.
int8_t numVecPredDestRegs() const { return _numVecPredDestRegs; }
uint8_t
numVecPredDestRegs() const
{
return _numTypedDestRegs[VecPredRegClass];
}
/// Number of coprocesor destination regs.
int8_t numCCDestRegs() const { return _numCCDestRegs; }
uint8_t numCCDestRegs() const { return _numTypedDestRegs[CCRegClass]; }
//@}
/// @name Flag accessors.