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arch,cpu: Replace StaticInst::_num${TYPE}DestRegs members with an array.

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The array is indexed using the register class.

Change-Id: I6cfd9735afa03e386e01e9e255fd6e55b7ba7272
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49712
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-08-20 19:30:16 -07:00
parent 2d012222c2
commit 967bada8db
4 changed files with 27 additions and 70 deletions
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34
src/arch/arm/insts/tme64.cc
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@@ -82,11 +82,6 @@ MicroTfence64::MicroTfence64(ExtMachInst machInst)
{
_numSrcRegs = 0;
_numDestRegs = 0;
_numFPDestRegs = 0;
_numVecDestRegs = 0;
_numVecElemDestRegs = 0;
_numIntDestRegs = 0;
_numCCDestRegs = 0;
flags[IsMicroop] = true;
flags[IsReadBarrier] = true;
flags[IsWriteBarrier] = true;
@@ -128,13 +123,8 @@ Tstart64::Tstart64(ExtMachInst machInst, IntRegIndex _dest)
_numSrcRegs = 0;
_numDestRegs = 0;
_numFPDestRegs = 0;
_numVecDestRegs = 0;
_numVecElemDestRegs = 0;
_numIntDestRegs = 0;
_numCCDestRegs = 0;
setDestRegIdx(_numDestRegs++, RegId(IntRegClass, dest));
_numIntDestRegs++;
_numTypedDestRegs[IntRegClass]++;
flags[IsHtmStart] = true;
flags[IsInteger] = true;
flags[IsLoad] = true;
@@ -162,13 +152,8 @@ Ttest64::Ttest64(ExtMachInst machInst, IntRegIndex _dest)
_numSrcRegs = 0;
_numDestRegs = 0;
_numFPDestRegs = 0;
_numVecDestRegs = 0;
_numVecElemDestRegs = 0;
_numIntDestRegs = 0;
_numCCDestRegs = 0;
setDestRegIdx(_numDestRegs++, RegId(IntRegClass, dest));
_numIntDestRegs++;
_numTypedDestRegs[IntRegClass]++;
flags[IsInteger] = true;
flags[IsMicroop] = true;
}
@@ -178,11 +163,6 @@ Tcancel64::Tcancel64(ExtMachInst machInst, uint64_t _imm)
{
_numSrcRegs = 0;
_numDestRegs = 0;
_numFPDestRegs = 0;
_numVecDestRegs = 0;
_numVecElemDestRegs = 0;
_numIntDestRegs = 0;
_numCCDestRegs = 0;
flags[IsLoad] = true;
flags[IsMicroop] = true;
flags[IsNonSpeculative] = true;
@@ -204,11 +184,6 @@ MacroTmeOp::MacroTmeOp(const char *mnem,
PredMacroOp(mnem, machInst, __opClass) {
_numSrcRegs = 0;
_numDestRegs = 0;
_numFPDestRegs = 0;
_numVecDestRegs = 0;
_numVecElemDestRegs = 0;
_numIntDestRegs = 0;
_numCCDestRegs = 0;
numMicroops = 0;
microOps = nullptr;
@@ -219,11 +194,6 @@ MicroTcommit64::MicroTcommit64(ExtMachInst machInst)
{
_numSrcRegs = 0;
_numDestRegs = 0;
_numFPDestRegs = 0;
_numVecDestRegs = 0;
_numVecElemDestRegs = 0;
_numIntDestRegs = 0;
_numCCDestRegs = 0;
flags[IsHtmStop] = true;
flags[IsLoad] = true;
flags[IsMicroop] = true;