diff --git a/src/arch/x86/bios/IntelMP.py b/src/arch/x86/bios/IntelMP.py
index c1de985a6a..0d9a6413d5 100644
--- a/src/arch/x86/bios/IntelMP.py
+++ b/src/arch/x86/bios/IntelMP.py
@@ -38,7 +38,7 @@ from m5.SimObject import SimObject
 
 class X86IntelMPFloatingPointer(SimObject):
     type = 'X86IntelMPFloatingPointer'
-    cxx_class = 'X86ISA::IntelMP::FloatingPointer'
+    cxx_class = 'X86ISA::intelmp::FloatingPointer'
     cxx_header = 'arch/x86/bios/intelmp.hh'
 
     # The minor revision of the spec to support. The major version is assumed
@@ -51,7 +51,7 @@ class X86IntelMPFloatingPointer(SimObject):
 
 class X86IntelMPConfigTable(SimObject):
     type = 'X86IntelMPConfigTable'
-    cxx_class = 'X86ISA::IntelMP::ConfigTable'
+    cxx_class = 'X86ISA::intelmp::ConfigTable'
     cxx_header = 'arch/x86/bios/intelmp.hh'
 
     spec_rev = Param.UInt8(4, 'minor revision of the MP spec supported')
@@ -79,19 +79,19 @@ class X86IntelMPConfigTable(SimObject):
 
 class X86IntelMPBaseConfigEntry(SimObject):
     type = 'X86IntelMPBaseConfigEntry'
-    cxx_class = 'X86ISA::IntelMP::BaseConfigEntry'
+    cxx_class = 'X86ISA::intelmp::BaseConfigEntry'
     cxx_header = 'arch/x86/bios/intelmp.hh'
     abstract = True
 
 class X86IntelMPExtConfigEntry(SimObject):
     type = 'X86IntelMPExtConfigEntry'
-    cxx_class = 'X86ISA::IntelMP::ExtConfigEntry'
+    cxx_class = 'X86ISA::intelmp::ExtConfigEntry'
     cxx_header = 'arch/x86/bios/intelmp.hh'
     abstract = True
 
 class X86IntelMPProcessor(X86IntelMPBaseConfigEntry):
     type = 'X86IntelMPProcessor'
-    cxx_class = 'X86ISA::IntelMP::Processor'
+    cxx_class = 'X86ISA::intelmp::Processor'
     cxx_header = 'arch/x86/bios/intelmp.hh'
 
     local_apic_id = Param.UInt8(0, 'local APIC id')
@@ -108,7 +108,7 @@ class X86IntelMPProcessor(X86IntelMPBaseConfigEntry):
 
 class X86IntelMPBus(X86IntelMPBaseConfigEntry):
     type = 'X86IntelMPBus'
-    cxx_class = 'X86ISA::IntelMP::Bus'
+    cxx_class = 'X86ISA::intelmp::Bus'
     cxx_header = 'arch/x86/bios/intelmp.hh'
 
     bus_id = Param.UInt8(0, 'bus id assigned by the bios')
@@ -121,7 +121,7 @@ class X86IntelMPBus(X86IntelMPBaseConfigEntry):
 
 class X86IntelMPIOAPIC(X86IntelMPBaseConfigEntry):
     type = 'X86IntelMPIOAPIC'
-    cxx_class = 'X86ISA::IntelMP::IOAPIC'
+    cxx_class = 'X86ISA::intelmp::IOAPIC'
     cxx_header = 'arch/x86/bios/intelmp.hh'
 
     id = Param.UInt8(0, 'id of this APIC')
@@ -152,7 +152,7 @@ class X86IntelMPTriggerMode(Enum):
 
 class X86IntelMPIOIntAssignment(X86IntelMPBaseConfigEntry):
     type = 'X86IntelMPIOIntAssignment'
-    cxx_class = 'X86ISA::IntelMP::IOIntAssignment'
+    cxx_class = 'X86ISA::intelmp::IOIntAssignment'
     cxx_header = 'arch/x86/bios/intelmp.hh'
 
     interrupt_type = Param.X86IntelMPInterruptType('INT', 'type of interrupt')
@@ -172,7 +172,7 @@ class X86IntelMPIOIntAssignment(X86IntelMPBaseConfigEntry):
 
 class X86IntelMPLocalIntAssignment(X86IntelMPBaseConfigEntry):
     type = 'X86IntelMPLocalIntAssignment'
-    cxx_class = 'X86ISA::IntelMP::LocalIntAssignment'
+    cxx_class = 'X86ISA::intelmp::LocalIntAssignment'
     cxx_header = 'arch/x86/bios/intelmp.hh'
 
     interrupt_type = Param.X86IntelMPInterruptType('INT', 'type of interrupt')
@@ -198,7 +198,7 @@ class X86IntelMPAddressType(Enum):
 
 class X86IntelMPAddrSpaceMapping(X86IntelMPExtConfigEntry):
     type = 'X86IntelMPAddrSpaceMapping'
-    cxx_class = 'X86ISA::IntelMP::AddrSpaceMapping'
+    cxx_class = 'X86ISA::intelmp::AddrSpaceMapping'
     cxx_header = 'arch/x86/bios/intelmp.hh'
 
     bus_id = Param.UInt8(0, 'id of the bus the address space is mapped to')
@@ -209,7 +209,7 @@ class X86IntelMPAddrSpaceMapping(X86IntelMPExtConfigEntry):
 
 class X86IntelMPBusHierarchy(X86IntelMPExtConfigEntry):
     type = 'X86IntelMPBusHierarchy'
-    cxx_class = 'X86ISA::IntelMP::BusHierarchy'
+    cxx_class = 'X86ISA::intelmp::BusHierarchy'
     cxx_header = 'arch/x86/bios/intelmp.hh'
 
     bus_id = Param.UInt8(0, 'id of the bus being described')
@@ -224,7 +224,7 @@ class X86IntelMPRangeList(Enum):
 
 class X86IntelMPCompatAddrSpaceMod(X86IntelMPExtConfigEntry):
     type = 'X86IntelMPCompatAddrSpaceMod'
-    cxx_class = 'X86ISA::IntelMP::CompatAddrSpaceMod'
+    cxx_class = 'X86ISA::intelmp::CompatAddrSpaceMod'
     cxx_header = 'arch/x86/bios/intelmp.hh'
 
     bus_id = Param.UInt8(0, 'id of the bus being described')
diff --git a/src/arch/x86/bios/intelmp.cc b/src/arch/x86/bios/intelmp.cc
index 8e6a0b1f7b..3d8bc683a8 100644
--- a/src/arch/x86/bios/intelmp.cc
+++ b/src/arch/x86/bios/intelmp.cc
@@ -62,7 +62,7 @@
 #include "params/X86IntelMPBusHierarchy.hh"
 #include "params/X86IntelMPCompatAddrSpaceMod.hh"
 
-const char X86ISA::IntelMP::FloatingPointer::signature[] = "_MP_";
+const char X86ISA::intelmp::FloatingPointer::signature[] = "_MP_";
 
 template<class T>
 uint8_t
@@ -103,7 +103,7 @@ writeOutString(PortProxy& proxy, Addr addr, std::string str, int length)
 }
 
 Addr
-X86ISA::IntelMP::FloatingPointer::writeOut(PortProxy& proxy, Addr addr)
+X86ISA::intelmp::FloatingPointer::writeOut(PortProxy& proxy, Addr addr)
 {
     // Make sure that either a config table is present or a default
     // configuration was found but not both.
@@ -142,13 +142,13 @@ X86ISA::IntelMP::FloatingPointer::writeOut(PortProxy& proxy, Addr addr)
     return 16;
 }
 
-X86ISA::IntelMP::FloatingPointer::FloatingPointer(const Params &p) :
+X86ISA::intelmp::FloatingPointer::FloatingPointer(const Params &p) :
     SimObject(p), tableAddr(0), specRev(p.spec_rev),
     defaultConfig(p.default_config), imcrPresent(p.imcr_present)
 {}
 
 Addr
-X86ISA::IntelMP::BaseConfigEntry::writeOut(PortProxy& proxy,
+X86ISA::intelmp::BaseConfigEntry::writeOut(PortProxy& proxy,
         Addr addr, uint8_t &checkSum)
 {
     proxy.writeBlob(addr, &type, 1);
@@ -156,13 +156,13 @@ X86ISA::IntelMP::BaseConfigEntry::writeOut(PortProxy& proxy,
     return 1;
 }
 
-X86ISA::IntelMP::BaseConfigEntry::BaseConfigEntry(
+X86ISA::intelmp::BaseConfigEntry::BaseConfigEntry(
         const Params &p, uint8_t _type) :
     SimObject(p), type(_type)
 {}
 
 Addr
-X86ISA::IntelMP::ExtConfigEntry::writeOut(PortProxy& proxy,
+X86ISA::intelmp::ExtConfigEntry::writeOut(PortProxy& proxy,
         Addr addr, uint8_t &checkSum)
 {
     proxy.writeBlob(addr, &type, 1);
@@ -172,15 +172,15 @@ X86ISA::IntelMP::ExtConfigEntry::writeOut(PortProxy& proxy,
     return 1;
 }
 
-X86ISA::IntelMP::ExtConfigEntry::ExtConfigEntry(const Params &p,
+X86ISA::intelmp::ExtConfigEntry::ExtConfigEntry(const Params &p,
         uint8_t _type, uint8_t _length) :
     SimObject(p), type(_type), length(_length)
 {}
 
-const char X86ISA::IntelMP::ConfigTable::signature[] = "PCMP";
+const char X86ISA::intelmp::ConfigTable::signature[] = "PCMP";
 
 Addr
-X86ISA::IntelMP::ConfigTable::writeOut(PortProxy& proxy, Addr addr)
+X86ISA::intelmp::ConfigTable::writeOut(PortProxy& proxy, Addr addr)
 {
     uint8_t checkSum = 0;
 
@@ -237,7 +237,7 @@ X86ISA::IntelMP::ConfigTable::writeOut(PortProxy& proxy, Addr addr)
     return offset + extOffset;
 };
 
-X86ISA::IntelMP::ConfigTable::ConfigTable(const Params &p) : SimObject(p),
+X86ISA::intelmp::ConfigTable::ConfigTable(const Params &p) : SimObject(p),
     specRev(p.spec_rev), oemID(p.oem_id), productID(p.product_id),
     oemTableAddr(p.oem_table_addr), oemTableSize(p.oem_table_size),
     localApic(p.local_apic),
@@ -245,7 +245,7 @@ X86ISA::IntelMP::ConfigTable::ConfigTable(const Params &p) : SimObject(p),
 {}
 
 Addr
-X86ISA::IntelMP::Processor::writeOut(
+X86ISA::intelmp::Processor::writeOut(
         PortProxy& proxy, Addr addr, uint8_t &checkSum)
 {
     BaseConfigEntry::writeOut(proxy, addr, checkSum);
@@ -261,7 +261,7 @@ X86ISA::IntelMP::Processor::writeOut(
     return 20;
 }
 
-X86ISA::IntelMP::Processor::Processor(const Params &p) : BaseConfigEntry(p, 0),
+X86ISA::intelmp::Processor::Processor(const Params &p) : BaseConfigEntry(p, 0),
     localApicID(p.local_apic_id), localApicVersion(p.local_apic_version),
     cpuFlags(0), cpuSignature(0), featureFlags(p.feature_flags)
 {
@@ -276,7 +276,7 @@ X86ISA::IntelMP::Processor::Processor(const Params &p) : BaseConfigEntry(p, 0),
 }
 
 Addr
-X86ISA::IntelMP::Bus::writeOut(
+X86ISA::intelmp::Bus::writeOut(
         PortProxy& proxy, Addr addr, uint8_t &checkSum)
 {
     BaseConfigEntry::writeOut(proxy, addr, checkSum);
@@ -285,12 +285,12 @@ X86ISA::IntelMP::Bus::writeOut(
     return 8;
 }
 
-X86ISA::IntelMP::Bus::Bus(const Params &p) : BaseConfigEntry(p, 1),
+X86ISA::intelmp::Bus::Bus(const Params &p) : BaseConfigEntry(p, 1),
     busID(p.bus_id), busType(p.bus_type)
 {}
 
 Addr
-X86ISA::IntelMP::IOAPIC::writeOut(
+X86ISA::intelmp::IOAPIC::writeOut(
         PortProxy& proxy, Addr addr, uint8_t &checkSum)
 {
     BaseConfigEntry::writeOut(proxy, addr, checkSum);
@@ -301,7 +301,7 @@ X86ISA::IntelMP::IOAPIC::writeOut(
     return 8;
 }
 
-X86ISA::IntelMP::IOAPIC::IOAPIC(const Params &p) : BaseConfigEntry(p, 2),
+X86ISA::intelmp::IOAPIC::IOAPIC(const Params &p) : BaseConfigEntry(p, 2),
     id(p.id), version(p.version), flags(0), address(p.address)
 {
     if (p.enable)
@@ -309,7 +309,7 @@ X86ISA::IntelMP::IOAPIC::IOAPIC(const Params &p) : BaseConfigEntry(p, 2),
 }
 
 Addr
-X86ISA::IntelMP::IntAssignment::writeOut(
+X86ISA::intelmp::IntAssignment::writeOut(
         PortProxy& proxy, Addr addr, uint8_t &checkSum)
 {
     BaseConfigEntry::writeOut(proxy, addr, checkSum);
@@ -322,20 +322,20 @@ X86ISA::IntelMP::IntAssignment::writeOut(
     return 8;
 }
 
-X86ISA::IntelMP::IOIntAssignment::IOIntAssignment(const Params &p) :
+X86ISA::intelmp::IOIntAssignment::IOIntAssignment(const Params &p) :
     IntAssignment(p, p.interrupt_type, p.polarity, p.trigger, 3,
             p.source_bus_id, p.source_bus_irq,
             p.dest_io_apic_id, p.dest_io_apic_intin)
 {}
 
-X86ISA::IntelMP::LocalIntAssignment::LocalIntAssignment(const Params &p) :
+X86ISA::intelmp::LocalIntAssignment::LocalIntAssignment(const Params &p) :
     IntAssignment(p, p.interrupt_type, p.polarity, p.trigger, 4,
             p.source_bus_id, p.source_bus_irq,
             p.dest_local_apic_id, p.dest_local_apic_intin)
 {}
 
 Addr
-X86ISA::IntelMP::AddrSpaceMapping::writeOut(
+X86ISA::intelmp::AddrSpaceMapping::writeOut(
         PortProxy& proxy, Addr addr, uint8_t &checkSum)
 {
     ExtConfigEntry::writeOut(proxy, addr, checkSum);
@@ -346,14 +346,14 @@ X86ISA::IntelMP::AddrSpaceMapping::writeOut(
     return length;
 }
 
-X86ISA::IntelMP::AddrSpaceMapping::AddrSpaceMapping(const Params &p) :
+X86ISA::intelmp::AddrSpaceMapping::AddrSpaceMapping(const Params &p) :
     ExtConfigEntry(p, 128, 20),
     busID(p.bus_id), addrType(p.address_type),
     addr(p.address), addrLength(p.length)
 {}
 
 Addr
-X86ISA::IntelMP::BusHierarchy::writeOut(
+X86ISA::intelmp::BusHierarchy::writeOut(
         PortProxy& proxy, Addr addr, uint8_t &checkSum)
 {
     ExtConfigEntry::writeOut(proxy, addr, checkSum);
@@ -367,7 +367,7 @@ X86ISA::IntelMP::BusHierarchy::writeOut(
     return length;
 }
 
-X86ISA::IntelMP::BusHierarchy::BusHierarchy(const Params &p) :
+X86ISA::intelmp::BusHierarchy::BusHierarchy(const Params &p) :
     ExtConfigEntry(p, 129, 8),
     busID(p.bus_id), info(0), parentBus(p.parent_bus)
 {
@@ -376,7 +376,7 @@ X86ISA::IntelMP::BusHierarchy::BusHierarchy(const Params &p) :
 }
 
 Addr
-X86ISA::IntelMP::CompatAddrSpaceMod::writeOut(
+X86ISA::intelmp::CompatAddrSpaceMod::writeOut(
         PortProxy& proxy, Addr addr, uint8_t &checkSum)
 {
     ExtConfigEntry::writeOut(proxy, addr, checkSum);
@@ -386,7 +386,7 @@ X86ISA::IntelMP::CompatAddrSpaceMod::writeOut(
     return length;
 }
 
-X86ISA::IntelMP::CompatAddrSpaceMod::CompatAddrSpaceMod(const Params &p) :
+X86ISA::intelmp::CompatAddrSpaceMod::CompatAddrSpaceMod(const Params &p) :
     ExtConfigEntry(p, 130, 8),
     busID(p.bus_id), mod(0), rangeList(p.range_list)
 {
diff --git a/src/arch/x86/bios/intelmp.hh b/src/arch/x86/bios/intelmp.hh
index 6e97047c33..837fc5cbc6 100644
--- a/src/arch/x86/bios/intelmp.hh
+++ b/src/arch/x86/bios/intelmp.hh
@@ -42,6 +42,7 @@
 #include <vector>
 
 #include "base/bitfield.hh"
+#include "base/compiler.hh"
 #include "enums/X86IntelMPAddressType.hh"
 #include "enums/X86IntelMPInterruptType.hh"
 #include "enums/X86IntelMPPolarity.hh"
@@ -80,7 +81,8 @@ uint8_t writeOutString(PortProxy& proxy, Addr addr, std::string str,
 namespace X86ISA
 {
 
-namespace IntelMP
+GEM5_DEPRECATED_NAMESPACE(IntelMP, intelmp);
+namespace intelmp
 {
 
 class FloatingPointer : public SimObject
diff --git a/src/arch/x86/fs_workload.hh b/src/arch/x86/fs_workload.hh
index 787c70270f..c27b96ee7c 100644
--- a/src/arch/x86/fs_workload.hh
+++ b/src/arch/x86/fs_workload.hh
@@ -58,13 +58,15 @@ namespace smbios
 class SMBiosTable;
 
 } // namespace smbios
-namespace IntelMP
+
+GEM5_DEPRECATED_NAMESPACE(IntelMP, intelmp);
+namespace intelmp
 {
 
 class FloatingPointer;
 class ConfigTable;
 
-} // namespace IntelMP
+} // namespace intelmp
 
 void installSegDesc(ThreadContext *tc, SegmentRegIndex seg,
                     SegDescriptor desc, bool longmode);
@@ -81,8 +83,8 @@ class FsWorkload : public KernelWorkload
   protected:
 
     smbios::SMBiosTable *smbiosTable;
-    IntelMP::FloatingPointer *mpFloatingPointer;
-    IntelMP::ConfigTable *mpConfigTable;
+    intelmp::FloatingPointer *mpFloatingPointer;
+    intelmp::ConfigTable *mpConfigTable;
     ACPI::RSDP *rsdp;
 
     void writeOutSMBiosTable(Addr header,