arch-riscv: Add riscv pmp support

This change adds the pmp (physical memory protection)
feature of riscv previliged isa.

Change-Id: Ica701223cfc1be91a0bf953e6a3df6d72d6d3130
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43945
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Peter Yuen <petery.hin@huawei.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/riscv/SConscript

@@ -52,6 +52,7 @@ if env['TARGET_ISA'] == 'riscv':
     Source('pagetable.cc')
     Source('pagetable_walker.cc')
     Source('pma_checker.cc')
+    Source('pmp.cc')
     Source('reg_abi.cc')
     Source('remote_gdb.cc')
     Source('tlb.cc')
@@ -63,6 +64,7 @@ if env['TARGET_ISA'] == 'riscv':
     Source('bare_metal/fs_workload.cc')
 
     SimObject('PMAChecker.py')
+    SimObject('PMP.py')
     SimObject('RiscvFsWorkload.py')
     SimObject('RiscvInterrupts.py')
     SimObject('RiscvISA.py')
@@ -72,6 +74,7 @@ if env['TARGET_ISA'] == 'riscv':
 
     DebugFlag('RiscvMisc')
     DebugFlag('TLBVerbose')
+    DebugFlag('PMP')
     DebugFlag('PageTableWalker', \
               "Page table walker state machine debugging")