Merge vm1.(none):/home/stever/bk/newmem

into  vm1.(none):/home/stever/bk/newmem-py

src/python/m5/__init__.py:
src/sim/syscall_emul.cc:
    Hand merge.

--HG--
extra : convert_revision : e2542735323e648383c89382421d98a7d1d761bf

src/python/m5/objects/AlphaConsole.py

@@ -1,4 +1,4 @@
-from m5 import *
+from m5.config import *
 from Device import BasicPioDevice
 
 class AlphaConsole(BasicPioDevice):

src/python/m5/objects/AlphaFullCPU.py

@@ -1,4 +1,5 @@
-from m5 import *
+from m5 import build_env
+from m5.config import *
 from BaseCPU import BaseCPU
 
 class DerivAlphaFullCPU(BaseCPU):

src/python/m5/objects/AlphaTLB.py

@@ -1,4 +1,4 @@
-from m5 import *
+from m5.config import *
 class AlphaTLB(SimObject):
     type = 'AlphaTLB'
     abstract = True

src/python/m5/objects/BadDevice.py

@@ -1,4 +1,4 @@
-from m5 import *
+from m5.config import *
 from Device import BasicPioDevice
 
 class BadDevice(BasicPioDevice):

src/python/m5/objects/BaseCPU.py

@@ -1,4 +1,6 @@
-from m5 import *
+from m5 import build_env
+from m5.config import *
+
 class BaseCPU(SimObject):
     type = 'BaseCPU'
     abstract = True

src/python/m5/objects/BaseCache.py

@@ -1,4 +1,4 @@
-from m5 import *
+from m5.config import *
 from BaseMem import BaseMem
 
 class Prefetch(Enum): vals = ['none', 'tagged', 'stride', 'ghb']

src/python/m5/objects/Bridge.py

@@ -1,4 +1,4 @@
-from m5 import *
+from m5.config import *
 from MemObject import MemObject
 
 class Bridge(MemObject):

src/python/m5/objects/Bus.py

@@ -1,4 +1,4 @@
-from m5 import *
+from m5.config import *
 from MemObject import MemObject
 
 class Bus(MemObject):

src/python/m5/objects/CoherenceProtocol.py

@@ -1,4 +1,4 @@
-from m5 import *
+from m5.config import *
 class Coherence(Enum): vals = ['uni', 'msi', 'mesi', 'mosi', 'moesi']
 
 class CoherenceProtocol(SimObject):

src/python/m5/objects/Device.py

@@ -1,4 +1,4 @@
-from m5 import *
+from m5.config import *
 from MemObject import MemObject
 
 class PioDevice(MemObject):

src/python/m5/objects/DiskImage.py

@@ -1,4 +1,4 @@
-from m5 import *
+from m5.config import *
 class DiskImage(SimObject):
     type = 'DiskImage'
     abstract = True

src/python/m5/objects/Ethernet.py

@@ -1,4 +1,5 @@
-from m5 import *
+from m5 import build_env
+from m5.config import *
 from Device import DmaDevice
 from Pci import PciDevice
 

src/python/m5/objects/Ide.py

@@ -1,4 +1,4 @@
-from m5 import *
+from m5.config import *
 from Pci import PciDevice
 
 class IdeID(Enum): vals = ['master', 'slave']

src/python/m5/objects/IntrControl.py

@@ -1,4 +1,4 @@
-from m5 import *
+from m5.config import *
 class IntrControl(SimObject):
     type = 'IntrControl'
     cpu = Param.BaseCPU(Parent.any, "the cpu")

src/python/m5/objects/MemObject.py

@@ -1,4 +1,4 @@
-from m5 import *
+from m5.config import *
 
 class MemObject(SimObject):
     type = 'MemObject'

src/python/m5/objects/MemTest.py

@@ -1,4 +1,4 @@
-from m5 import *
+from m5.config import *
 class MemTest(SimObject):
     type = 'MemTest'
     cache = Param.BaseCache("L1 cache")

src/python/m5/objects/Pci.py

@@ -1,4 +1,4 @@
-from m5 import *
+from m5.config import *
 from Device import BasicPioDevice, DmaDevice
 
 class PciConfigData(SimObject):

src/python/m5/objects/PhysicalMemory.py

@@ -1,4 +1,4 @@
-from m5 import *
+from m5.config import *
 from MemObject import *
 
 class PhysicalMemory(MemObject):

src/python/m5/objects/Platform.py

@@ -1,4 +1,4 @@
-from m5 import *
+from m5.config import *
 class Platform(SimObject):
     type = 'Platform'
     abstract = True

src/python/m5/objects/Process.py

@@ -1,4 +1,4 @@
-from m5 import *
+from m5.config import *
 class Process(SimObject):
     type = 'Process'
     abstract = True

src/python/m5/objects/Repl.py

@@ -1,4 +1,4 @@
-from m5 import *
+from m5.config import *
 class Repl(SimObject):
     type = 'Repl'
     abstract = True

src/python/m5/objects/Root.py

@@ -1,4 +1,4 @@
-from m5 import *
+from m5.config import *
 from Serialize import Serialize
 from Statistics import Statistics
 from Trace import Trace

src/python/m5/objects/SimConsole.py

@@ -1,4 +1,4 @@
-from m5 import *
+from m5.config import *
 class ConsoleListener(SimObject):
     type = 'ConsoleListener'
     port = Param.TcpPort(3456, "listen port")

src/python/m5/objects/SimpleDisk.py

@@ -1,4 +1,4 @@
-from m5 import *
+from m5.config import *
 class SimpleDisk(SimObject):
     type = 'SimpleDisk'
     disk = Param.DiskImage("Disk Image")

src/python/m5/objects/System.py

@@ -1,4 +1,5 @@
-from m5 import *
+from m5 import build_env
+from m5.config import *
 
 class System(SimObject):
     type = 'System'

src/python/m5/objects/Tsunami.py

@@ -1,4 +1,4 @@
-from m5 import *
+from m5.config import *
 from Device import BasicPioDevice
 from Platform import Platform
 

src/python/m5/objects/Uart.py

@@ -1,4 +1,5 @@
-from m5 import *
+from m5 import build_env
+from m5.config import *
 from Device import BasicPioDevice
 
 class Uart(BasicPioDevice):