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arch-arm: Replace TLB,TLBVerbose usage in ArmMMU

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Some ISAs (like Arm) have moved most of the translation logic into
the MMU and use the TLB simply as translation storage. It makes
sense to use the MMU debug flag for that logic and reduce the
scope of the TLB flag to TLB insertion/hits/misses

Change-Id: I2a164545c711d83d3e87075b0cb5c279eed274c9
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Giacomo Travaglini
2024-07-17 10:20:36 +01:00
parent 58bc790a09
commit 94ffe5f233
1 changed files with 18 additions and 19 deletions
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37
src/arch/arm/mmu.cc
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@@ -47,8 +47,7 @@
#include "arch/arm/table_walker.hh"
#include "arch/arm/tlb.hh"
#include "arch/arm/tlbi_op.hh"
#include "debug/TLB.hh"
#include "debug/TLBVerbose.hh"
#include "debug/MMU.hh"
#include "mem/packet_access.hh"
#include "sim/pseudo_inst.hh"
#include "sim/process.hh"
@@ -442,7 +441,7 @@ MMU::checkPermissions(TlbEntry *te, const RequestPtr &req, Mode mode,
switch ((state.dacr >> (static_cast<uint8_t>(te->domain) * 2)) & 0x3) {
case 0:
stats.domainFaults++;
DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x"
DPRINTF(MMU, "MMU Fault: Data abort on domain. DACR: %#x"
" domain: %#x write:%d\n", state.dacr,
static_cast<uint8_t>(te->domain), is_write);
if (is_fetch) {
@@ -485,7 +484,7 @@ MMU::checkPermissions(TlbEntry *te, const RequestPtr &req, Mode mode,
} else {
switch (ap) {
case 0:
DPRINTF(TLB, "Access permissions 0, checking rs:%#x\n",
DPRINTF(MMU, "Access permissions 0, checking rs:%#x\n",
(int)state.sctlr.rs);
if (!state.sctlr.xp) {
switch ((int)state.sctlr.rs) {
@@ -539,7 +538,7 @@ MMU::checkPermissions(TlbEntry *te, const RequestPtr &req, Mode mode,
(state.securityState == SecurityState::Secure &&
te->ns && state.scr.sif))) {
stats.permsFaults++;
DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d "
DPRINTF(MMU, "MMU Fault: Prefetch abort on permission check. AP:%d "
"priv:%d write:%d ns:%d sif:%d sctlr.afe: %d \n",
ap, is_priv, is_write, te->ns,
state.scr.sif, state.sctlr.afe);
@@ -551,7 +550,7 @@ MMU::checkPermissions(TlbEntry *te, const RequestPtr &req, Mode mode,
state.isStage2, tran_method);
} else if (abt | hapAbt) {
stats.permsFaults++;
DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d priv:%d"
DPRINTF(MMU, "MMU Fault: Data abort on permission check. AP:%d priv:%d"
" write:%d\n", ap, is_priv, is_write);
return std::make_shared<DataAbort>(
vaddr, te->domain, is_write,
@@ -653,7 +652,7 @@ MMU::checkPermissions64(TlbEntry *te, const RequestPtr &req, Mode mode,
if (!grant) {
if (is_fetch) {
stats.permsFaults++;
DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. "
DPRINTF(MMU, "MMU Fault: Prefetch abort on permission check. "
"ns:%d scr.sif:%d sctlr.afe: %d\n",
te->ns, state.scr.sif, state.sctlr.afe);
// Use PC value instead of vaddr because vaddr might be aligned to
@@ -664,7 +663,7 @@ MMU::checkPermissions64(TlbEntry *te, const RequestPtr &req, Mode mode,
state.isStage2, TranMethod::LpaeTran);
} else {
stats.permsFaults++;
DPRINTF(TLB, "TLB Fault: Data abort on permission check."
DPRINTF(MMU, "MMU Fault: Data abort on permission check."
"ns:%d", te->ns);
return std::make_shared<DataAbort>(
vaddr_tainted, te->domain,
@@ -699,7 +698,7 @@ MMU::s2PermBits64(TlbEntry *te, const RequestPtr &req, Mode mode,
xn = true;
}
DPRINTF(TLBVerbose,
DPRINTF(MMU,
"Checking S2 permissions: hap:%d, xn:%d, pxn:%d, r:%d, "
"w:%d, x:%d\n", te->hap, xn, pxn, r, w, x);
@@ -731,7 +730,7 @@ MMU::s1PermBits64(TlbEntry *te, const RequestPtr &req, Mode mode,
uint8_t xn = te->xn;
uint8_t pxn = te->pxn;
DPRINTF(TLBVerbose, "Checking S1 permissions: ap:%d, xn:%d, pxn:%d, r:%d, "
DPRINTF(MMU, "Checking S1 permissions: ap:%d, xn:%d, pxn:%d, r:%d, "
"w:%d, x:%d, is_priv: %d, wxn: %d\n", ap, xn,
pxn, r, w, x, is_priv, wxn);
@@ -947,7 +946,7 @@ MMU::translateMmuOff(ThreadContext *tc, const RequestPtr &req, Mode mode,
temp_te.outerShareable = false;
}
temp_te.setAttributes(long_desc_format);
DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable: "
DPRINTF(MMU, "(No MMU) setting memory attributes: shareable: "
"%d, innerAttrs: %d, outerAttrs: %d, stage2: %d\n",
temp_te.shareable, temp_te.innerAttrs, temp_te.outerAttrs,
state.isStage2);
@@ -978,7 +977,7 @@ MMU::translateMmuOn(ThreadContext* tc, const RequestPtr &req, Mode mode,
// request that triggered the translation
if (isCompleteTranslation(te)) {
// Set memory attributes
DPRINTF(TLBVerbose,
DPRINTF(MMU,
"Setting memory attributes: shareable: %d, innerAttrs: %d, "
"outerAttrs: %d, mtype: %d, stage2: %d\n",
te->shareable, te->innerAttrs, te->outerAttrs,
@@ -1048,13 +1047,13 @@ MMU::translateFs(const RequestPtr &req, ThreadContext *tc, Mode mode,
TranMethod tran_method = long_desc_format ?
TranMethod::LpaeTran : TranMethod::VmsaTran;
DPRINTF(TLBVerbose,
DPRINTF(MMU,
"CPSR is priv:%d UserMode:%d secure:%d S1S2NsTran:%d\n",
state.isPriv, flags & UserMode,
state.securityState == SecurityState::Secure,
tran_type & S1S2NsTran);
DPRINTF(TLB, "translateFs addr %#x, mode %d, st2 %d, scr %#x sctlr %#x "
DPRINTF(MMU, "translateFs addr %#x, mode %d, st2 %d, scr %#x sctlr %#x "
"flags %#lx tranType 0x%x\n", vaddr_tainted, mode,
state.isStage2, state.scr, state.sctlr, flags, tran_type);
@@ -1093,7 +1092,7 @@ MMU::translateFs(const RequestPtr &req, ThreadContext *tc, Mode mode,
fault = translateMmuOff(tc, req, mode, tran_type, vaddr,
long_desc_format, state);
} else {
DPRINTF(TLBVerbose, "Translating %s=%#x context=%d\n",
DPRINTF(MMU, "Translating %s=%#x context=%d\n",
state.isStage2 ? "IPA" : "VA", vaddr_tainted, state.asid);
// Translation enabled
fault = translateMmuOn(tc, req, mode, translation, delay, timing,
@@ -1199,7 +1198,7 @@ MMU::translateComplete(const RequestPtr &req, ThreadContext *tc,
else
fault = translateSe(req, tc, mode, translation, delay, true, state);
DPRINTF(TLBVerbose, "Translation returning delay=%d fault=%d\n", delay,
DPRINTF(MMU, "Translation returning delay=%d fault=%d\n", delay,
fault != NoFault);
// If we have a translation, and we're not in the middle of doing a stage
// 2 translation tell the translation that we've either finished or its
@@ -1260,7 +1259,7 @@ MMU::updateMiscReg(ThreadContext *tc,
((tran_type == state.curTranType) || stage2)) {
} else {
DPRINTF(TLBVerbose, "TLB variables changed!\n");
DPRINTF(MMU, "MMU variables changed!\n");
state.updateMiscReg(tc, tran_type);
itbStage2->setVMID(state.vmid);
@@ -1528,7 +1527,7 @@ MMU::getTE(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode,
// start translation table walk, pass variables rather than
// re-retreaving in table walker for speed
DPRINTF(TLB,
DPRINTF(MMU,
"TLB Miss: Starting hardware table walker for %#x(%d:%d)\n",
vaddr_tainted, state.asid, state.vmid);
@@ -1614,7 +1613,7 @@ MMU::getResultTe(TlbEntry **te, const RequestPtr &req,
// This case deals with an S1 hit (or bypass), followed by
// an S2 hit-but-perms issue
if (state.isStage2) {
DPRINTF(TLBVerbose, "s2TLB: reqVa %#x, reqPa %#x, fault %p\n",
DPRINTF(MMU, "s2TLB: reqVa %#x, reqPa %#x, fault %p\n",
vaddr_tainted, req->hasPaddr() ? req->getPaddr() : ~0,
fault);
if (fault != NoFault) {