arch-arm: Add arm demo board (#1478)
This demo board is a preset arm board, that can be used to run example gem5 simulations. This board doesnt simulate any known hardware. The board will be used to run benchmarks such as gapbs and npb to collect stats. The plan is to show these stats on the gem5 resources website to provide more details about the resources.
This commit is contained in:
Harshil Patel
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configs/example/gem5_library/arm-demo-ubuntu-run.py
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configs/example/gem5_library/arm-demo-ubuntu-run.py
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# Copyright (c) 2024 The Regents of the University of California
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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"""
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This script further shows an example of booting an ARM based full system Ubuntu
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disk image. This simulation boots the disk image using the ArmDemoBoard.
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Usage
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-----
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```bash
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scons build/ARM/gem5.opt -j $(nproc)
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./build/ARM/gem5.opt configs/example/gem5_library/arm-demo-ubuntu-run.py
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```
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"""
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import argparse
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from gem5.isas import ISA
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from gem5.prebuilt.demo.arm_demo_board import ArmDemoBoard
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from gem5.resources.resource import obtain_resource
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from gem5.simulate.exit_event import ExitEvent
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from gem5.simulate.simulator import Simulator
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from gem5.utils.requires import requires
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# This runs a check to ensure the gem5 binary interpreting this file is compiled to include the ARM ISA.
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requires(isa_required=ISA.ARM)
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parser = argparse.ArgumentParser(
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description="An example configuration script to run the ArmDemoBoard."
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)
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parser.add_argument(
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"--use-kvm",
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action="store_true",
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help="Use KVM cores instead of Timing.",
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)
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args = parser.parse_args()
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board = ArmDemoBoard(use_kvm=args.use_kvm)
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board.set_workload(
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obtain_resource(
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"arm-ubuntu-24.04-boot-with-systemd", resource_version="2.0.0"
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)
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)
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def exit_event_handler():
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print("First exit: kernel booted")
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yield False # gem5 is now executing systemd startup
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print("Second exit: Started `after_boot.sh` script")
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# The after_boot.sh script is executed after the kernel and systemd have
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# booted.
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yield False # gem5 is now executing the `after_boot.sh` script
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print("Third exit: Finished `after_boot.sh` script")
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# The after_boot.sh script will run a script if it is passed via
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# m5 readfile. This is the last exit event before the simulation exits.
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yield True
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# We define the system with the aforementioned system defined.
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simulator = Simulator(
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board=board,
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on_exit_event={
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ExitEvent.EXIT: exit_event_handler(),
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},
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)
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simulator.run()
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@@ -280,6 +280,7 @@ PySource('gem5.components.processors',
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PySource('gem5.prebuilt', 'gem5/prebuilt/__init__.py')
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PySource('gem5.prebuilt.demo', 'gem5/prebuilt/demo/__init__.py')
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PySource('gem5.prebuilt.demo', 'gem5/prebuilt/demo/x86_demo_board.py')
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PySource('gem5.prebuilt.demo', 'gem5/prebuilt/demo/arm_demo_board.py')
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PySource('gem5.prebuilt.riscvmatched',
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'gem5/prebuilt/riscvmatched/__init__.py')
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PySource('gem5.prebuilt.riscvmatched',
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112
src/python/gem5/prebuilt/demo/arm_demo_board.py
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src/python/gem5/prebuilt/demo/arm_demo_board.py
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@@ -0,0 +1,112 @@
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# Copyright (c) 2024 The Regents of the University of California
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from m5.objects import (
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ArmDefaultRelease,
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VExpress_GEM5_Foundation,
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VExpress_GEM5_V1,
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)
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from m5.util import warn
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from ...components.boards.arm_board import ArmBoard
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from ...components.cachehierarchies.classic.private_l1_shared_l2_cache_hierarchy import (
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PrivateL1SharedL2CacheHierarchy,
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)
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from ...components.memory import DualChannelDDR4_2400
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from ...components.processors.cpu_types import CPUTypes
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from ...components.processors.simple_processor import SimpleProcessor
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from ...isas import ISA
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from ...utils.requires import requires
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class ArmDemoBoard(ArmBoard):
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"""
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This prebuilt ARM board is used for demonstration purposes. It simulates an
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ARM 3GHz dual-core system with a 4GiB DDR4_2400 memory system. It uses
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a PrivateL1SharedL2CacheHierarchy with l1d and l1i caches set to 64KiB and
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l2 shared cache set to 8MiB
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**DISCLAIMER**: This board is solely for demonstration purposes. This board
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is not known to be representative of any real-world system or produce
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reliable statistical results.
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"""
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def __init__(self, use_kvm: bool = False) -> None:
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"""
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:param use_kvm: If True, the board will use a SimpleProcessor
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with cpu type of CPUTypes.KVM. If False, the board will use a SimpleProcessor with
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a cpu type of CPUTypes.TIMING.
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"""
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requires(
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isa_required=ISA.ARM,
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)
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warn(
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"The ARMDemoBoard is solely for demonstration purposes. "
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"This board is not known to be be representative of any "
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"real-world system. Use with caution."
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)
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cache_hierarchy = PrivateL1SharedL2CacheHierarchy(
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l1d_size="64KiB", l1i_size="64KiB", l2_size="8MiB"
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)
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# Note: Normally a system with these specification would have 1
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# GiB for memory but because some benchmarks would not run with
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# 1 GiB of memory so we have set it to 4 GiB.
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memory = DualChannelDDR4_2400(size="4GiB")
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if use_kvm:
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processor = SimpleProcessor(
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cpu_type=CPUTypes.KVM, num_cores=2, isa=ISA.ARM
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)
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# The ArmBoard requires a `release` to be specified. This adds all the
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# extensions or features to the system. We are setting this to for_kvm()
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# to enable KVM simulation.
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release = ArmDefaultRelease.for_kvm()
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# The platform sets up the memory ranges of all the on-chip and off-chip
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# devices present on the ARM system. ARM KVM only works with VExpress_GEM5_V1
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# on the ArmBoard at the moment.
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platform = VExpress_GEM5_V1()
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else:
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processor = SimpleProcessor(
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cpu_type=CPUTypes.TIMING, num_cores=2, isa=ISA.ARM
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)
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release = ArmDefaultRelease()
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# The platform sets up the memory ranges of all the on-chip and off-chip
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# devices present on the ARM system.
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platform = VExpress_GEM5_Foundation()
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super().__init__(
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clk_freq="3GHz",
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processor=processor,
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memory=memory,
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cache_hierarchy=cache_hierarchy,
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release=release,
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platform=platform,
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)
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