gpu-compute: Create CU's ports in the standard way
The CU would initialize its ports in getMasterPort(), which is not desirable as getMasterPort() may be called several times for the same port. This can lead to a fatal if the CU expects to only create a single port of a given type, and may lead to other issues where stat names are duplicated. This change instantiates and initializes the CU's ports in the CU constructor using the CU params. The index field is also removed from the CU's ports because the base class already has an ID field, which will be set to the default value in the base class's constructor for scalar ports. It doesn't make sense for scalar port's to take an index because they are scalar, so we let the base class initialize the ID to the invalid port ID. Change-Id: Id18386f5f53800a6447d968380676d8fd9bac9df Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32836 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
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committed by
Anthony Gutierrez
parent
a7530f798b
commit
94000aefe6
@@ -174,24 +174,24 @@ FetchUnit::initiateFetch(Wavefront *wavefront)
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computeUnit.shader->gpuTc,
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false, pkt->senderState);
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if (computeUnit.sqcTLBPort->isStalled()) {
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assert(computeUnit.sqcTLBPort->retries.size() > 0);
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if (computeUnit.sqcTLBPort.isStalled()) {
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assert(computeUnit.sqcTLBPort.retries.size() > 0);
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DPRINTF(GPUTLB, "Failed to send TLB req for FETCH addr %#x\n",
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vaddr);
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computeUnit.sqcTLBPort->retries.push_back(pkt);
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} else if (!computeUnit.sqcTLBPort->sendTimingReq(pkt)) {
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computeUnit.sqcTLBPort.retries.push_back(pkt);
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} else if (!computeUnit.sqcTLBPort.sendTimingReq(pkt)) {
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// Stall the data port;
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// No more packet is issued till
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// ruby indicates resources are freed by
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// a recvReqRetry() call back on this port.
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computeUnit.sqcTLBPort->stallPort();
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computeUnit.sqcTLBPort.stallPort();
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DPRINTF(GPUTLB, "Failed to send TLB req for FETCH addr %#x\n",
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vaddr);
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computeUnit.sqcTLBPort->retries.push_back(pkt);
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computeUnit.sqcTLBPort.retries.push_back(pkt);
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} else {
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DPRINTF(GPUTLB, "sent FETCH translation request for %#x\n", vaddr);
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}
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@@ -200,7 +200,7 @@ FetchUnit::initiateFetch(Wavefront *wavefront)
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new TheISA::GpuTLB::TranslationState(BaseTLB::Execute,
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computeUnit.shader->gpuTc);
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computeUnit.sqcTLBPort->sendFunctional(pkt);
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computeUnit.sqcTLBPort.sendFunctional(pkt);
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TheISA::GpuTLB::TranslationState *sender_state =
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safe_cast<TheISA::GpuTLB::TranslationState*>(pkt->senderState);
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@@ -257,8 +257,8 @@ FetchUnit::fetch(PacketPtr pkt, Wavefront *wavefront)
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if (timingSim) {
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// translation is done. Send the appropriate timing memory request.
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if (!computeUnit.sqcPort->sendTimingReq(pkt)) {
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computeUnit.sqcPort->retries.push_back(std::make_pair(pkt,
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if (!computeUnit.sqcPort.sendTimingReq(pkt)) {
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computeUnit.sqcPort.retries.push_back(std::make_pair(pkt,
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wavefront));
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DPRINTF(GPUPort, "CU%d: WF[%d][%d]: Fetch addr %#x failed!\n",
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@@ -270,7 +270,7 @@ FetchUnit::fetch(PacketPtr pkt, Wavefront *wavefront)
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pkt->req->getPaddr());
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}
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} else {
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computeUnit.sqcPort->sendFunctional(pkt);
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computeUnit.sqcPort.sendFunctional(pkt);
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processFetchReturn(pkt);
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}
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}
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