ARM: mark msr/mrs instructions as SerializeBefore/After

Since miscellaneous registers bypass wakeup logic, force serialization
to resolve data dependencies through them
* * *
ARM: adding non-speculative/serialize flags for instructions change CPSR

src/cpu/base_dyn_inst_impl.hh

@@ -321,6 +321,8 @@ template <class Impl>
 void
 BaseDynInst<Impl>::markSrcRegReady()
 {
+    DPRINTF(IQ, "[sn:%lli] has %d ready out of %d sources. RTI %d)\n",
+            seqNum, readyRegs+1, numSrcRegs(), readyToIssue());
     if (++readyRegs == numSrcRegs()) {
         setCanIssue();
     }

src/cpu/o3/iew_impl.hh

@@ -1192,6 +1192,7 @@ DefaultIEW<Impl>::executeInsts()
     }
 
     // Uncomment this if you want to see all available instructions.
+    // @todo This doesn't actually work anymore, we should fix it.
 //    printAvailableInsts();
 
     // Execute/writeback any instructions that are available.

src/cpu/o3/inst_queue_impl.hh

@@ -896,6 +896,8 @@ InstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst)
         // handled by the IQ and thus have no dependency graph entry.
         // @todo Figure out a cleaner way to handle this.
         if (dest_reg >= numPhysRegs) {
+            DPRINTF(IQ, "dest_reg :%d, numPhysRegs: %d\n", dest_reg,
+                    numPhysRegs);
             continue;
         }
 
@@ -907,8 +909,8 @@ InstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst)
         DynInstPtr dep_inst = dependGraph.pop(dest_reg);
 
         while (dep_inst) {
-            DPRINTF(IQ, "Waking up a dependent instruction, PC%#x.\n",
-                    dep_inst->readPC());
+            DPRINTF(IQ, "Waking up a dependent instruction, [sn:%lli] "
+                    "PC%#x.\n", dep_inst->seqNum, dep_inst->readPC());
 
             // Might want to give more information to the instruction
             // so that it knows which of its source registers is