diff --git a/src/Doxyfile b/src/Doxyfile
index 1ff46c8da2..dd52c258e1 100644
--- a/src/Doxyfile
+++ b/src/Doxyfile
@@ -1285,7 +1285,7 @@ INCLUDE_FILE_PATTERNS  =
 # omitted =1 is assumed.
 
 PREDEFINED             = DOXYGEN_SHOULD_SKIP_THIS \
-                         THE_ISA
+                         IS_NULL_ISA
 
 # If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then 
 # this tag can be used to specify a list of macro names that should be expanded. 
diff --git a/src/SConscript b/src/SConscript
index fd3981b703..f79a6576c2 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -739,8 +739,7 @@ for opt in export_vars:
 def makeTheISA(source, target, env):
     isas = [ src.get_contents().decode('utf-8') for src in source ]
     target_isa = env['TARGET_ISA']
-    def define(isa):
-        return str(isa.upper()) + '_ISA'
+    is_null_isa = '1' if (target_isa.lower() == 'null') else '0'
 
     def namespace(isa):
         return isa[0].upper() + isa[1:].lower() + 'ISA'
@@ -753,21 +752,16 @@ def makeTheISA(source, target, env):
 
 ''')
 
-    # create defines for the preprocessing and compile-time determination
-    for i,isa in enumerate(isas):
-        code('#define $0 $1', define(isa), i + 1)
-    code()
-
     # create an enum for any run-time determination of the ISA, we
     # reuse the same name as the namespaces
     code('enum class Arch {')
     for isa in isas:
-        code('  $0 = $1,', namespace(isa), define(isa))
+        code('  $0,', namespace(isa))
     code('};')
 
     code('''
 
-#define THE_ISA ${{define(target_isa)}}
+#define IS_NULL_ISA ${{is_null_isa}}
 #define TheISA ${{namespace(target_isa)}}
 
 #endif // __CONFIG_THE_ISA_HH__''')
diff --git a/src/arch/SConscript b/src/arch/SConscript
index e545892819..fb9f463717 100644
--- a/src/arch/SConscript
+++ b/src/arch/SConscript
@@ -51,7 +51,7 @@ Import('*')
 # ISA "switch header" generation.
 #
 # Auto-generate arch headers that include the right ISA-specific
-# header based on the setting of THE_ISA preprocessor variable.
+# header based on the setting of TARGET_ISA setting.
 #
 #################################################################
 
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 724da06712..8a95f70976 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -47,7 +47,7 @@
 // Before we do anything else, check if this build is the NULL ISA,
 // and if so stop here
 #include "config/the_isa.hh"
-#if THE_ISA == NULL_ISA
+#if IS_NULL_ISA
 #error Including BaseCPU in a system without CPU support
 #else
 #include "arch/generic/interrupts.hh"
@@ -625,6 +625,6 @@ class BaseCPU : public ClockedObject
 
 } // namespace gem5
 
-#endif // THE_ISA == NULL_ISA
+#endif // !IS_NULL_ISA
 
 #endif // __CPU_BASE_HH__
diff --git a/src/dev/net/dist_iface.cc b/src/dev/net/dist_iface.cc
index 6a44eba2f5..d0cfd88cce 100644
--- a/src/dev/net/dist_iface.cc
+++ b/src/dev/net/dist_iface.cc
@@ -868,7 +868,7 @@ DistIface::toggleSync(ThreadContext *tc)
         // stop point.  Suspend execution of all local thread contexts.
         // Dist-gem5 will reactivate all thread contexts when everyone has
         // reached the sync stop point.
-#if THE_ISA != NULL_ISA
+#if !IS_NULL_ISA
         for (auto *tc: primary->sys->threads) {
             if (tc->status() == ThreadContext::Active)
                 tc->quiesce();
@@ -882,7 +882,7 @@ DistIface::toggleSync(ThreadContext *tc)
         // nodes to prevent causality errors.  We can also schedule CPU
         // activation here, since we know exactly when the next sync will
         // occur.
-#if THE_ISA != NULL_ISA
+#if !IS_NULL_ISA
         for (auto *tc: primary->sys->threads) {
             if (tc->status() == ThreadContext::Active)
                 tc->quiesceTick(primary->syncEvent->when() + 1);
diff --git a/src/sim/system.cc b/src/sim/system.cc
index 12cde39c2c..0cb580563f 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -54,7 +54,7 @@
 #include "cpu/kvm/base.hh"
 #include "cpu/kvm/vm.hh"
 #endif
-#if THE_ISA != NULL_ISA
+#if !IS_NULL_ISA
 #include "cpu/base.hh"
 #endif
 #include "cpu/thread_context.hh"
@@ -77,7 +77,7 @@ std::vector<System *> System::systemList;
 void
 System::Threads::Thread::resume()
 {
-#   if THE_ISA != NULL_ISA
+#   if !IS_NULL_ISA
     DPRINTFS(Quiesce, context->getCpuPtr(), "activating\n");
     context->activate();
 #   endif
@@ -133,7 +133,7 @@ System::Threads::replace(ThreadContext *tc, ContextID id)
 {
     auto &t = thread(id);
     panic_if(!t.context, "Can't replace a context which doesn't exist.");
-#   if THE_ISA != NULL_ISA
+#   if !IS_NULL_ISA
     if (t.resumeEvent->scheduled()) {
         Tick when = t.resumeEvent->when();
         t.context->getCpuPtr()->deschedule(t.resumeEvent);
@@ -171,7 +171,7 @@ void
 System::Threads::quiesce(ContextID id)
 {
     auto &t = thread(id);
-#   if THE_ISA != NULL_ISA
+#   if !IS_NULL_ISA
     [[maybe_unused]] BaseCPU *cpu = t.context->getCpuPtr();
     DPRINTFS(Quiesce, cpu, "quiesce()\n");
 #   endif
@@ -181,7 +181,7 @@ System::Threads::quiesce(ContextID id)
 void
 System::Threads::quiesceTick(ContextID id, Tick when)
 {
-#   if THE_ISA != NULL_ISA
+#   if !IS_NULL_ISA
     auto &t = thread(id);
     BaseCPU *cpu = t.context->getCpuPtr();
 
@@ -449,7 +449,7 @@ System::unserialize(CheckpointIn &cp)
                 !when || !t.resumeEvent) {
             continue;
         }
-#       if THE_ISA != NULL_ISA
+#       if !IS_NULL_ISA
         t.context->getCpuPtr()->schedule(t.resumeEvent, when);
 #       endif
     }
diff --git a/src/sim/workload.cc b/src/sim/workload.cc
index d208a58a3d..e9529bedc4 100644
--- a/src/sim/workload.cc
+++ b/src/sim/workload.cc
@@ -44,7 +44,7 @@ Workload::registerThreadContext(ThreadContext *tc)
     panic_if(!success, "Failed to add thread context %d.",
             tc->contextId());
 
-#   if THE_ISA != NULL_ISA
+#   if !IS_NULL_ISA
     if (gdb)
         gdb->addThreadContext(tc);
 #   endif
@@ -66,7 +66,7 @@ Workload::replaceThreadContext(ThreadContext *tc)
         panic_if(!success,
                 "Failed to insert replacement thread context %d.", id);
 
-#       if THE_ISA != NULL_ISA
+#       if !IS_NULL_ISA
         if (gdb)
             gdb->replaceThreadContext(tc);
 #       endif
@@ -79,7 +79,7 @@ Workload::replaceThreadContext(ThreadContext *tc)
 bool
 Workload::trapToGdb(int signal, ContextID ctx_id)
 {
-#   if THE_ISA != NULL_ISA
+#   if !IS_NULL_ISA
     if (gdb) {
         gdb->trap(ctx_id, signal);
         return true;
@@ -93,7 +93,7 @@ Workload::startup()
 {
     SimObject::startup();
 
-#   if THE_ISA != NULL_ISA
+#   if !IS_NULL_ISA
     // Now that we're about to start simulation, wait for GDB connections if
     // requested.
     if (gdb && waitForRemoteGDB) {