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misc: Standardize the way create() constructs SimObjects.

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The create() method on Params structs usually instantiate SimObjects
using a constructor which takes the Params struct as a parameter
somehow. There has been a lot of needless variation in how that was
done, making it annoying to pass Params down to base classes. Some of
the different forms were:

const Params &
Params &
Params *
const Params *
Params const*

This change goes through and fixes up every constructor and every
create() method to use the const Params & form. We use a reference
because the Params struct should never be null. We use const because
neither the create method nor the consuming object should modify the
record of the parameters as they came in from the config. That would
make consuming them not idempotent, and make it impossible to tell what
the actual simulation configuration was since it would change from any
user visible form (config script, config.ini, dot pdf output).

Change-Id: I77453cba52fdcfd5f4eec92dfb0bddb5a9945f31
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35938
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2020-10-07 06:49:23 -07:00
parent aeb39c1441
commit 91d83cc8a1
822 changed files with 4078 additions and 4038 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/dev/arm/a9scu.cc
View File

@@ -43,7 +43,7 @@
#include "mem/packet_access.hh"
#include "sim/system.hh"
A9SCU::A9SCU(Params *p)
A9SCU::A9SCU(const Params &p)
: BasicPioDevice(p, 0x60)
{
}
@@ -105,7 +105,7 @@ A9SCU::write(PacketPtr pkt)
}
A9SCU *
A9SCUParams::create()
A9SCUParams::create() const
{
return new A9SCU(this);
return new A9SCU(*this);
}

2
src/dev/arm/a9scu.hh
View File

@@ -60,7 +60,7 @@ class A9SCU : public BasicPioDevice
* The constructor for RealView just registers itself with the MMU.
* @param p params structure
*/
A9SCU(Params *p);
A9SCU(const Params &p);
/**
* Handle a read to the device

2
src/dev/arm/abstract_nvm.hh
View File

@@ -54,7 +54,7 @@ class AbstractNVM : public SimObject
{
public:
AbstractNVM(const AbstractNVMParams* p): SimObject(p) {};
AbstractNVM(const AbstractNVMParams &p): SimObject(p) {};
virtual ~AbstractNVM() {};
/**

16
src/dev/arm/amba_device.cc
View File

@@ -48,23 +48,23 @@
const uint64_t AmbaVendor = ULL(0xb105f00d00000000);
AmbaPioDevice::AmbaPioDevice(const Params *p, Addr pio_size)
: BasicPioDevice(p, pio_size), ambaId(AmbaVendor | p->amba_id)
AmbaPioDevice::AmbaPioDevice(const Params &p, Addr pio_size)
: BasicPioDevice(p, pio_size), ambaId(AmbaVendor | p.amba_id)
{
}
AmbaIntDevice::AmbaIntDevice(const Params *p, Addr pio_size)
AmbaIntDevice::AmbaIntDevice(const Params &p, Addr pio_size)
: AmbaPioDevice(p, pio_size),
interrupt(p->interrupt->get()), intDelay(p->int_delay)
interrupt(p.interrupt->get()), intDelay(p.int_delay)
{
}
AmbaDmaDevice::AmbaDmaDevice(const Params *p, Addr pio_size)
: DmaDevice(p), ambaId(AmbaVendor | p->amba_id),
pioAddr(p->pio_addr), pioSize(pio_size),
pioDelay(p->pio_latency), interrupt(p->interrupt->get())
AmbaDmaDevice::AmbaDmaDevice(const Params &p, Addr pio_size)
: DmaDevice(p), ambaId(AmbaVendor | p.amba_id),
pioAddr(p.pio_addr), pioSize(pio_size),
pioDelay(p.pio_latency), interrupt(p.interrupt->get())
{
}

6
src/dev/arm/amba_device.hh
View File

@@ -80,7 +80,7 @@ class AmbaPioDevice : public BasicPioDevice, public AmbaDevice
public:
typedef AmbaPioDeviceParams Params;
AmbaPioDevice(const Params *p, Addr pio_size);
AmbaPioDevice(const Params &p, Addr pio_size);
};
class AmbaIntDevice : public AmbaPioDevice
@@ -91,7 +91,7 @@ class AmbaIntDevice : public AmbaPioDevice
public:
typedef AmbaIntDeviceParams Params;
AmbaIntDevice(const Params *p, Addr pio_size);
AmbaIntDevice(const Params &p, Addr pio_size);
};
class AmbaDmaDevice : public DmaDevice, public AmbaDevice
@@ -105,7 +105,7 @@ class AmbaDmaDevice : public DmaDevice, public AmbaDevice
public:
typedef AmbaDmaDeviceParams Params;
AmbaDmaDevice(const Params *p, Addr pio_size = 0);
AmbaDmaDevice(const Params &p, Addr pio_size = 0);
};

10
src/dev/arm/amba_fake.cc
View File

@@ -45,7 +45,7 @@
#include "mem/packet.hh"
#include "mem/packet_access.hh"
AmbaFake::AmbaFake(const Params *p)
AmbaFake::AmbaFake(const Params &p)
: AmbaPioDevice(p, 0x1000)
{
}
@@ -60,7 +60,7 @@ AmbaFake::read(PacketPtr pkt)
DPRINTF(AMBA, " read register %#x\n", daddr);
pkt->setLE<uint32_t>(0);
if (!readId(pkt, ambaId, pioAddr) && !params()->ignore_access)
if (!readId(pkt, ambaId, pioAddr) && !params().ignore_access)
panic("Tried to read AmbaFake %s at offset %#x that doesn't exist\n",
name(), daddr);
@@ -74,7 +74,7 @@ AmbaFake::write(PacketPtr pkt)
Addr daddr = pkt->getAddr() - pioAddr;
if (!params()->ignore_access)
if (!params().ignore_access)
panic("Tried to write AmbaFake %s at offset %#x that doesn't exist\n",
name(), daddr);
@@ -84,7 +84,7 @@ AmbaFake::write(PacketPtr pkt)
AmbaFake *
AmbaFakeParams::create()
AmbaFakeParams::create() const
{
return new AmbaFake(this);
return new AmbaFake(*this);
}

8
src/dev/arm/amba_fake.hh
View File

@@ -55,13 +55,13 @@
class AmbaFake : public AmbaPioDevice
{
public:
typedef AmbaFakeParams Params;
const Params *
typedef AmbaFakeParams Params;
const Params &
params() const
{
return dynamic_cast<const Params *>(_params);
return dynamic_cast<const Params &>(_params);
}
AmbaFake(const Params *p);
AmbaFake(const Params &p);
virtual Tick read(PacketPtr pkt);
virtual Tick write(PacketPtr pkt);

30
src/dev/arm/base_gic.cc
View File

@@ -44,11 +44,11 @@
#include "params/ArmSPI.hh"
#include "params/BaseGic.hh"
BaseGic::BaseGic(const Params *p)
BaseGic::BaseGic(const Params &p)
: PioDevice(p),
platform(p->platform)
platform(p.platform)
{
RealView *const rv(dynamic_cast<RealView*>(p->platform));
RealView *const rv = dynamic_cast<RealView*>(p.platform);
// The platform keeps track of the GIC that is hooked up to the
// system. Due to quirks in gem5's configuration system, the
// platform can't take a GIC as parameter. Instead, we need to
@@ -69,19 +69,19 @@ BaseGic::init()
getSystem()->setGIC(this);
}
const BaseGic::Params *
const BaseGic::Params &
BaseGic::params() const
{
return dynamic_cast<const Params *>(_params);
return dynamic_cast<const Params &>(_params);
}
ArmInterruptPinGen::ArmInterruptPinGen(const ArmInterruptPinParams *p)
ArmInterruptPinGen::ArmInterruptPinGen(const ArmInterruptPinParams &p)
: SimObject(p)
{
}
ArmSPIGen::ArmSPIGen(const ArmSPIParams *p)
: ArmInterruptPinGen(p), pin(new ArmSPI(p->platform, p->num))
ArmSPIGen::ArmSPIGen(const ArmSPIParams &p)
: ArmInterruptPinGen(p), pin(new ArmSPI(p.platform, p.num))
{
}
@@ -91,7 +91,7 @@ ArmSPIGen::get(ThreadContext* tc)
return pin;
}
ArmPPIGen::ArmPPIGen(const ArmPPIParams *p)
ArmPPIGen::ArmPPIGen(const ArmPPIParams &p)
: ArmInterruptPinGen(p)
{
}
@@ -109,8 +109,8 @@ ArmPPIGen::get(ThreadContext* tc)
return pin_it->second;
} else {
// Generate PPI Pin
auto p = static_cast<const ArmPPIParams *>(_params);
ArmPPI *pin = new ArmPPI(p->platform, tc, p->num);
auto &p = static_cast<const ArmPPIParams &>(_params);
ArmPPI *pin = new ArmPPI(p.platform, tc, p.num);
pins.insert({cid, pin});
@@ -196,13 +196,13 @@ ArmPPI::clear()
}
ArmSPIGen *
ArmSPIParams::create()
ArmSPIParams::create() const
{
return new ArmSPIGen(this);
return new ArmSPIGen(*this);
}
ArmPPIGen *
ArmPPIParams::create()
ArmPPIParams::create() const
{
return new ArmPPIGen(this);
return new ArmPPIGen(*this);
}

10
src/dev/arm/base_gic.hh
View File

@@ -65,11 +65,11 @@ class BaseGic : public PioDevice
typedef BaseGicParams Params;
enum class GicVersion { GIC_V2, GIC_V3, GIC_V4 };
BaseGic(const Params *p);
BaseGic(const Params &p);
virtual ~BaseGic();
void init() override;
const Params * params() const;
const Params &params() const;
/**
* Post an interrupt from a device that is connected to the GIC.
@@ -135,7 +135,7 @@ class BaseGicRegisters
class ArmInterruptPinGen : public SimObject
{
public:
ArmInterruptPinGen(const ArmInterruptPinParams *p);
ArmInterruptPinGen(const ArmInterruptPinParams &p);
virtual ArmInterruptPin* get(ThreadContext *tc = nullptr) = 0;
};
@@ -148,7 +148,7 @@ class ArmInterruptPinGen : public SimObject
class ArmSPIGen : public ArmInterruptPinGen
{
public:
ArmSPIGen(const ArmSPIParams *p);
ArmSPIGen(const ArmSPIParams &p);
ArmInterruptPin* get(ThreadContext *tc = nullptr) override;
protected:
@@ -163,7 +163,7 @@ class ArmSPIGen : public ArmInterruptPinGen
class ArmPPIGen : public ArmInterruptPinGen
{
public:
ArmPPIGen(const ArmPPIParams *p);
ArmPPIGen(const ArmPPIParams &p);
ArmInterruptPin* get(ThreadContext* tc = nullptr) override;
protected:

6
src/dev/arm/display.cc
View File

@@ -39,12 +39,12 @@
#include "params/Display.hh"
Display::Display(const DisplayParams *p)
Display::Display(const DisplayParams &p)
: SimObject(p)
{}
Display *
DisplayParams::create()
DisplayParams::create() const
{
return new Display(this);
return new Display(*this);
}

2
src/dev/arm/display.hh
View File

@@ -45,7 +45,7 @@ class DisplayParams;
class Display : public SimObject
{
public:
Display(const DisplayParams *p);
Display(const DisplayParams &p);
};
#endif // __DEV_ARM_DISPLAY_H__

11
src/dev/arm/energy_ctrl.cc
View File

@@ -44,16 +44,16 @@
#include "params/EnergyCtrl.hh"
#include "sim/dvfs_handler.hh"
EnergyCtrl::EnergyCtrl(const Params *p)
EnergyCtrl::EnergyCtrl(const Params &p)
: BasicPioDevice(p, PIO_NUM_FIELDS * 4), // each field is 32 bit
dvfsHandler(p->dvfs_handler),
dvfsHandler(p.dvfs_handler),
domainID(0),
domainIDIndexToRead(0),
perfLevelAck(0),
perfLevelToRead(0),
updateAckEvent([this]{ updatePLAck(); }, name())
{
fatal_if(!p->dvfs_handler, "EnergyCtrl: Needs a DVFSHandler for a "
fatal_if(!p.dvfs_handler, "EnergyCtrl: Needs a DVFSHandler for a "
"functioning system.\n");
}
@@ -241,9 +241,10 @@ EnergyCtrl::unserialize(CheckpointIn &cp)
}
}
EnergyCtrl * EnergyCtrlParams::create()
EnergyCtrl *
EnergyCtrlParams::create() const
{
return new EnergyCtrl(this);
return new EnergyCtrl(*this);
}
void

2
src/dev/arm/energy_ctrl.hh
View File

@@ -113,7 +113,7 @@ class EnergyCtrl : public BasicPioDevice
};
typedef EnergyCtrlParams Params;
EnergyCtrl(const Params *p);
EnergyCtrl(const Params &p);
/**
* Read command sent to the device

22
src/dev/arm/flash_device.cc
View File

@@ -60,9 +60,9 @@
*/
FlashDevice*
FlashDeviceParams::create()
FlashDeviceParams::create() const
{
return new FlashDevice(this);
return new FlashDevice(*this);
}
@@ -70,17 +70,17 @@ FlashDeviceParams::create()
* Flash Device constructor and destructor
*/
FlashDevice::FlashDevice(const FlashDeviceParams* p):
FlashDevice::FlashDevice(const FlashDeviceParams &p):
AbstractNVM(p),
diskSize(0),
blockSize(p->blk_size),
pageSize(p->page_size),
GCActivePercentage(p->GC_active),
readLatency(p->read_lat),
writeLatency(p->write_lat),
eraseLatency(p->erase_lat),
dataDistribution(p->data_distribution),
numPlanes(p->num_planes),
blockSize(p.blk_size),
pageSize(p.page_size),
GCActivePercentage(p.GC_active),
readLatency(p.read_lat),
writeLatency(p.write_lat),
eraseLatency(p.erase_lat),
dataDistribution(p.data_distribution),
numPlanes(p.num_planes),
pagesPerBlock(0),
pagesPerDisk(0),
blocksPerDisk(0),

2
src/dev/arm/flash_device.hh
View File

@@ -56,7 +56,7 @@ class FlashDevice : public AbstractNVM
public:
/** Initialize functions*/
FlashDevice(const FlashDeviceParams*);
FlashDevice(const FlashDeviceParams &);
~FlashDevice();
/** Checkpoint functions*/

6
src/dev/arm/fvp_base_pwr_ctrl.cc
View File

@@ -47,7 +47,7 @@
#include "params/FVPBasePwrCtrl.hh"
#include "sim/system.hh"
FVPBasePwrCtrl::FVPBasePwrCtrl(FVPBasePwrCtrlParams *const params)
FVPBasePwrCtrl::FVPBasePwrCtrl(const FVPBasePwrCtrlParams &params)
: BasicPioDevice(params, 0x1000),
regs(),
system(*static_cast<ArmSystem *>(sys))
@@ -312,7 +312,7 @@ FVPBasePwrCtrl::startCoreUp(ThreadContext *const tc)
}
FVPBasePwrCtrl *
FVPBasePwrCtrlParams::create()
FVPBasePwrCtrlParams::create() const
{
return new FVPBasePwrCtrl(this);
return new FVPBasePwrCtrl(*this);
}

2
src/dev/arm/fvp_base_pwr_ctrl.hh
View File

@@ -55,7 +55,7 @@ class ThreadContext;
class FVPBasePwrCtrl : public BasicPioDevice
{
public:
FVPBasePwrCtrl(FVPBasePwrCtrlParams *const params);
FVPBasePwrCtrl(const FVPBasePwrCtrlParams &params);
/**
* Triggered by the ISA when a WFI instruction is executed and (1) there

76
src/dev/arm/generic_timer.cc
View File

@@ -52,12 +52,12 @@
using namespace ArmISA;
SystemCounter::SystemCounter(SystemCounterParams *const p)
SystemCounter::SystemCounter(const SystemCounterParams &p)
: SimObject(p),
_enabled(true),
_value(0),
_increment(1),
_freqTable(p->freqs),
_freqTable(p.freqs),
_activeFreqEntry(0),
_updateTick(0),
_freqUpdateEvent([this]{ freqUpdateCallback(); }, name()),
@@ -395,21 +395,21 @@ ArchTimer::drainResume()
updateCounter();
}
GenericTimer::GenericTimer(GenericTimerParams *const p)
GenericTimer::GenericTimer(const GenericTimerParams &p)
: SimObject(p),
systemCounter(*p->counter),
system(*p->system)
systemCounter(*p.counter),
system(*p.system)
{
SystemCounter::validateCounterRef(p->counter);
fatal_if(!p->system, "GenericTimer::GenericTimer: No system specified, "
SystemCounter::validateCounterRef(p.counter);
fatal_if(!p.system, "GenericTimer::GenericTimer: No system specified, "
"can't instantiate architected timers\n");
system.setGenericTimer(this);
}
const GenericTimerParams *
const GenericTimerParams &
GenericTimer::params() const
{
return dynamic_cast<const GenericTimerParams *>(_params);
return dynamic_cast<const GenericTimerParams &>(_params);
}
void
@@ -467,7 +467,7 @@ void
GenericTimer::createTimers(unsigned cpus)
{
assert(timers.size() < cpus);
auto p = static_cast<const GenericTimerParams *>(_params);
auto &p = static_cast<const GenericTimerParams &>(_params);
const unsigned old_cpu_count(timers.size());
timers.resize(cpus);
@@ -477,10 +477,10 @@ GenericTimer::createTimers(unsigned cpus)
timers[i].reset(
new CoreTimers(*this, system, i,
p->int_phys_s->get(tc),
p->int_phys_ns->get(tc),
p->int_virt->get(tc),
p->int_hyp->get(tc)));
p.int_phys_s->get(tc),
p.int_phys_ns->get(tc),
p.int_virt->get(tc),
p.int_hyp->get(tc)));
}
}
@@ -727,7 +727,7 @@ GenericTimer::CoreTimers::CoreTimers(GenericTimer &_parent,
ArmInterruptPin *_irqPhysS, ArmInterruptPin *_irqPhysNS,
ArmInterruptPin *_irqVirt, ArmInterruptPin *_irqHyp)
: parent(_parent),
cntfrq(parent.params()->cntfrq),
cntfrq(parent.params().cntfrq),
threadContext(system.threads[cpu]),
irqPhysS(_irqPhysS),
irqPhysNS(_irqPhysNS),
@@ -873,23 +873,23 @@ GenericTimerISA::readMiscReg(int reg)
return value;
}
GenericTimerFrame::GenericTimerFrame(GenericTimerFrameParams *const p)
GenericTimerFrame::GenericTimerFrame(const GenericTimerFrameParams &p)
: PioDevice(p),
timerRange(RangeSize(p->cnt_base, ArmSystem::PageBytes)),
timerRange(RangeSize(p.cnt_base, ArmSystem::PageBytes)),
addrRanges({timerRange}),
systemCounter(*p->counter),
systemCounter(*p.counter),
physTimer(csprintf("%s.phys_timer", name()),
*this, systemCounter, p->int_phys->get()),
*this, systemCounter, p.int_phys->get()),
virtTimer(csprintf("%s.virt_timer", name()),
*this, systemCounter,
p->int_virt->get()),
p.int_virt->get()),
accessBits(0x3f),
system(*dynamic_cast<ArmSystem *>(sys))
{
SystemCounter::validateCounterRef(p->counter);
SystemCounter::validateCounterRef(p.counter);
// Expose optional CNTEL0Base register frame
if (p->cnt_el0_base != MaxAddr) {
timerEl0Range = RangeSize(p->cnt_el0_base, ArmSystem::PageBytes);
if (p.cnt_el0_base != MaxAddr) {
timerEl0Range = RangeSize(p.cnt_el0_base, ArmSystem::PageBytes);
accessBitsEl0 = 0x303;
addrRanges.push_back(timerEl0Range);
}
@@ -1244,18 +1244,18 @@ GenericTimerFrame::timerWrite(Addr addr, size_t size, uint64_t data,
}
}
GenericTimerMem::GenericTimerMem(GenericTimerMemParams *const p)
GenericTimerMem::GenericTimerMem(const GenericTimerMemParams &p)
: PioDevice(p),
counterCtrlRange(RangeSize(p->cnt_control_base, ArmSystem::PageBytes)),
counterStatusRange(RangeSize(p->cnt_read_base, ArmSystem::PageBytes)),
timerCtrlRange(RangeSize(p->cnt_ctl_base, ArmSystem::PageBytes)),
counterCtrlRange(RangeSize(p.cnt_control_base, ArmSystem::PageBytes)),
counterStatusRange(RangeSize(p.cnt_read_base, ArmSystem::PageBytes)),
timerCtrlRange(RangeSize(p.cnt_ctl_base, ArmSystem::PageBytes)),
cnttidr(0x0),
addrRanges{counterCtrlRange, counterStatusRange, timerCtrlRange},
systemCounter(*p->counter),
frames(p->frames),
systemCounter(*p.counter),
frames(p.frames),
system(*dynamic_cast<ArmSystem *>(sys))
{
SystemCounter::validateCounterRef(p->counter);
SystemCounter::validateCounterRef(p.counter);
for (auto &range : addrRanges)
GenericTimerMem::validateFrameRange(range);
fatal_if(frames.size() > MAX_TIMER_FRAMES,
@@ -1586,25 +1586,25 @@ GenericTimerMem::timerCtrlWrite(Addr addr, size_t size, uint64_t data,
}
SystemCounter *
SystemCounterParams::create()
SystemCounterParams::create() const
{
return new SystemCounter(this);
return new SystemCounter(*this);
}
GenericTimer *
GenericTimerParams::create()
GenericTimerParams::create() const
{
return new GenericTimer(this);
return new GenericTimer(*this);
}
GenericTimerFrame *
GenericTimerFrameParams::create()
GenericTimerFrameParams::create() const
{
return new GenericTimerFrame(this);
return new GenericTimerFrame(*this);
}
GenericTimerMem *
GenericTimerMemParams::create()
GenericTimerMemParams::create() const
{
return new GenericTimerMem(this);
return new GenericTimerMem(*this);
}

10
src/dev/arm/generic_timer.hh
View File

@@ -100,7 +100,7 @@ class SystemCounter : public SimObject
static constexpr size_t MAX_FREQ_ENTRIES = 1004;
public:
SystemCounter(SystemCounterParams *const p);
SystemCounter(const SystemCounterParams &p);
/// Validates a System Counter reference
/// @param sys_cnt System counter reference to validate
@@ -276,9 +276,9 @@ class ArchTimerKvm : public ArchTimer
class GenericTimer : public SimObject
{
public:
const GenericTimerParams * params() const;
const GenericTimerParams &params() const;
GenericTimer(GenericTimerParams *const p);
GenericTimer(const GenericTimerParams &p);
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
@@ -392,7 +392,7 @@ class GenericTimerISA : public ArmISA::BaseISADevice
class GenericTimerFrame : public PioDevice
{
public:
GenericTimerFrame(GenericTimerFrameParams *const p);
GenericTimerFrame(const GenericTimerFrameParams &p);
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
@@ -496,7 +496,7 @@ class GenericTimerFrame : public PioDevice
class GenericTimerMem : public PioDevice
{
public:
GenericTimerMem(GenericTimerMemParams *const p);
GenericTimerMem(const GenericTimerMemParams &p);
/// Validates a Generic Timer register frame address range
/// @param base_addr Range of the register frame

24
src/dev/arm/gic_v2.cc
View File

@@ -59,18 +59,18 @@ const AddrRange GicV2::GICD_IPRIORITYR(0x400, 0x800);
const AddrRange GicV2::GICD_ITARGETSR (0x800, 0xc00);
const AddrRange GicV2::GICD_ICFGR (0xc00, 0xd00);
GicV2::GicV2(const Params *p)
GicV2::GicV2(const Params &p)
: BaseGic(p),
gicdPIDR(p->gicd_pidr),
gicdIIDR(p->gicd_iidr),
giccIIDR(p->gicc_iidr),
distRange(RangeSize(p->dist_addr, DIST_SIZE)),
cpuRange(RangeSize(p->cpu_addr, p->cpu_size)),
gicdPIDR(p.gicd_pidr),
gicdIIDR(p.gicd_iidr),
giccIIDR(p.gicc_iidr),
distRange(RangeSize(p.dist_addr, DIST_SIZE)),
cpuRange(RangeSize(p.cpu_addr, p.cpu_size)),
addrRanges{distRange, cpuRange},
distPioDelay(p->dist_pio_delay),
cpuPioDelay(p->cpu_pio_delay), intLatency(p->int_latency),
enabled(false), haveGem5Extensions(p->gem5_extensions),
itLines(p->it_lines),
distPioDelay(p.dist_pio_delay),
cpuPioDelay(p.cpu_pio_delay), intLatency(p.int_latency),
enabled(false), haveGem5Extensions(p.gem5_extensions),
itLines(p.it_lines),
intEnabled {}, pendingInt {}, activeInt {},
intPriority {}, intConfig {}, cpuTarget {},
cpuSgiPending {}, cpuSgiActive {},
@@ -1092,7 +1092,7 @@ GicV2::BankedRegs::unserialize(CheckpointIn &cp)
}
GicV2 *
GicV2Params::create()
GicV2Params::create() const
{
return new GicV2(this);
return new GicV2(*this);
}

6
src/dev/arm/gic_v2.hh
View File

@@ -476,12 +476,12 @@ class GicV2 : public BaseGic, public BaseGicRegisters
public:
typedef GicV2Params Params;
const Params *
const Params &
params() const
{
return dynamic_cast<const Params *>(_params);
return dynamic_cast<const Params &>(_params);
}
GicV2(const Params *p);
GicV2(const Params &p);
~GicV2();
DrainState drain() override;

12
src/dev/arm/gic_v2m.cc
View File

@@ -65,19 +65,19 @@
#include "mem/packet_access.hh"
Gicv2m *
Gicv2mParams::create()
Gicv2mParams::create() const
{
return new Gicv2m(this);
return new Gicv2m(*this);
}
Gicv2mFrame *
Gicv2mFrameParams::create()
Gicv2mFrameParams::create() const
{
return new Gicv2mFrame(this);
return new Gicv2mFrame(*this);
}
Gicv2m::Gicv2m(const Params *p)
: PioDevice(p), pioDelay(p->pio_delay), frames(p->frames), gic(p->gic)
Gicv2m::Gicv2m(const Params &p)
: PioDevice(p), pioDelay(p.pio_delay), frames(p.frames), gic(p.gic)
{
// Assert SPI ranges start at 32
for (int i = 0; i < frames.size(); i++) {

6
src/dev/arm/gic_v2m.hh
View File

@@ -65,8 +65,8 @@ class Gicv2mFrame : public SimObject
const unsigned int spi_len;
typedef Gicv2mFrameParams Params;
Gicv2mFrame(const Params *p) :
SimObject(p), addr(p->addr), spi_base(p->spi_base), spi_len(p->spi_len)
Gicv2mFrame(const Params &p) :
SimObject(p), addr(p.addr), spi_base(p.spi_base), spi_len(p.spi_len)
{}
};
@@ -93,7 +93,7 @@ class Gicv2m : public PioDevice
public:
typedef Gicv2mParams Params;
Gicv2m(const Params *p);
Gicv2m(const Params &p);
/** @{ */
/** Return the address ranges used by the Gicv2m

28
src/dev/arm/gic_v3.cc
View File

@@ -51,7 +51,7 @@
#include "mem/packet.hh"
#include "mem/packet_access.hh"
Gicv3::Gicv3(const Params * p)
Gicv3::Gicv3(const Params &p)
: BaseGic(p)
{
}
@@ -59,25 +59,25 @@ Gicv3::Gicv3(const Params * p)
void
Gicv3::init()
{
distributor = new Gicv3Distributor(this, params()->it_lines);
distributor = new Gicv3Distributor(this, params().it_lines);
int threads = sys->threads.size();
redistributors.resize(threads, nullptr);
cpuInterfaces.resize(threads, nullptr);
panic_if(threads > params()->cpu_max,
panic_if(threads > params().cpu_max,
"Exceeding maximum number of PEs supported by GICv3: "
"using %u while maximum is %u.", threads, params()->cpu_max);
"using %u while maximum is %u.", threads, params().cpu_max);
for (int i = 0; i < threads; i++) {
redistributors[i] = new Gicv3Redistributor(this, i);
cpuInterfaces[i] = new Gicv3CPUInterface(this, i);
}
distRange = RangeSize(params()->dist_addr,
distRange = RangeSize(params().dist_addr,
Gicv3Distributor::ADDR_RANGE_SIZE - 1);
redistSize = redistributors[0]->addrRangeSize;
redistRange = RangeSize(params()->redist_addr, redistSize * threads - 1);
redistRange = RangeSize(params().redist_addr, redistSize * threads - 1);
addrRanges = {distRange, redistRange};
@@ -88,7 +88,7 @@ Gicv3::init()
cpuInterfaces[i]->init();
}
Gicv3Its *its = params()->its;
Gicv3Its *its = params().its;
if (its)
its->setGIC(this);
@@ -108,7 +108,7 @@ Gicv3::read(PacketPtr pkt)
const Addr daddr = addr - distRange.start();
panic_if(!distributor, "Distributor is null!");
resp = distributor->read(daddr, size, is_secure_access);
delay = params()->dist_pio_delay;
delay = params().dist_pio_delay;
DPRINTF(GIC, "Gicv3::read(): (distributor) context_id %d register %#x "
"size %d is_secure_access %d (value %#x)\n",
pkt->req->contextId(), daddr, size, is_secure_access, resp);
@@ -118,7 +118,7 @@ Gicv3::read(PacketPtr pkt)
Gicv3Redistributor *redist = getRedistributorByAddr(addr);
resp = redist->read(daddr, size, is_secure_access);
delay = params()->redist_pio_delay;
delay = params().redist_pio_delay;
DPRINTF(GIC, "Gicv3::read(): (redistributor %d) context_id %d "
"register %#x size %d is_secure_access %d (value %#x)\n",
redist->processorNumber(), pkt->req->contextId(), daddr, size,
@@ -148,7 +148,7 @@ Gicv3::write(PacketPtr pkt)
"register %#x size %d is_secure_access %d value %#x\n",
pkt->req->contextId(), daddr, size, is_secure_access, data);
distributor->write(daddr, data, size, is_secure_access);
delay = params()->dist_pio_delay;
delay = params().dist_pio_delay;
} else if (redistRange.contains(addr)) {
Addr daddr = (addr - redistRange.start()) % redistSize;
@@ -160,7 +160,7 @@ Gicv3::write(PacketPtr pkt)
redist->write(daddr, data, size, is_secure_access);
delay = params()->redist_pio_delay;
delay = params().redist_pio_delay;
} else {
panic("Gicv3::write(): unknown address %#x\n", addr);
}
@@ -212,7 +212,7 @@ bool
Gicv3::supportsVersion(GicVersion version)
{
return (version == GicVersion::GIC_V3) ||
(version == GicVersion::GIC_V4 && params()->gicv4);
(version == GicVersion::GIC_V4 && params().gicv4);
}
void
@@ -296,7 +296,7 @@ Gicv3::unserialize(CheckpointIn & cp)
}
Gicv3 *
Gicv3Params::create()
Gicv3Params::create() const
{
return new Gicv3(this);
return new Gicv3(*this);
}

6
src/dev/arm/gic_v3.hh
View File

@@ -111,10 +111,10 @@ class Gicv3 : public BaseGic
void init() override;
const Params *
const Params &
params() const
{
return dynamic_cast<const Params *>(_params);
return dynamic_cast<const Params &>(_params);
}
Tick read(PacketPtr pkt) override;
@@ -128,7 +128,7 @@ class Gicv3 : public BaseGic
public:
Gicv3(const Params * p);
Gicv3(const Params &p);
void deassertInt(uint32_t cpu, ArmISA::InterruptTypes int_type);
void deassertAll(uint32_t cpu);
bool haveAsserted(uint32_t cpu) const;

2
src/dev/arm/gic_v3_cpu_interface.cc
View File

@@ -80,7 +80,7 @@ Gicv3CPUInterface::resetHppi(uint32_t intid)
void
Gicv3CPUInterface::setThreadContext(ThreadContext *tc)
{
maintenanceInterrupt = gic->params()->maint_int->get(tc);
maintenanceInterrupt = gic->params().maint_int->get(tc);
fatal_if(maintenanceInterrupt->num() >= redistributor->irqPending.size(),
"Invalid maintenance interrupt number\n");
}

12
src/dev/arm/gic_v3_its.cc
View File

@@ -771,15 +771,15 @@ ItsCommand::vsync(Yield &yield, CommandEntry &command)
panic("ITS %s command unimplemented", __func__);
}
Gicv3Its::Gicv3Its(const Gicv3ItsParams *params)
: BasicPioDevice(params, params->pio_size),
Gicv3Its::Gicv3Its(const Gicv3ItsParams &params)
: BasicPioDevice(params, params.pio_size),
dmaPort(name() + ".dma", *this),
gitsControl(CTLR_QUIESCENT),
gitsTyper(params->gits_typer),
gitsTyper(params.gits_typer),
gitsCbaser(0), gitsCreadr(0),
gitsCwriter(0), gitsIidr(0),
tableBases(NUM_BASER_REGS, 0),
requestorId(params->system->getRequestorId(this)),
requestorId(params.system->getRequestorId(this)),
gic(nullptr),
commandEvent([this] { checkCommandQueue(); }, name()),
pendingCommands(false),
@@ -1288,7 +1288,7 @@ Gicv3Its::moveAllPendingState(
}
Gicv3Its *
Gicv3ItsParams::create()
Gicv3ItsParams::create() const
{
return new Gicv3Its(this);
return new Gicv3Its(*this);
}

2
src/dev/arm/gic_v3_its.hh
View File

@@ -100,7 +100,7 @@ class Gicv3Its : public BasicPioDevice
bool recvTimingResp(PacketPtr pkt);
void recvReqRetry();
Gicv3Its(const Gicv3ItsParams *params);
Gicv3Its(const Gicv3ItsParams &params);
void setGIC(Gicv3 *_gic);

2
src/dev/arm/gic_v3_redistributor.cc
View File

@@ -73,7 +73,7 @@ Gicv3Redistributor::Gicv3Redistributor(Gicv3 * gic, uint32_t cpu_id)
lpiConfigurationTablePtr(0),
lpiIDBits(0),
lpiPendingTablePtr(0),
addrRangeSize(gic->params()->gicv4 ? 0x40000 : 0x20000)
addrRangeSize(gic->params().gicv4 ? 0x40000 : 0x20000)
{
}

82
src/dev/arm/gpu_nomali.cc
View File

@@ -52,14 +52,14 @@ static const std::map<Enums::NoMaliGpuType, nomali_gpu_type_t> gpuTypeMap{
{ Enums::T760, NOMALI_GPU_T760 },
};
NoMaliGpu::NoMaliGpu(const NoMaliGpuParams *p)
NoMaliGpu::NoMaliGpu(const NoMaliGpuParams &p)
: PioDevice(p),
pioAddr(p->pio_addr),
platform(p->platform),
pioAddr(p.pio_addr),
platform(p.platform),
interruptMap{
{ NOMALI_INT_GPU, p->int_gpu },
{ NOMALI_INT_JOB, p->int_job },
{ NOMALI_INT_MMU, p->int_mmu },
{ NOMALI_INT_GPU, p.int_gpu },
{ NOMALI_INT_JOB, p.int_job },
{ NOMALI_INT_MMU, p.int_mmu },
}
{
if (nomali_api_version() != NOMALI_API_VERSION)
@@ -69,16 +69,16 @@ NoMaliGpu::NoMaliGpu(const NoMaliGpuParams *p)
nomali_config_t cfg;
memset(&cfg, 0, sizeof(cfg));
const auto it_gpu(gpuTypeMap.find(p->gpu_type));
const auto it_gpu(gpuTypeMap.find(p.gpu_type));
if (it_gpu == gpuTypeMap.end()) {
fatal("Unrecognized GPU type: %s (%i)\n",
Enums::NoMaliGpuTypeStrings[p->gpu_type], p->gpu_type);
Enums::NoMaliGpuTypeStrings[p.gpu_type], p.gpu_type);
}
cfg.type = it_gpu->second;
cfg.ver_maj = p->ver_maj;
cfg.ver_min = p->ver_min;
cfg.ver_status = p->ver_status;
cfg.ver_maj = p.ver_maj;
cfg.ver_min = p.ver_min;
cfg.ver_status = p.ver_status;
panicOnErr(
nomali_create(&nomali, &cfg),
@@ -321,45 +321,45 @@ NoMaliGpu::_reset(nomali_handle_t h, void *usr)
}
CustomNoMaliGpu::CustomNoMaliGpu(const CustomNoMaliGpuParams *p)
CustomNoMaliGpu::CustomNoMaliGpu(const CustomNoMaliGpuParams &p)
: NoMaliGpu(p),
idRegs{
{ GPU_CONTROL_REG(GPU_ID), p->gpu_id },
{ GPU_CONTROL_REG(L2_FEATURES), p->l2_features },
{ GPU_CONTROL_REG(TILER_FEATURES), p->tiler_features },
{ GPU_CONTROL_REG(MEM_FEATURES), p->mem_features },
{ GPU_CONTROL_REG(MMU_FEATURES), p->mmu_features },
{ GPU_CONTROL_REG(AS_PRESENT), p->as_present },
{ GPU_CONTROL_REG(JS_PRESENT), p->js_present },
{ GPU_CONTROL_REG(GPU_ID), p.gpu_id },
{ GPU_CONTROL_REG(L2_FEATURES), p.l2_features },
{ GPU_CONTROL_REG(TILER_FEATURES), p.tiler_features },
{ GPU_CONTROL_REG(MEM_FEATURES), p.mem_features },
{ GPU_CONTROL_REG(MMU_FEATURES), p.mmu_features },
{ GPU_CONTROL_REG(AS_PRESENT), p.as_present },
{ GPU_CONTROL_REG(JS_PRESENT), p.js_present },
{ GPU_CONTROL_REG(THREAD_MAX_THREADS), p->thread_max_threads },
{ GPU_CONTROL_REG(THREAD_MAX_THREADS), p.thread_max_threads },
{ GPU_CONTROL_REG(THREAD_MAX_WORKGROUP_SIZE),
p->thread_max_workgroup_size },
p.thread_max_workgroup_size },
{ GPU_CONTROL_REG(THREAD_MAX_BARRIER_SIZE),
p->thread_max_barrier_size },
{ GPU_CONTROL_REG(THREAD_FEATURES), p->thread_features },
p.thread_max_barrier_size },
{ GPU_CONTROL_REG(THREAD_FEATURES), p.thread_features },
{ GPU_CONTROL_REG(SHADER_PRESENT_LO), bits(p->shader_present, 31, 0) },
{ GPU_CONTROL_REG(SHADER_PRESENT_HI), bits(p->shader_present, 63, 32) },
{ GPU_CONTROL_REG(TILER_PRESENT_LO), bits(p->tiler_present, 31, 0) },
{ GPU_CONTROL_REG(TILER_PRESENT_HI), bits(p->tiler_present, 63, 32) },
{ GPU_CONTROL_REG(L2_PRESENT_LO), bits(p->l2_present, 31, 0) },
{ GPU_CONTROL_REG(L2_PRESENT_HI), bits(p->l2_present, 63, 32) },
{ GPU_CONTROL_REG(SHADER_PRESENT_LO), bits(p.shader_present, 31, 0) },
{ GPU_CONTROL_REG(SHADER_PRESENT_HI), bits(p.shader_present, 63, 32) },
{ GPU_CONTROL_REG(TILER_PRESENT_LO), bits(p.tiler_present, 31, 0) },
{ GPU_CONTROL_REG(TILER_PRESENT_HI), bits(p.tiler_present, 63, 32) },
{ GPU_CONTROL_REG(L2_PRESENT_LO), bits(p.l2_present, 31, 0) },
{ GPU_CONTROL_REG(L2_PRESENT_HI), bits(p.l2_present, 63, 32) },
}
{
fatal_if(p->texture_features.size() > 3,
fatal_if(p.texture_features.size() > 3,
"Too many texture feature registers specified (%i)\n",
p->texture_features.size());
p.texture_features.size());
fatal_if(p->js_features.size() > 16,
fatal_if(p.js_features.size() > 16,
"Too many job slot feature registers specified (%i)\n",
p->js_features.size());
p.js_features.size());
for (int i = 0; i < p->texture_features.size(); i++)
idRegs[TEXTURE_FEATURES_REG(i)] = p->texture_features[i];
for (int i = 0; i < p.texture_features.size(); i++)
idRegs[TEXTURE_FEATURES_REG(i)] = p.texture_features[i];
for (int i = 0; i < p->js_features.size(); i++)
idRegs[JS_FEATURES_REG(i)] = p->js_features[i];
for (int i = 0; i < p.js_features.size(); i++)
idRegs[JS_FEATURES_REG(i)] = p.js_features[i];
}
CustomNoMaliGpu::~CustomNoMaliGpu()
@@ -378,13 +378,13 @@ CustomNoMaliGpu::onReset()
NoMaliGpu *
NoMaliGpuParams::create()
NoMaliGpuParams::create() const
{
return new NoMaliGpu(this);
return new NoMaliGpu(*this);
}
CustomNoMaliGpu *
CustomNoMaliGpuParams::create()
CustomNoMaliGpuParams::create() const
{
return new CustomNoMaliGpu(this);
return new CustomNoMaliGpu(*this);
}

4
src/dev/arm/gpu_nomali.hh
View File

@@ -50,7 +50,7 @@ class RealView;
class NoMaliGpu : public PioDevice
{
public:
NoMaliGpu(const NoMaliGpuParams *p);
NoMaliGpu(const NoMaliGpuParams &p);
virtual ~NoMaliGpu();
void init() override;
@@ -188,7 +188,7 @@ class NoMaliGpu : public PioDevice
class CustomNoMaliGpu : public NoMaliGpu
{
public:
CustomNoMaliGpu(const CustomNoMaliGpuParams *p);
CustomNoMaliGpu(const CustomNoMaliGpuParams &p);
virtual ~CustomNoMaliGpu();
protected:

22
src/dev/arm/hdlcd.cc
View File

@@ -54,16 +54,16 @@ using std::vector;
// initialize hdlcd registers
HDLcd::HDLcd(const HDLcdParams *p)
HDLcd::HDLcd(const HDLcdParams &p)
: AmbaDmaDevice(p, 0xFFFF),
// Parameters
vnc(p->vnc),
workaroundSwapRB(p->workaround_swap_rb),
workaroundDmaLineCount(p->workaround_dma_line_count),
vnc(p.vnc),
workaroundSwapRB(p.workaround_swap_rb),
workaroundDmaLineCount(p.workaround_dma_line_count),
addrRanges{RangeSize(pioAddr, pioSize)},
enableCapture(p->enable_capture),
pixelBufferSize(p->pixel_buffer_size),
virtRefreshRate(p->virt_refresh_rate),
enableCapture(p.enable_capture),
pixelBufferSize(p.pixel_buffer_size),
virtRefreshRate(p.virt_refresh_rate),
// Registers
version(VERSION_RESETV),
@@ -83,8 +83,8 @@ HDLcd::HDLcd(const HDLcdParams *p)
virtRefreshEvent([this]{ virtRefresh(); }, name()),
// Other
imgFormat(p->frame_format), pic(NULL), conv(PixelConverter::rgba8888_le),
pixelPump(*this, *p->pxl_clk, p->pixel_chunk)
imgFormat(p.frame_format), pic(NULL), conv(PixelConverter::rgba8888_le),
pixelPump(*this, *p.pxl_clk, p.pixel_chunk)
{
if (vnc)
vnc->setFrameBuffer(&pixelPump.fb);
@@ -692,7 +692,7 @@ HDLcd::PixelPump::dumpSettings()
HDLcd *
HDLcdParams::create()
HDLcdParams::create() const
{
return new HDLcd(this);
return new HDLcd(*this);
}

2
src/dev/arm/hdlcd.hh
View File

@@ -90,7 +90,7 @@ class HDLcdPixelPump;
class HDLcd: public AmbaDmaDevice
{
public:
HDLcd(const HDLcdParams *p);
HDLcd(const HDLcdParams &p);
~HDLcd();
void regStats() override;

8
src/dev/arm/kmi.cc
View File

@@ -48,10 +48,10 @@
#include "mem/packet.hh"
#include "mem/packet_access.hh"
Pl050::Pl050(const Pl050Params *p)
Pl050::Pl050(const Pl050Params &p)
: AmbaIntDevice(p, 0x1000), control(0), status(0x43), clkdiv(0),
rawInterrupts(0),
ps2(p->ps2)
ps2(p.ps2)
{
ps2->hostRegDataAvailable([this]() { this->updateRxInt(); });
}
@@ -221,7 +221,7 @@ Pl050::unserialize(CheckpointIn &cp)
}
Pl050 *
Pl050Params::create()
Pl050Params::create() const
{
return new Pl050(this);
return new Pl050(*this);
}

2
src/dev/arm/kmi.hh
View File

@@ -126,7 +126,7 @@ class Pl050 : public AmbaIntDevice
PS2Device *ps2;
public:
Pl050(const Pl050Params *p);
Pl050(const Pl050Params &p);
Tick read(PacketPtr pkt) override;
Tick write(PacketPtr pkt) override;

10
src/dev/arm/pci_host.cc
View File

@@ -39,10 +39,10 @@
#include "params/GenericArmPciHost.hh"
GenericArmPciHost::GenericArmPciHost(const GenericArmPciHostParams *p)
GenericArmPciHost::GenericArmPciHost(const GenericArmPciHostParams &p)
: GenericPciHost(p),
intPolicy(p->int_policy), intBase(p->int_base),
intCount(p->int_count)
intPolicy(p.int_policy), intBase(p.int_base),
intCount(p.int_count)
{
}
@@ -71,7 +71,7 @@ GenericArmPciHost::mapPciInterrupt(const PciBusAddr &addr, PciIntPin pin) const
GenericArmPciHost *
GenericArmPciHostParams::create()
GenericArmPciHostParams::create() const
{
return new GenericArmPciHost(this);
return new GenericArmPciHost(*this);
}

2
src/dev/arm/pci_host.hh
View File

@@ -48,7 +48,7 @@ class GenericArmPciHost
: public GenericPciHost
{
public:
GenericArmPciHost(const GenericArmPciHostParams *p);
GenericArmPciHost(const GenericArmPciHostParams &p);
virtual ~GenericArmPciHost() {}
protected:

10
src/dev/arm/pl011.cc
View File

@@ -50,13 +50,13 @@
#include "params/Pl011.hh"
#include "sim/sim_exit.hh"
Pl011::Pl011(const Pl011Params *p)
Pl011::Pl011(const Pl011Params &p)
: Uart(p, 0x1000),
intEvent([this]{ generateInterrupt(); }, name()),
control(0x300), fbrd(0), ibrd(0), lcrh(0), ifls(0x12),
imsc(0), rawInt(0),
endOnEOT(p->end_on_eot), interrupt(p->interrupt->get()),
intDelay(p->int_delay)
endOnEOT(p.end_on_eot), interrupt(p.interrupt->get()),
intDelay(p.int_delay)
{
}
@@ -327,7 +327,7 @@ Pl011::unserialize(CheckpointIn &cp)
}
Pl011 *
Pl011Params::create()
Pl011Params::create() const
{
return new Pl011(this);
return new Pl011(*this);
}

2
src/dev/arm/pl011.hh
View File

@@ -55,7 +55,7 @@ struct Pl011Params;
class Pl011 : public Uart, public AmbaDevice
{
public:
Pl011(const Pl011Params *p);
Pl011(const Pl011Params &p);
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;

12
src/dev/arm/pl111.cc
View File

@@ -53,16 +53,16 @@
using std::vector;
// initialize clcd registers
Pl111::Pl111(const Params *p)
Pl111::Pl111(const Params &p)
: AmbaDmaDevice(p), lcdTiming0(0), lcdTiming1(0), lcdTiming2(0),
lcdTiming3(0), lcdUpbase(0), lcdLpbase(0), lcdControl(0), lcdImsc(0),
lcdRis(0), lcdMis(0),
clcdCrsrCtrl(0), clcdCrsrConfig(0), clcdCrsrPalette0(0),
clcdCrsrPalette1(0), clcdCrsrXY(0), clcdCrsrClip(0), clcdCrsrImsc(0),
clcdCrsrIcr(0), clcdCrsrRis(0), clcdCrsrMis(0),
pixelClock(p->pixel_clock),
pixelClock(p.pixel_clock),
converter(PixelConverter::rgba8888_le), fb(LcdMaxWidth, LcdMaxHeight),
vnc(p->vnc), bmp(&fb), pic(NULL),
vnc(p.vnc), bmp(&fb), pic(NULL),
width(LcdMaxWidth), height(LcdMaxHeight),
bytesPerPixel(4), startTime(0), startAddr(0), maxAddr(0), curAddr(0),
waterMark(0), dmaPendingNum(0),
@@ -71,7 +71,7 @@ Pl111::Pl111(const Params *p)
dmaDoneEventAll(maxOutstandingDma, this),
dmaDoneEventFree(maxOutstandingDma),
intEvent([this]{ generateInterrupt(); }, name()),
enableCapture(p->enable_capture)
enableCapture(p.enable_capture)
{
pioSize = 0xFFFF;
@@ -744,9 +744,9 @@ Pl111::getAddrRanges() const
}
Pl111 *
Pl111Params::create()
Pl111Params::create() const
{
return new Pl111(this);
return new Pl111(*this);
}

6
src/dev/arm/pl111.hh
View File

@@ -358,12 +358,12 @@ class Pl111: public AmbaDmaDevice
public:
typedef Pl111Params Params;
const Params *
const Params &
params() const
{
return dynamic_cast<const Params *>(_params);
return dynamic_cast<const Params &>(_params);
}
Pl111(const Params *p);
Pl111(const Params &p);
~Pl111();
Tick read(PacketPtr pkt) override;

8
src/dev/arm/realview.cc
View File

@@ -53,8 +53,8 @@
#include "sim/system.hh"
RealView::RealView(const Params *p)
: Platform(p), system(p->system), gic(nullptr)
RealView::RealView(const Params &p)
: Platform(p), system(p.system), gic(nullptr)
{}
void
@@ -84,7 +84,7 @@ RealView::clearPciInt(int line)
}
RealView *
RealViewParams::create()
RealViewParams::create() const
{
return new RealView(this);
return new RealView(*this);
}

6
src/dev/arm/realview.hh
View File

@@ -64,9 +64,9 @@ class RealView : public Platform
public:
typedef RealViewParams Params;
const Params *
const Params &
params() const {
return dynamic_cast<const Params *>(_params);
return dynamic_cast<const Params &>(_params);
}
/**
@@ -75,7 +75,7 @@ class RealView : public Platform
* @param s system the object belongs to
* @param intctrl pointer to the interrupt controller
*/
RealView(const Params *p);
RealView(const Params &p);
/** Give platform a pointer to interrupt controller */
void setGic(BaseGic *_gic) { gic = _gic; }

12
src/dev/arm/rtc_pl031.cc
View File

@@ -46,12 +46,14 @@
#include "mem/packet.hh"
#include "mem/packet_access.hh"
PL031::PL031(Params *p)
: AmbaIntDevice(p, 0x1000), timeVal(mkutctime(&p->time)),
lastWrittenTick(0), loadVal(0), matchVal(0),
PL031::PL031(const Params &p)
: AmbaIntDevice(p, 0x1000), lastWrittenTick(0), loadVal(0), matchVal(0),
rawInt(false), maskInt(false), pendingInt(false),
matchEvent([this]{ counterMatch(); }, name())
{
// Make a temporary copy so mkutctime can modify it.
struct tm local_time = p.time;
timeVal = mkutctime(&local_time);
}
@@ -239,7 +241,7 @@ PL031::unserialize(CheckpointIn &cp)
PL031 *
PL031Params::create()
PL031Params::create() const
{
return new PL031(this);
return new PL031(*this);
}

6
src/dev/arm/rtc_pl031.hh
View File

@@ -98,16 +98,16 @@ class PL031 : public AmbaIntDevice
public:
typedef PL031Params Params;
const Params *
const Params &
params() const
{
return dynamic_cast<const Params *>(_params);
return dynamic_cast<const Params &>(_params);
}
/**
* The constructor for RealView just registers itself with the MMU.
* @param p params structure
*/
PL031(Params *p);
PL031(const Params &p);
/**
* Handle a read to the device

34
src/dev/arm/rv_ctrl.cc
View File

@@ -45,7 +45,7 @@
#include "sim/system.hh"
#include "sim/voltage_domain.hh"
RealViewCtrl::RealViewCtrl(Params *p)
RealViewCtrl::RealViewCtrl(const Params &p)
: BasicPioDevice(p, 0xD4), flags(0), scData(0)
{
}
@@ -59,10 +59,10 @@ RealViewCtrl::read(PacketPtr pkt)
switch(daddr) {
case ProcId0:
pkt->setLE(params()->proc_id0);
pkt->setLE(params().proc_id0);
break;
case ProcId1:
pkt->setLE(params()->proc_id1);
pkt->setLE(params().proc_id1);
break;
case Clock24:
Tick clk;
@@ -102,7 +102,7 @@ RealViewCtrl::read(PacketPtr pkt)
pkt->setLE<uint32_t>(flags);
break;
case IdReg:
pkt->setLE<uint32_t>(params()->idreg);
pkt->setLE<uint32_t>(params().idreg);
break;
case CfgStat:
pkt->setLE<uint32_t>(1);
@@ -234,17 +234,17 @@ RealViewCtrl::registerDevice(DeviceFunc func, uint8_t site, uint8_t pos,
}
RealViewOsc::RealViewOsc(RealViewOscParams *p)
: ClockDomain(p, p->voltage_domain),
RealViewCtrl::Device(*p->parent, RealViewCtrl::FUNC_OSC,
p->site, p->position, p->dcc, p->device)
RealViewOsc::RealViewOsc(const RealViewOscParams &p)
: ClockDomain(p, p.voltage_domain),
RealViewCtrl::Device(*p.parent, RealViewCtrl::FUNC_OSC,
p.site, p.position, p.dcc, p.device)
{
if (SimClock::Float::s / p->freq > UINT32_MAX) {
if (SimClock::Float::s / p.freq > UINT32_MAX) {
fatal("Oscillator frequency out of range: %f\n",
SimClock::Float::s / p->freq / 1E6);
SimClock::Float::s / p.freq / 1E6);
}
_clockPeriod = p->freq;
_clockPeriod = p.freq;
}
void
@@ -315,19 +315,19 @@ RealViewTemperatureSensor::read() const
}
RealViewCtrl *
RealViewCtrlParams::create()
RealViewCtrlParams::create() const
{
return new RealViewCtrl(this);
return new RealViewCtrl(*this);
}
RealViewOsc *
RealViewOscParams::create()
RealViewOscParams::create() const
{
return new RealViewOsc(this);
return new RealViewOsc(*this);
}
RealViewTemperatureSensor *
RealViewTemperatureSensorParams::create()
RealViewTemperatureSensorParams::create() const
{
return new RealViewTemperatureSensor(this);
return new RealViewTemperatureSensor(*this);
}

16
src/dev/arm/rv_ctrl.hh
View File

@@ -154,16 +154,16 @@ class RealViewCtrl : public BasicPioDevice
public:
typedef RealViewCtrlParams Params;
const Params *
const Params &
params() const
{
return dynamic_cast<const Params *>(_params);
return dynamic_cast<const Params &>(_params);
}
/**
* The constructor for RealView just registers itself with the MMU.
* @param p params structure
*/
RealViewCtrl(Params *p);
RealViewCtrl(const Params &p);
/**
* Handle a read to the device
@@ -202,7 +202,7 @@ class RealViewOsc
: public ClockDomain, RealViewCtrl::Device
{
public:
RealViewOsc(RealViewOscParams *p);
RealViewOsc(const RealViewOscParams &p);
virtual ~RealViewOsc() {};
void startup() override;
@@ -228,11 +228,11 @@ class RealViewTemperatureSensor
: public SimObject, RealViewCtrl::Device
{
public:
RealViewTemperatureSensor(RealViewTemperatureSensorParams *p)
RealViewTemperatureSensor(const RealViewTemperatureSensorParams &p)
: SimObject(p),
RealViewCtrl::Device(*p->parent, RealViewCtrl::FUNC_TEMP,
p->site, p->position, p->dcc, p->device),
system(p->system)
RealViewCtrl::Device(*p.parent, RealViewCtrl::FUNC_TEMP,
p.site, p.position, p.dcc, p.device),
system(p.system)
{}
virtual ~RealViewTemperatureSensor() {};

88
src/dev/arm/smmu_v3.cc
View File

@@ -51,49 +51,49 @@
#include "mem/packet_access.hh"
#include "sim/system.hh"
SMMUv3::SMMUv3(SMMUv3Params *params) :
SMMUv3::SMMUv3(const SMMUv3Params &params) :
ClockedObject(params),
system(*params->system),
requestorId(params->system->getRequestorId(this)),
system(*params.system),
requestorId(params.system->getRequestorId(this)),
requestPort(name() + ".request", *this),
tableWalkPort(name() + ".walker", *this),
controlPort(name() + ".control", *this, params->reg_map),
tlb(params->tlb_entries, params->tlb_assoc, params->tlb_policy),
configCache(params->cfg_entries, params->cfg_assoc, params->cfg_policy),
ipaCache(params->ipa_entries, params->ipa_assoc, params->ipa_policy),
walkCache({ { params->walk_S1L0, params->walk_S1L1,
params->walk_S1L2, params->walk_S1L3,
params->walk_S2L0, params->walk_S2L1,
params->walk_S2L2, params->walk_S2L3 } },
params->walk_assoc, params->walk_policy),
tlbEnable(params->tlb_enable),
configCacheEnable(params->cfg_enable),
ipaCacheEnable(params->ipa_enable),
walkCacheEnable(params->walk_enable),
controlPort(name() + ".control", *this, params.reg_map),
tlb(params.tlb_entries, params.tlb_assoc, params.tlb_policy),
configCache(params.cfg_entries, params.cfg_assoc, params.cfg_policy),
ipaCache(params.ipa_entries, params.ipa_assoc, params.ipa_policy),
walkCache({ { params.walk_S1L0, params.walk_S1L1,
params.walk_S1L2, params.walk_S1L3,
params.walk_S2L0, params.walk_S2L1,
params.walk_S2L2, params.walk_S2L3 } },
params.walk_assoc, params.walk_policy),
tlbEnable(params.tlb_enable),
configCacheEnable(params.cfg_enable),
ipaCacheEnable(params.ipa_enable),
walkCacheEnable(params.walk_enable),
tableWalkPortEnable(false),
walkCacheNonfinalEnable(params->wc_nonfinal_enable),
walkCacheS1Levels(params->wc_s1_levels),
walkCacheS2Levels(params->wc_s2_levels),
requestPortWidth(params->request_port_width),
tlbSem(params->tlb_slots),
walkCacheNonfinalEnable(params.wc_nonfinal_enable),
walkCacheS1Levels(params.wc_s1_levels),
walkCacheS2Levels(params.wc_s2_levels),
requestPortWidth(params.request_port_width),
tlbSem(params.tlb_slots),
ifcSmmuSem(1),
smmuIfcSem(1),
configSem(params->cfg_slots),
ipaSem(params->ipa_slots),
walkSem(params->walk_slots),
configSem(params.cfg_slots),
ipaSem(params.ipa_slots),
walkSem(params.walk_slots),
requestPortSem(1),
transSem(params->xlate_slots),
ptwSem(params->ptw_slots),
transSem(params.xlate_slots),
ptwSem(params.ptw_slots),
cycleSem(1),
tlbLat(params->tlb_lat),
ifcSmmuLat(params->ifc_smmu_lat),
smmuIfcLat(params->smmu_ifc_lat),
configLat(params->cfg_lat),
ipaLat(params->ipa_lat),
walkLat(params->walk_lat),
deviceInterfaces(params->device_interfaces),
tlbLat(params.tlb_lat),
ifcSmmuLat(params.ifc_smmu_lat),
smmuIfcLat(params.smmu_ifc_lat),
configLat(params.cfg_lat),
ipaLat(params.ipa_lat),
walkLat(params.walk_lat),
deviceInterfaces(params.device_interfaces),
commandExecutor(name() + ".cmd_exec", *this),
regsMap(params->reg_map),
regsMap(params.reg_map),
processCommandsEvent(this)
{
fatal_if(regsMap.size() != SMMU_REG_SIZE,
@@ -104,14 +104,14 @@ SMMUv3::SMMUv3(SMMUv3Params *params) :
memset(&regs, 0, sizeof(regs));
// Setup RO ID registers
regs.idr0 = params->smmu_idr0;
regs.idr1 = params->smmu_idr1;
regs.idr2 = params->smmu_idr2;
regs.idr3 = params->smmu_idr3;
regs.idr4 = params->smmu_idr4;
regs.idr5 = params->smmu_idr5;
regs.iidr = params->smmu_iidr;
regs.aidr = params->smmu_aidr;
regs.idr0 = params.smmu_idr0;
regs.idr1 = params.smmu_idr1;
regs.idr2 = params.smmu_idr2;
regs.idr3 = params.smmu_idr3;
regs.idr4 = params.smmu_idr4;
regs.idr5 = params.smmu_idr5;
regs.iidr = params.smmu_iidr;
regs.aidr = params.smmu_aidr;
// TODO: At the moment it possible to set the ID registers to hold
// any possible value. It would be nice to have a sanity check here
@@ -828,7 +828,7 @@ SMMUv3::getPort(const std::string &name, PortID id)
}
SMMUv3*
SMMUv3Params::create()
SMMUv3Params::create() const
{
return new SMMUv3(this);
return new SMMUv3(*this);
}

2
src/dev/arm/smmu_v3.hh
View File

@@ -165,7 +165,7 @@ class SMMUv3 : public ClockedObject
const PageTableOps *getPageTableOps(uint8_t trans_granule);
public:
SMMUv3(SMMUv3Params *p);
SMMUv3(const SMMUv3Params &p);
virtual ~SMMUv3() {}
virtual void init() override;

42
src/dev/arm/smmu_v3_deviceifc.cc
View File

@@ -43,33 +43,33 @@
#include "dev/arm/smmu_v3_transl.hh"
SMMUv3DeviceInterface::SMMUv3DeviceInterface(
const SMMUv3DeviceInterfaceParams *p) :
const SMMUv3DeviceInterfaceParams &p) :
ClockedObject(p),
smmu(nullptr),
microTLB(new SMMUTLB(p->utlb_entries,
p->utlb_assoc,
p->utlb_policy)),
mainTLB(new SMMUTLB(p->tlb_entries,
p->tlb_assoc,
p->tlb_policy)),
microTLBEnable(p->utlb_enable),
mainTLBEnable(p->tlb_enable),
microTLB(new SMMUTLB(p.utlb_entries,
p.utlb_assoc,
p.utlb_policy)),
mainTLB(new SMMUTLB(p.tlb_entries,
p.tlb_assoc,
p.tlb_policy)),
microTLBEnable(p.utlb_enable),
mainTLBEnable(p.tlb_enable),
devicePortSem(1),
microTLBSem(p->utlb_slots),
mainTLBSem(p->tlb_slots),
microTLBLat(p->utlb_lat),
mainTLBLat(p->tlb_lat),
microTLBSem(p.utlb_slots),
mainTLBSem(p.tlb_slots),
microTLBLat(p.utlb_lat),
mainTLBLat(p.tlb_lat),
devicePort(new SMMUDevicePort(csprintf("%s.device_port",
name()), *this)),
atsDevicePort(name() + ".atsDevicePort", *this),
atsMemPort(name() + ".atsMemPort", *this),
portWidth(p->port_width),
wrBufSlotsRemaining(p->wrbuf_slots),
xlateSlotsRemaining(p->xlate_slots),
portWidth(p.port_width),
wrBufSlotsRemaining(p.wrbuf_slots),
xlateSlotsRemaining(p.xlate_slots),
pendingMemAccesses(0),
prefetchEnable(p->prefetch_enable),
prefetchEnable(p.prefetch_enable),
prefetchReserveLastWay(
p->prefetch_reserve_last_way),
p.prefetch_reserve_last_way),
deviceNeedsRetry(false),
atsDeviceNeedsRetry(false),
sendDeviceRetryEvent(*this),
@@ -254,14 +254,14 @@ DrainState
SMMUv3DeviceInterface::drain()
{
// Wait until all SMMU translations are completed
if (xlateSlotsRemaining < params()->xlate_slots) {
if (xlateSlotsRemaining < params().xlate_slots) {
return DrainState::Draining;
}
return DrainState::Drained;
}
SMMUv3DeviceInterface*
SMMUv3DeviceInterfaceParams::create()
SMMUv3DeviceInterfaceParams::create() const
{
return new SMMUv3DeviceInterface(this);
return new SMMUv3DeviceInterface(*this);
}

6
src/dev/arm/smmu_v3_deviceifc.hh
View File

@@ -118,7 +118,7 @@ class SMMUv3DeviceInterface : public ClockedObject
Port& getPort(const std::string &name, PortID id) override;
public:
SMMUv3DeviceInterface(const SMMUv3DeviceInterfaceParams *p);
SMMUv3DeviceInterface(const SMMUv3DeviceInterfaceParams &p);
~SMMUv3DeviceInterface()
{
@@ -126,10 +126,10 @@ class SMMUv3DeviceInterface : public ClockedObject
delete mainTLB;
}
const SMMUv3DeviceInterfaceParams *
const SMMUv3DeviceInterfaceParams &
params() const
{
return static_cast<const SMMUv3DeviceInterfaceParams *>(_params);
return static_cast<const SMMUv3DeviceInterfaceParams &>(_params);
}
DrainState drain() override;

10
src/dev/arm/timer_a9global.cc
View File

@@ -46,9 +46,9 @@
#include "mem/packet.hh"
#include "mem/packet_access.hh"
A9GlobalTimer::A9GlobalTimer(Params *p)
: BasicPioDevice(p, 0x1C), gic(p->gic),
global_timer(name() + ".globaltimer", this, p->int_num)
A9GlobalTimer::A9GlobalTimer(const Params &p)
: BasicPioDevice(p, 0x1C), gic(p.gic),
global_timer(name() + ".globaltimer", this, p.int_num)
{
}
@@ -310,7 +310,7 @@ A9GlobalTimer::unserialize(CheckpointIn &cp)
}
A9GlobalTimer *
A9GlobalTimerParams::create()
A9GlobalTimerParams::create() const
{
return new A9GlobalTimer(this);
return new A9GlobalTimer(*this);
}

6
src/dev/arm/timer_a9global.hh
View File

@@ -143,16 +143,16 @@ class A9GlobalTimer : public BasicPioDevice
public:
typedef A9GlobalTimerParams Params;
const Params *
const Params &
params() const
{
return dynamic_cast<const Params *>(_params);
return dynamic_cast<const Params &>(_params);
}
/**
* The constructor for RealView just registers itself with the MMU.
* @param p params structure
*/
A9GlobalTimer(Params *p);
A9GlobalTimer(const Params &p);
/**
* Handle a read to the device

12
src/dev/arm/timer_cpulocal.cc
View File

@@ -46,7 +46,7 @@
#include "mem/packet.hh"
#include "mem/packet_access.hh"
CpuLocalTimer::CpuLocalTimer(Params *p)
CpuLocalTimer::CpuLocalTimer(const Params &p)
: BasicPioDevice(p, 0x38)
{
}
@@ -54,7 +54,7 @@ CpuLocalTimer::CpuLocalTimer(Params *p)
void
CpuLocalTimer::init()
{
auto p = params();
const auto &p = params();
// Initialize the timer registers for each per cpu timer
for (int i = 0; i < sys->threads.size(); i++) {
ThreadContext* tc = sys->threads[i];
@@ -63,8 +63,8 @@ CpuLocalTimer::init()
localTimer.emplace_back(
new Timer(oss.str(), this,
p->int_timer->get(tc),
p->int_watchdog->get(tc)));
p.int_timer->get(tc),
p.int_watchdog->get(tc)));
}
BasicPioDevice::init();
@@ -441,7 +441,7 @@ CpuLocalTimer::unserialize(CheckpointIn &cp)
}
CpuLocalTimer *
CpuLocalTimerParams::create()
CpuLocalTimerParams::create() const
{
return new CpuLocalTimer(this);
return new CpuLocalTimer(*this);
}

6
src/dev/arm/timer_cpulocal.hh
View File

@@ -157,16 +157,16 @@ class CpuLocalTimer : public BasicPioDevice
public:
typedef CpuLocalTimerParams Params;
const Params *
const Params &
params() const
{
return dynamic_cast<const Params *>(_params);
return dynamic_cast<const Params &>(_params);
}
/**
* The constructor for RealView just registers itself with the MMU.
* @param p params structure
*/
CpuLocalTimer(Params *p);
CpuLocalTimer(const Params &p);
/** Inits the local timers */
void init() override;

10
src/dev/arm/timer_sp804.cc
View File

@@ -45,10 +45,10 @@
#include "mem/packet.hh"
#include "mem/packet_access.hh"
Sp804::Sp804(Params *p)
Sp804::Sp804(const Params &p)
: AmbaPioDevice(p, 0x1000),
timer0(name() + ".timer0", this, p->int0->get(), p->clock0),
timer1(name() + ".timer1", this, p->int1->get(), p->clock1)
timer0(name() + ".timer0", this, p.int0->get(), p.clock0),
timer1(name() + ".timer1", this, p.int1->get(), p.clock1)
{
}
@@ -282,7 +282,7 @@ Sp804::unserialize(CheckpointIn &cp)
}
Sp804 *
Sp804Params::create()
Sp804Params::create() const
{
return new Sp804(this);
return new Sp804(*this);
}

6
src/dev/arm/timer_sp804.hh
View File

@@ -130,16 +130,16 @@ class Sp804 : public AmbaPioDevice
public:
typedef Sp804Params Params;
const Params *
const Params &
params() const
{
return dynamic_cast<const Params *>(_params);
return dynamic_cast<const Params &>(_params);
}
/**
* The constructor for RealView just registers itself with the MMU.
* @param p params structure
*/
Sp804(Params *p);
Sp804(const Params &p);
/**
* Handle a read to the device

28
src/dev/arm/ufs_device.cc
View File

@@ -72,14 +72,14 @@
/**
* Constructor and destructor functions of UFSHCM device
*/
UFSHostDevice::UFSSCSIDevice::UFSSCSIDevice(const UFSHostDeviceParams* p,
UFSHostDevice::UFSSCSIDevice::UFSSCSIDevice(const UFSHostDeviceParams &p,
uint32_t lun_id, const Callback &transfer_cb,
const Callback &read_cb):
SimObject(p),
flashDisk(p->image[lun_id]),
flashDevice(p->internalflash[lun_id]),
blkSize(p->img_blk_size),
lunAvail(p->image.size()),
flashDisk(p.image[lun_id]),
flashDevice(p.internalflash[lun_id]),
blkSize(p.img_blk_size),
lunAvail(p.image.size()),
diskSize(flashDisk->size()),
capacityLower((diskSize - 1) & 0xffffffff),
capacityUpper((diskSize - SectorSize) >> 32),
@@ -712,15 +712,15 @@ UFSHostDevice::UFSSCSIDevice::writeFlash(uint8_t* writeaddr, uint64_t offset,
* Constructor for the UFS Host device
*/
UFSHostDevice::UFSHostDevice(const UFSHostDeviceParams* p) :
UFSHostDevice::UFSHostDevice(const UFSHostDeviceParams &p) :
DmaDevice(p),
pioAddr(p->pio_addr),
pioAddr(p.pio_addr),
pioSize(0x0FFF),
pioDelay(p->pio_latency),
intNum(p->int_num),
gic(p->gic),
lunAvail(p->image.size()),
UFSSlots(p->ufs_slots - 1),
pioDelay(p.pio_latency),
intNum(p.int_num),
gic(p.gic),
lunAvail(p.image.size()),
UFSSlots(p.ufs_slots - 1),
readPendingNum(0),
writePendingNum(0),
activeDoorbells(0),
@@ -757,9 +757,9 @@ UFSHostDevice::UFSHostDevice(const UFSHostDeviceParams* p) :
*/
UFSHostDevice*
UFSHostDeviceParams::create()
UFSHostDeviceParams::create() const
{
return new UFSHostDevice(this);
return new UFSHostDevice(*this);
}

4
src/dev/arm/ufs_device.hh
View File

@@ -170,7 +170,7 @@ class UFSHostDevice : public DmaDevice
{
public:
UFSHostDevice(const UFSHostDeviceParams* p);
UFSHostDevice(const UFSHostDeviceParams &p);
DrainState drain() override;
void checkDrain();
@@ -541,7 +541,7 @@ class UFSHostDevice : public DmaDevice
/**
* Constructor and destructor
*/
UFSSCSIDevice(const UFSHostDeviceParams* p, uint32_t lun_id,
UFSSCSIDevice(const UFSHostDeviceParams &p, uint32_t lun_id,
const Callback &transfer_cb, const Callback &read_cb);
~UFSSCSIDevice();

12
src/dev/arm/vgic.cc
View File

@@ -45,10 +45,10 @@
#include "mem/packet.hh"
#include "mem/packet_access.hh"
VGic::VGic(const Params *p)
: PioDevice(p), gicvIIDR(p->gicv_iidr), platform(p->platform),
gic(p->gic), vcpuAddr(p->vcpu_addr), hvAddr(p->hv_addr),
pioDelay(p->pio_delay), maintInt(p->maint_int)
VGic::VGic(const Params &p)
: PioDevice(p), gicvIIDR(p.gicv_iidr), platform(p.platform),
gic(p.gic), vcpuAddr(p.vcpu_addr), hvAddr(p.hv_addr),
pioDelay(p.pio_delay), maintInt(p.maint_int)
{
for (int x = 0; x < VGIC_CPU_MAX; x++) {
postVIntEvent[x] = new EventFunctionWrapper(
@@ -554,7 +554,7 @@ VGic::vcpuIntData::unserialize(CheckpointIn &cp)
}
VGic *
VGicParams::create()
VGicParams::create() const
{
return new VGic(this);
return new VGic(*this);
}

8
src/dev/arm/vgic.hh
View File

@@ -186,13 +186,13 @@ class VGic : public PioDevice
struct std::array<vcpuIntData, VGIC_CPU_MAX> vcpuData;
public:
typedef VGicParams Params;
const Params *
typedef VGicParams Params;
const Params &
params() const
{
return dynamic_cast<const Params *>(_params);
return dynamic_cast<const Params &>(_params);
}
VGic(const Params *p);
VGic(const Params &p);
~VGic();
AddrRangeList getAddrRanges() const override;

12
src/dev/arm/vio_mmio.cc
View File

@@ -42,11 +42,11 @@
#include "mem/packet_access.hh"
#include "params/MmioVirtIO.hh"
MmioVirtIO::MmioVirtIO(const MmioVirtIOParams *params)
: BasicPioDevice(params, params->pio_size),
MmioVirtIO::MmioVirtIO(const MmioVirtIOParams &params)
: BasicPioDevice(params, params.pio_size),
hostFeaturesSelect(0), guestFeaturesSelect(0), pageSize(0),
interruptStatus(0), vio(*params->vio),
interrupt(params->interrupt->get())
interruptStatus(0), vio(*params.vio),
interrupt(params.interrupt->get())
{
fatal_if(!interrupt, "No MMIO VirtIO interrupt specified\n");
@@ -276,7 +276,7 @@ MmioVirtIO::setInterrupts(uint32_t value)
MmioVirtIO *
MmioVirtIOParams::create()
MmioVirtIOParams::create() const
{
return new MmioVirtIO(this);
return new MmioVirtIO(*this);
}

2
src/dev/arm/vio_mmio.hh
View File

@@ -47,7 +47,7 @@ struct MmioVirtIOParams;
class MmioVirtIO : public BasicPioDevice
{
public:
MmioVirtIO(const MmioVirtIOParams *params);
MmioVirtIO(const MmioVirtIOParams &params);
virtual ~MmioVirtIO();
protected: // BasicPioDevice

6
src/dev/arm/watchdog_sp805.cc
View File

@@ -42,7 +42,7 @@
#include "mem/packet_access.hh"
#include "params/Sp805.hh"
Sp805::Sp805(Sp805Params const* params)
Sp805::Sp805(const Sp805Params &params)
: AmbaIntDevice(params, 0x1000),
timeoutInterval(0xffffffff),
timeoutStartTick(MaxTick),
@@ -261,7 +261,7 @@ Sp805::unserialize(CheckpointIn &cp)
}
Sp805 *
Sp805Params::create()
Sp805Params::create() const
{
return new Sp805(this);
return new Sp805(*this);
}

2
src/dev/arm/watchdog_sp805.hh
View File

@@ -52,7 +52,7 @@ class Sp805Params;
class Sp805 : public AmbaIntDevice
{
public:
Sp805(Sp805Params const* params);
Sp805(const Sp805Params &params);
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;

8
src/dev/baddev.cc
View File

@@ -40,8 +40,8 @@
using namespace std;
BadDevice::BadDevice(Params *p)
: BasicPioDevice(p, 0x10), devname(p->devicename)
BadDevice::BadDevice(const Params &p)
: BasicPioDevice(p, 0x10), devname(p.devicename)
{
}
@@ -58,7 +58,7 @@ BadDevice::write(PacketPtr pkt)
}
BadDevice *
BadDeviceParams::create()
BadDeviceParams::create() const
{
return new BadDevice(this);
return new BadDevice(*this);
}

6
src/dev/baddev.hh
View File

@@ -52,10 +52,10 @@ class BadDevice : public BasicPioDevice
typedef BadDeviceParams Params;
protected:
const Params *
const Params &
params() const
{
return dynamic_cast<const Params *>(_params);
return dynamic_cast<const Params &>(_params);
}
public:
@@ -64,7 +64,7 @@ class BadDevice : public BasicPioDevice
* @param p object parameters
* @param a base address of the write
*/
BadDevice(Params *p);
BadDevice(const Params &p);
virtual Tick read(PacketPtr pkt);
virtual Tick write(PacketPtr pkt);

4
src/dev/dma_device.cc
View File

@@ -114,8 +114,8 @@ DmaPort::recvTimingResp(PacketPtr pkt)
return true;
}
DmaDevice::DmaDevice(const Params *p)
: PioDevice(p), dmaPort(this, sys, p->sid, p->ssid)
DmaDevice::DmaDevice(const Params &p)
: PioDevice(p), dmaPort(this, sys, p.sid, p.ssid)
{ }
void

2
src/dev/dma_device.hh
View File

@@ -169,7 +169,7 @@ class DmaDevice : public PioDevice
public:
typedef DmaDeviceParams Params;
DmaDevice(const Params *p);
DmaDevice(const Params &p);
virtual ~DmaDevice() { }
void dmaWrite(Addr addr, int size, Event *event, uint8_t *data,

2
src/dev/hsa/hsa_device.hh
View File

@@ -48,7 +48,7 @@ class HSADevice : public DmaDevice
public:
typedef HSADeviceParams Params;
HSADevice(const Params *p) : DmaDevice(p), hsaPP(p->hsapp)
HSADevice(const Params &p) : DmaDevice(p), hsaPP(p.hsapp)
{
assert(hsaPP);
hsaPP->setDevice(this);

4
src/dev/hsa/hsa_driver.cc
View File

@@ -45,8 +45,8 @@
#include "sim/proxy_ptr.hh"
#include "sim/syscall_emul_buf.hh"
HSADriver::HSADriver(HSADriverParams *p)
: EmulatedDriver(p), device(p->device), queueId(0)
HSADriver::HSADriver(const HSADriverParams &p)
: EmulatedDriver(p), device(p.device), queueId(0)
{
}

2
src/dev/hsa/hsa_driver.hh
View File

@@ -62,7 +62,7 @@ class ThreadContext;
class HSADriver : public EmulatedDriver
{
public:
HSADriver(HSADriverParams *p);
HSADriver(const HSADriverParams &p);
int open(ThreadContext *tc, int mode, int flags);
Addr mmap(ThreadContext *tc, Addr start, uint64_t length,

12
src/dev/hsa/hsa_packet_processor.cc
View File

@@ -70,12 +70,12 @@ HSAPP_EVENT_DESCRIPTION_GENERATOR(CmdQueueCmdDmaEvent)
HSAPP_EVENT_DESCRIPTION_GENERATOR(QueueProcessEvent)
HSAPP_EVENT_DESCRIPTION_GENERATOR(DepSignalsReadDmaEvent)
HSAPacketProcessor::HSAPacketProcessor(const Params *p)
: DmaDevice(p), numHWQueues(p->numHWQueues), pioAddr(p->pioAddr),
pioSize(PAGE_SIZE), pioDelay(10), pktProcessDelay(p->pktProcessDelay)
HSAPacketProcessor::HSAPacketProcessor(const Params &p)
: DmaDevice(p), numHWQueues(p.numHWQueues), pioAddr(p.pioAddr),
pioSize(PAGE_SIZE), pioDelay(10), pktProcessDelay(p.pktProcessDelay)
{
DPRINTF(HSAPacketProcessor, "%s:\n", __FUNCTION__);
hwSchdlr = new HWScheduler(this, p->wakeupDelay);
hwSchdlr = new HWScheduler(this, p.wakeupDelay);
regdQList.resize(numHWQueues);
for (int i = 0; i < numHWQueues; i++) {
regdQList[i] = new RQLEntry(this, i);
@@ -658,9 +658,9 @@ AQLRingBuffer::allocEntry(uint32_t nBufReq)
}
HSAPacketProcessor *
HSAPacketProcessorParams::create()
HSAPacketProcessorParams::create() const
{
return new HSAPacketProcessor(this);
return new HSAPacketProcessor(*this);
}
void

2
src/dev/hsa/hsa_packet_processor.hh
View File

@@ -309,7 +309,7 @@ class HSAPacketProcessor: public DmaDevice
const Tick pktProcessDelay;
typedef HSAPacketProcessorParams Params;
HSAPacketProcessor(const Params *p);
HSAPacketProcessor(const Params &p);
~HSAPacketProcessor();
void setDeviceQueueDesc(uint64_t hostReadIndexPointer,
uint64_t basePointer,

10
src/dev/i2c/bus.cc
View File

@@ -51,13 +51,13 @@ using std::map;
* 4KB - see e.g.
* http://infocenter.arm.com/help/topic/com.arm.doc.dui0440b/Bbajihec.html
*/
I2CBus::I2CBus(const I2CBusParams *p)
I2CBus::I2CBus(const I2CBusParams &p)
: BasicPioDevice(p, 0x1000), scl(1), sda(1), state(IDLE), currBit(7),
i2cAddr(0x00), message(0x00)
{
vector<I2CDevice*> devs = p->devices;
vector<I2CDevice*> devs = p.devices;
for (auto d : p->devices) {
for (auto d : p.devices) {
devices[d->i2cAddr()] = d;
}
}
@@ -236,7 +236,7 @@ I2CBus::unserialize(CheckpointIn &cp)
}
I2CBus*
I2CBusParams::create()
I2CBusParams::create() const
{
return new I2CBus(this);
return new I2CBus(*this);
}

2
src/dev/i2c/bus.hh
View File

@@ -140,7 +140,7 @@ class I2CBus : public BasicPioDevice
public:
I2CBus(const I2CBusParams* p);
I2CBus(const I2CBusParams &p);
Tick read(PacketPtr pkt) override;
Tick write(PacketPtr pkt) override;

4
src/dev/i2c/device.hh
View File

@@ -56,8 +56,8 @@ class I2CDevice : public SimObject
public:
I2CDevice(const I2CDeviceParams* p)
: SimObject(p), _addr(p->i2c_addr)
I2CDevice(const I2CDeviceParams &p)
: SimObject(p), _addr(p.i2c_addr)
{ }
virtual ~I2CDevice() { }

10
src/dev/io_device.cc
View File

@@ -44,8 +44,8 @@
#include "debug/AddrRanges.hh"
#include "sim/system.hh"
PioDevice::PioDevice(const Params *p)
: ClockedObject(p), sys(p->system), pioPort(this)
PioDevice::PioDevice(const Params &p)
: ClockedObject(p), sys(p.system), pioPort(this)
{}
PioDevice::~PioDevice()
@@ -69,9 +69,9 @@ PioDevice::getPort(const std::string &if_name, PortID idx)
return ClockedObject::getPort(if_name, idx);
}
BasicPioDevice::BasicPioDevice(const Params *p, Addr size)
: PioDevice(p), pioAddr(p->pio_addr), pioSize(size),
pioDelay(p->pio_latency)
BasicPioDevice::BasicPioDevice(const Params &p, Addr size)
: PioDevice(p), pioAddr(p.pio_addr), pioSize(size),
pioDelay(p.pio_latency)
{}
AddrRangeList

12
src/dev/io_device.hh
View File

@@ -129,13 +129,13 @@ class PioDevice : public ClockedObject
public:
typedef PioDeviceParams Params;
PioDevice(const Params *p);
PioDevice(const Params &p);
virtual ~PioDevice();
const Params *
const Params &
params() const
{
return dynamic_cast<const Params *>(_params);
return dynamic_cast<const Params &>(_params);
}
void init() override;
@@ -161,12 +161,12 @@ class BasicPioDevice : public PioDevice
public:
typedef BasicPioDeviceParams Params;
BasicPioDevice(const Params *p, Addr size);
BasicPioDevice(const Params &p, Addr size);
const Params *
const Params &
params() const
{
return dynamic_cast<const Params *>(_params);
return dynamic_cast<const Params &>(_params);
}
/**

28
src/dev/isa_fake.cc
View File

@@ -40,13 +40,13 @@
using namespace std;
IsaFake::IsaFake(Params *p)
: BasicPioDevice(p, p->ret_bad_addr ? 0 : p->pio_size)
IsaFake::IsaFake(const Params &p)
: BasicPioDevice(p, p.ret_bad_addr ? 0 : p.pio_size)
{
retData8 = p->ret_data8;
retData16 = p->ret_data16;
retData32 = p->ret_data32;
retData64 = p->ret_data64;
retData8 = p.ret_data8;
retData16 = p.ret_data16;
retData32 = p.ret_data32;
retData64 = p.ret_data64;
}
Tick
@@ -54,10 +54,10 @@ IsaFake::read(PacketPtr pkt)
{
pkt->makeAtomicResponse();
if (params()->warn_access != "")
if (params().warn_access != "")
warn("Device %s accessed by read to address %#x size=%d\n",
name(), pkt->getAddr(), pkt->getSize());
if (params()->ret_bad_addr) {
if (params().ret_bad_addr) {
DPRINTF(IsaFake, "read to bad address va=%#x size=%d\n",
pkt->getAddr(), pkt->getSize());
pkt->setBadAddress();
@@ -79,7 +79,7 @@ IsaFake::read(PacketPtr pkt)
pkt->setLE(retData8);
break;
default:
if (params()->fake_mem)
if (params().fake_mem)
std::memset(pkt->getPtr<uint8_t>(), 0, pkt->getSize());
else
panic("invalid access size! Device being accessed by cache?\n");
@@ -92,7 +92,7 @@ Tick
IsaFake::write(PacketPtr pkt)
{
pkt->makeAtomicResponse();
if (params()->warn_access != "") {
if (params().warn_access != "") {
uint64_t data;
switch (pkt->getSize()) {
case sizeof(uint64_t):
@@ -113,7 +113,7 @@ IsaFake::write(PacketPtr pkt)
warn("Device %s accessed by write to address %#x size=%d data=%#x\n",
name(), pkt->getAddr(), pkt->getSize(), data);
}
if (params()->ret_bad_addr) {
if (params().ret_bad_addr) {
DPRINTF(IsaFake, "write to bad address va=%#x size=%d \n",
pkt->getAddr(), pkt->getSize());
pkt->setBadAddress();
@@ -121,7 +121,7 @@ IsaFake::write(PacketPtr pkt)
DPRINTF(IsaFake, "write - va=%#x size=%d \n",
pkt->getAddr(), pkt->getSize());
if (params()->update_data) {
if (params().update_data) {
switch (pkt->getSize()) {
case sizeof(uint64_t):
retData64 = pkt->getLE<uint64_t>();
@@ -144,7 +144,7 @@ IsaFake::write(PacketPtr pkt)
}
IsaFake *
IsaFakeParams::create()
IsaFakeParams::create() const
{
return new IsaFake(this);
return new IsaFake(*this);
}

6
src/dev/isa_fake.hh
View File

@@ -56,16 +56,16 @@ class IsaFake : public BasicPioDevice
public:
typedef IsaFakeParams Params;
const Params *
const Params &
params() const
{
return dynamic_cast<const Params *>(_params);
return dynamic_cast<const Params &>(_params);
}
/**
* The constructor for Isa Fake just registers itself with the MMU.
* @param p params structure
*/
IsaFake(Params *p);
IsaFake(const Params &p);
/**
* This read always returns -1.

8
src/dev/mips/malta.cc
View File

@@ -45,8 +45,8 @@
using namespace std;
Malta::Malta(const Params *p)
: Platform(p), system(p->system)
Malta::Malta(const Params &p)
: Platform(p), system(p.system)
{
for (int i = 0; i < Malta::Max_CPUs; i++)
intr_sum_type[i] = 0;
@@ -97,7 +97,7 @@ Malta::unserialize(CheckpointIn &cp)
}
Malta *
MaltaParams::create()
MaltaParams::create() const
{
return new Malta(this);
return new Malta(*this);
}

2
src/dev/mips/malta.hh
View File

@@ -79,7 +79,7 @@ class Malta : public Platform
* @param intctrl pointer to the interrupt controller
*/
typedef MaltaParams Params;
Malta(const Params *p);
Malta(const Params &p);
/**
* Cause the cpu to post a serial interrupt to the CPU.

8
src/dev/mips/malta_cchip.cc
View File

@@ -50,8 +50,8 @@
using namespace std;
MaltaCChip::MaltaCChip(Params *p)
: BasicPioDevice(p, 0xfffffff), malta(p->malta)
MaltaCChip::MaltaCChip(const Params &p)
: BasicPioDevice(p, 0xfffffff), malta(p.malta)
{
warn("MaltaCCHIP::MaltaCChip() not implemented.");
@@ -141,8 +141,8 @@ MaltaCChip::unserialize(CheckpointIn &cp)
}
MaltaCChip *
MaltaCChipParams::create()
MaltaCChipParams::create() const
{
return new MaltaCChip(this);
return new MaltaCChip(*this);
}

6
src/dev/mips/malta_cchip.hh
View File

@@ -78,10 +78,10 @@ class MaltaCChip : public BasicPioDevice
public:
typedef MaltaCChipParams Params;
const Params *
const Params &
params() const
{
return dynamic_cast<const Params *>(_params);
return dynamic_cast<const Params &>(_params);
}
/**
@@ -89,7 +89,7 @@ class MaltaCChip : public BasicPioDevice
* device register to 0.
* @param p params struct
*/
MaltaCChip(Params *p);
MaltaCChip(const Params &p);
Tick read(PacketPtr pkt) override;

18
src/dev/mips/malta_io.cc
View File

@@ -53,15 +53,15 @@
using namespace std;
MaltaIO::RTC::RTC(const string &name, const MaltaIOParams *p)
: MC146818(p->malta, name, p->time, p->year_is_bcd, p->frequency),
malta(p->malta)
MaltaIO::RTC::RTC(const string &name, const MaltaIOParams &p)
: MC146818(p.malta, name, p.time, p.year_is_bcd, p.frequency),
malta(p.malta)
{
}
MaltaIO::MaltaIO(const Params *p)
: BasicPioDevice(p, 0x100), malta(p->malta),
pitimer(this, p->name + "pitimer"), rtc(p->name + ".rtc", p)
MaltaIO::MaltaIO(const Params &p)
: BasicPioDevice(p, 0x100), malta(p.malta),
pitimer(this, p.name + "pitimer"), rtc(p.name + ".rtc", p)
{
// set the back pointer from malta to myself
malta->io = this;
@@ -74,7 +74,7 @@ MaltaIO::MaltaIO(const Params *p)
Tick
MaltaIO::frequency() const
{
return SimClock::Frequency / params()->frequency;
return SimClock::Frequency / params().frequency;
}
Tick
@@ -145,7 +145,7 @@ MaltaIO::startup()
}
MaltaIO *
MaltaIOParams::create()
MaltaIOParams::create() const
{
return new MaltaIO(this);
return new MaltaIO(*this);
}

8
src/dev/mips/malta_io.hh
View File

@@ -53,7 +53,7 @@ class MaltaIO : public BasicPioDevice
{
public:
Malta *malta;
RTC(const std::string &name, const MaltaIOParams *p);
RTC(const std::string &name, const MaltaIOParams &p);
protected:
void handleEvent()
@@ -104,17 +104,17 @@ class MaltaIO : public BasicPioDevice
typedef MaltaIOParams Params;
const Params *
const Params &
params() const
{
return dynamic_cast<const Params *>(_params);
return dynamic_cast<const Params &>(_params);
}
/**
* Initialize all the data for devices supported by Malta I/O.
* @param p pointer to Params struct
*/
MaltaIO(const Params *p);
MaltaIO(const Params &p);
Tick read(PacketPtr pkt) override;
Tick write(PacketPtr pkt) override;

36
src/dev/net/dist_etherlink.cc
View File

@@ -68,32 +68,32 @@
using namespace std;
DistEtherLink::DistEtherLink(const Params *p)
: SimObject(p), linkDelay(p->delay)
DistEtherLink::DistEtherLink(const Params &p)
: SimObject(p), linkDelay(p.delay)
{
DPRINTF(DistEthernet,"DistEtherLink::DistEtherLink() "
"link delay:%llu ticksPerByte:%f\n", p->delay, p->speed);
"link delay:%llu ticksPerByte:%f\n", p.delay, p.speed);
txLink = new TxLink(name() + ".link0", this, p->speed, p->delay_var,
p->dump);
rxLink = new RxLink(name() + ".link1", this, p->delay, p->dump);
txLink = new TxLink(name() + ".link0", this, p.speed, p.delay_var,
p.dump);
rxLink = new RxLink(name() + ".link1", this, p.delay, p.dump);
Tick sync_repeat;
if (p->sync_repeat != 0) {
if (p->sync_repeat != p->delay)
if (p.sync_repeat != 0) {
if (p.sync_repeat != p.delay)
warn("DistEtherLink(): sync_repeat is %lu and linkdelay is %lu",
p->sync_repeat, p->delay);
sync_repeat = p->sync_repeat;
p.sync_repeat, p.delay);
sync_repeat = p.sync_repeat;
} else {
sync_repeat = p->delay;
sync_repeat = p.delay;
}
// create the dist (TCP) interface to talk to the peer gem5 processes.
distIface = new TCPIface(p->server_name, p->server_port,
p->dist_rank, p->dist_size,
p->sync_start, sync_repeat, this,
p->dist_sync_on_pseudo_op, p->is_switch,
p->num_nodes);
distIface = new TCPIface(p.server_name, p.server_port,
p.dist_rank, p.dist_size,
p.sync_start, sync_repeat, this,
p.dist_sync_on_pseudo_op, p.is_switch,
p.num_nodes);
localIface = new LocalIface(name() + ".int0", txLink, rxLink, distIface);
}
@@ -254,9 +254,9 @@ DistEtherLink::LocalIface::LocalIface(const std::string &name,
}
DistEtherLink *
DistEtherLinkParams::create()
DistEtherLinkParams::create() const
{
return new DistEtherLink(this);
return new DistEtherLink(*this);
}

6
src/dev/net/dist_etherlink.hh
View File

@@ -212,13 +212,13 @@ class DistEtherLink : public SimObject
public:
typedef DistEtherLinkParams Params;
DistEtherLink(const Params *p);
DistEtherLink(const Params &p);
~DistEtherLink();
const Params *
const Params &
params() const
{
return dynamic_cast<const Params *>(_params);
return dynamic_cast<const Params &>(_params);
}
Port &getPort(const std::string &if_name,

10
src/dev/net/etherbus.cc
View File

@@ -48,10 +48,10 @@
using namespace std;
EtherBus::EtherBus(const Params *p)
: SimObject(p), ticksPerByte(p->speed), loopback(p->loopback),
EtherBus::EtherBus(const Params &p)
: SimObject(p), ticksPerByte(p.speed), loopback(p.loopback),
event([this]{ txDone(); }, "ethernet bus completion"),
sender(0), dump(p->dump)
sender(0), dump(p.dump)
{
}
@@ -107,7 +107,7 @@ EtherBus::send(EtherInt *sndr, EthPacketPtr &pkt)
}
EtherBus *
EtherBusParams::create()
EtherBusParams::create() const
{
return new EtherBus(this);
return new EtherBus(*this);
}

6
src/dev/net/etherbus.hh
View File

@@ -56,13 +56,13 @@ class EtherBus : public SimObject
public:
typedef EtherBusParams Params;
EtherBus(const Params *p);
EtherBus(const Params &p);
virtual ~EtherBus() {}
const Params *
const Params &
params() const
{
return dynamic_cast<const Params *>(_params);
return dynamic_cast<const Params &>(_params);
}
void txDone();

12
src/dev/net/etherdevice.hh
View File

@@ -46,14 +46,14 @@ class EtherDevice : public PciDevice
{
public:
typedef EtherDeviceParams Params;
EtherDevice(const Params *params)
EtherDevice(const Params &params)
: PciDevice(params)
{}
const Params *
const Params &
params() const
{
return dynamic_cast<const Params *>(_params);
return dynamic_cast<const Params &>(_params);
}
public:
@@ -124,14 +124,14 @@ class EtherDevice : public PciDevice
class EtherDevBase : public EtherDevice
{
public:
EtherDevBase(const EtherDevBaseParams *params)
EtherDevBase(const EtherDevBaseParams &params)
: EtherDevice(params)
{}
const EtherDevBaseParams *
const EtherDevBaseParams &
params() const
{
return dynamic_cast<const EtherDevBaseParams *>(_params);
return dynamic_cast<const EtherDevBaseParams &>(_params);
}
};

10
src/dev/net/etherdump.cc
View File

@@ -42,9 +42,9 @@
using std::string;
EtherDump::EtherDump(const Params *p)
: SimObject(p), stream(simout.create(p->file, true)->stream()),
maxlen(p->maxlen)
EtherDump::EtherDump(const Params &p)
: SimObject(p), stream(simout.create(p.file, true)->stream()),
maxlen(p.maxlen)
{
}
@@ -102,7 +102,7 @@ EtherDump::dumpPacket(EthPacketPtr &packet)
}
EtherDump *
EtherDumpParams::create()
EtherDumpParams::create() const
{
return new EtherDump(this);
return new EtherDump(*this);
}

2
src/dev/net/etherdump.hh
View File

@@ -52,7 +52,7 @@ class EtherDump : public SimObject
public:
typedef EtherDumpParams Params;
EtherDump(const Params *p);
EtherDump(const Params &p);
inline void dump(EthPacketPtr &pkt) { dumpPacket(pkt); }
};

14
src/dev/net/etherlink.cc
View File

@@ -63,13 +63,13 @@
using namespace std;
EtherLink::EtherLink(const Params *p)
EtherLink::EtherLink(const Params &p)
: SimObject(p)
{
link[0] = new Link(name() + ".link0", this, 0, p->speed,
p->delay, p->delay_var, p->dump);
link[1] = new Link(name() + ".link1", this, 1, p->speed,
p->delay, p->delay_var, p->dump);
link[0] = new Link(name() + ".link0", this, 0, p.speed,
p.delay, p.delay_var, p.dump);
link[1] = new Link(name() + ".link1", this, 1, p.speed,
p.delay, p.delay_var, p.dump);
interface[0] = new Interface(name() + ".int0", link[0], link[1]);
interface[1] = new Interface(name() + ".int1", link[1], link[0]);
@@ -266,7 +266,7 @@ EtherLink::Link::unserialize(const string &base, CheckpointIn &cp)
}
EtherLink *
EtherLinkParams::create()
EtherLinkParams::create() const
{
return new EtherLink(this);
return new EtherLink(*this);
}

6
src/dev/net/etherlink.hh
View File

@@ -140,13 +140,13 @@ class EtherLink : public SimObject
public:
typedef EtherLinkParams Params;
EtherLink(const Params *p);
EtherLink(const Params &p);
virtual ~EtherLink();
const Params *
const Params &
params() const
{
return dynamic_cast<const Params *>(_params);
return dynamic_cast<const Params &>(_params);
}
Port &getPort(const std::string &if_name,

14
src/dev/net/etherswitch.cc
View File

@@ -39,14 +39,14 @@
using namespace std;
EtherSwitch::EtherSwitch(const Params *p)
: SimObject(p), ttl(p->time_to_live)
EtherSwitch::EtherSwitch(const Params &p)
: SimObject(p), ttl(p.time_to_live)
{
for (int i = 0; i < p->port_interface_connection_count; ++i) {
for (int i = 0; i < p.port_interface_connection_count; ++i) {
std::string interfaceName = csprintf("%s.interface%d", name(), i);
Interface *interface = new Interface(interfaceName, this,
p->output_buffer_size, p->delay,
p->delay_var, p->fabric_speed, i);
p.output_buffer_size, p.delay,
p.delay_var, p.fabric_speed, i);
interfaces.push_back(interface);
}
}
@@ -347,7 +347,7 @@ EtherSwitch::Interface::PortFifo::unserialize(CheckpointIn &cp)
}
EtherSwitch *
EtherSwitchParams::create()
EtherSwitchParams::create() const
{
return new EtherSwitch(this);
return new EtherSwitch(*this);
}

7
src/dev/net/etherswitch.hh
View File

@@ -50,12 +50,13 @@ class EtherSwitch : public SimObject
public:
typedef EtherSwitchParams Params;
EtherSwitch(const Params *p);
EtherSwitch(const Params &p);
~EtherSwitch();
const Params * params() const
const Params &
params() const
{
return dynamic_cast<const Params*>(_params);
return dynamic_cast<const Params &>(_params);
}
Port &getPort(const std::string &if_name,

24
src/dev/net/ethertap.cc
View File

@@ -89,8 +89,8 @@ class TapEvent : public PollEvent
}
};
EtherTapBase::EtherTapBase(const Params *p)
: SimObject(p), buflen(p->bufsz), dump(p->dump), event(NULL),
EtherTapBase::EtherTapBase(const Params &p)
: SimObject(p), buflen(p.bufsz), dump(p.dump), event(NULL),
interface(NULL),
txEvent([this]{ retransmit(); }, "EtherTapBase retransmit")
{
@@ -283,12 +283,12 @@ TapListener::accept()
}
EtherTapStub::EtherTapStub(const Params *p) : EtherTapBase(p), socket(-1)
EtherTapStub::EtherTapStub(const Params &p) : EtherTapBase(p), socket(-1)
{
if (ListenSocket::allDisabled())
fatal("All listeners are disabled! EtherTapStub can't work!");
listener = new TapListener(this, p->port);
listener = new TapListener(this, p.port);
listener->listen();
}
@@ -399,16 +399,16 @@ EtherTapStub::sendReal(const void *data, size_t len)
#if USE_TUNTAP
EtherTap::EtherTap(const Params *p) : EtherTapBase(p)
EtherTap::EtherTap(const Params &p) : EtherTapBase(p)
{
int fd = open(p->tun_clone_device.c_str(), O_RDWR | O_NONBLOCK);
int fd = open(p.tun_clone_device.c_str(), O_RDWR | O_NONBLOCK);
if (fd < 0)
panic("Couldn't open %s.\n", p->tun_clone_device);
panic("Couldn't open %s.\n", p.tun_clone_device);
struct ifreq ifr;
memset(&ifr, 0, sizeof(ifr));
ifr.ifr_flags = IFF_TAP | IFF_NO_PI;
strncpy(ifr.ifr_name, p->tap_device_name.c_str(), IFNAMSIZ - 1);
strncpy(ifr.ifr_name, p.tap_device_name.c_str(), IFNAMSIZ - 1);
if (ioctl(fd, TUNSETIFF, (void *)&ifr) < 0)
panic("Failed to access tap device %s.\n", ifr.ifr_name);
@@ -470,15 +470,15 @@ EtherTap::sendReal(const void *data, size_t len)
}
EtherTap *
EtherTapParams::create()
EtherTapParams::create() const
{
return new EtherTap(this);
return new EtherTap(*this);
}
#endif
EtherTapStub *
EtherTapStubParams::create()
EtherTapStubParams::create() const
{
return new EtherTapStub(this);
return new EtherTapStub(*this);
}

18
src/dev/net/ethertap.hh
View File

@@ -57,13 +57,13 @@ class EtherTapBase : public SimObject
{
public:
typedef EtherTapBaseParams Params;
EtherTapBase(const Params *p);
EtherTapBase(const Params &p);
virtual ~EtherTapBase();
const Params *
const Params &
params() const
{
return dynamic_cast<const Params *>(_params);
return dynamic_cast<const Params &>(_params);
}
void serialize(CheckpointOut &cp) const override;
@@ -137,13 +137,13 @@ class EtherTapStub : public EtherTapBase
{
public:
typedef EtherTapStubParams Params;
EtherTapStub(const Params *p);
EtherTapStub(const Params &p);
~EtherTapStub();
const Params *
const Params &
params() const
{
return dynamic_cast<const Params *>(_params);
return dynamic_cast<const Params &>(_params);
}
void serialize(CheckpointOut &cp) const override;
@@ -172,13 +172,13 @@ class EtherTap : public EtherTapBase
{
public:
typedef EtherTapParams Params;
EtherTap(const Params *p);
EtherTap(const Params &p);
~EtherTap();
const Params *
const Params &
params() const
{
return dynamic_cast<const Params *>(_params);
return dynamic_cast<const Params &>(_params);
}

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