misc: Standardize the way create() constructs SimObjects.

The create() method on Params structs usually instantiate SimObjects
using a constructor which takes the Params struct as a parameter
somehow. There has been a lot of needless variation in how that was
done, making it annoying to pass Params down to base classes. Some of
the different forms were:

const Params &
Params &
Params *
const Params *
Params const*

This change goes through and fixes up every constructor and every
create() method to use the const Params & form. We use a reference
because the Params struct should never be null. We use const because
neither the create method nor the consuming object should modify the
record of the parameters as they came in from the config. That would
make consuming them not idempotent, and make it impossible to tell what
the actual simulation configuration was since it would change from any
user visible form (config script, config.ini, dot pdf output).

Change-Id: I77453cba52fdcfd5f4eec92dfb0bddb5a9945f31
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35938
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/arm/fastmodel/CortexA76/cortex_a76.cc

@@ -204,13 +204,13 @@ CortexA76Cluster::getPort(const std::string &if_name, PortID idx)
 } // namespace FastModel
 
 FastModel::CortexA76 *
-FastModelCortexA76Params::create()
+FastModelCortexA76Params::create() const
 {
     return new FastModel::CortexA76(*this);
 }
 
 FastModel::CortexA76Cluster *
-FastModelCortexA76ClusterParams::create()
+FastModelCortexA76ClusterParams::create() const
 {
     return new FastModel::CortexA76Cluster(*this);
 }

src/arch/arm/fastmodel/CortexA76/evs.cc

@@ -155,25 +155,25 @@ template class ScxEvsCortexA76<ScxEvsCortexA76x4Types>;
 } // namespace FastModel
 
 FastModel::ScxEvsCortexA76x1 *
-FastModelScxEvsCortexA76x1Params::create()
+FastModelScxEvsCortexA76x1Params::create() const
 {
     return new FastModel::ScxEvsCortexA76x1(name.c_str(), *this);
 }
 
 FastModel::ScxEvsCortexA76x2 *
-FastModelScxEvsCortexA76x2Params::create()
+FastModelScxEvsCortexA76x2Params::create() const
 {
     return new FastModel::ScxEvsCortexA76x2(name.c_str(), *this);
 }
 
 FastModel::ScxEvsCortexA76x3 *
-FastModelScxEvsCortexA76x3Params::create()
+FastModelScxEvsCortexA76x3Params::create() const
 {
     return new FastModel::ScxEvsCortexA76x3(name.c_str(), *this);
 }
 
 FastModel::ScxEvsCortexA76x4 *
-FastModelScxEvsCortexA76x4Params::create()
+FastModelScxEvsCortexA76x4Params::create() const
 {
     return new FastModel::ScxEvsCortexA76x4(name.c_str(), *this);
 }

src/arch/arm/fastmodel/CortexR52/cortex_r52.cc

@@ -93,7 +93,7 @@ CortexR52::getPort(const std::string &if_name, PortID idx)
     }
 }
 
-CortexR52Cluster::CortexR52Cluster(Params &p) :
+CortexR52Cluster::CortexR52Cluster(const Params &p) :
     SimObject(&p), _params(p), cores(p.cores), evs(p.evs)
 {
     for (int i = 0; i < p.cores.size(); i++)
@@ -162,13 +162,13 @@ CortexR52Cluster::getPort(const std::string &if_name, PortID idx)
 } // namespace FastModel
 
 FastModel::CortexR52 *
-FastModelCortexR52Params::create()
+FastModelCortexR52Params::create() const
 {
     return new FastModel::CortexR52(*this);
 }
 
 FastModel::CortexR52Cluster *
-FastModelCortexR52ClusterParams::create()
+FastModelCortexR52ClusterParams::create() const
 {
     return new FastModel::CortexR52Cluster(*this);
 }

src/arch/arm/fastmodel/CortexR52/cortex_r52.hh

@@ -62,8 +62,8 @@ class CortexR52 : public Iris::CPU<CortexR52TC>
     const Params &params() { return _params; }
 
   public:
-    CortexR52(Params &p) : Base(&p, scx::scx_get_iris_connection_interface()),
-        _params(p)
+    CortexR52(const Params &p) :
+        Base(&p, scx::scx_get_iris_connection_interface()), _params(p)
     {}
 
     template <class T>
@@ -95,7 +95,7 @@ class CortexR52Cluster : public SimObject
     CortexR52 *getCore(int num) const { return cores.at(num); }
     sc_core::sc_module *getEvs() const { return evs; }
 
-    CortexR52Cluster(Params &p);
+    CortexR52Cluster(const Params &p);
     const Params &params() { return _params; }
 
     Port &getPort(const std::string &if_name,

src/arch/arm/fastmodel/CortexR52/evs.cc

@@ -131,25 +131,25 @@ template class ScxEvsCortexR52<ScxEvsCortexR52x4Types>;
 } // namespace FastModel
 
 FastModel::ScxEvsCortexR52x1 *
-FastModelScxEvsCortexR52x1Params::create()
+FastModelScxEvsCortexR52x1Params::create() const
 {
     return new FastModel::ScxEvsCortexR52x1(name.c_str(), *this);
 }
 
 FastModel::ScxEvsCortexR52x2 *
-FastModelScxEvsCortexR52x2Params::create()
+FastModelScxEvsCortexR52x2Params::create() const
 {
     return new FastModel::ScxEvsCortexR52x2(name.c_str(), *this);
 }
 
 FastModel::ScxEvsCortexR52x3 *
-FastModelScxEvsCortexR52x3Params::create()
+FastModelScxEvsCortexR52x3Params::create() const
 {
     return new FastModel::ScxEvsCortexR52x3(name.c_str(), *this);
 }
 
 FastModel::ScxEvsCortexR52x4 *
-FastModelScxEvsCortexR52x4Params::create()
+FastModelScxEvsCortexR52x4Params::create() const
 {
     return new FastModel::ScxEvsCortexR52x4(name.c_str(), *this);
 }

src/arch/arm/fastmodel/GIC/gic.cc

@@ -360,13 +360,13 @@ GIC::supportsVersion(GicVersion version)
 } // namespace FastModel
 
 FastModel::SCGIC *
-SCFastModelGICParams::create()
+SCFastModelGICParams::create() const
 {
     return new FastModel::SCGIC(*this, name.c_str());
 }
 
 FastModel::GIC *
-FastModelGICParams::create()
+FastModelGICParams::create() const
 {
     return new FastModel::GIC(*this);
 }

src/arch/arm/fastmodel/amba_from_tlm_bridge.cc

@@ -54,7 +54,7 @@ AmbaFromTlmBridge64::gem5_getPort(const std::string &if_name, int idx)
 } // namespace FastModel
 
 FastModel::AmbaFromTlmBridge64 *
-AmbaFromTlmBridge64Params::create()
+AmbaFromTlmBridge64Params::create() const
 {
     return new FastModel::AmbaFromTlmBridge64(name.c_str());
 }

src/arch/arm/fastmodel/amba_to_tlm_bridge.cc

@@ -52,7 +52,7 @@ AmbaToTlmBridge64::gem5_getPort(const std::string &if_name, int idx)
 } // namespace FastModel
 
 FastModel::AmbaToTlmBridge64 *
-AmbaToTlmBridge64Params::create()
+AmbaToTlmBridge64Params::create() const
 {
     return new FastModel::AmbaToTlmBridge64(name.c_str());
 }

src/arch/arm/fastmodel/iris/cpu.cc

@@ -34,7 +34,7 @@
 namespace Iris
 {
 
-BaseCPU::BaseCPU(BaseCPUParams *params, sc_core::sc_module *_evs) :
+BaseCPU::BaseCPU(const BaseCPUParams &params, sc_core::sc_module *_evs) :
     ::BaseCPU::BaseCPU(params), evs(_evs),
     clockEvent(nullptr), periodAttribute(nullptr)
 {

src/arch/arm/fastmodel/iris/cpu.hh

@@ -58,7 +58,7 @@ static const std::string SendFunctionalAttributeName = "gem5_send_functional";
 class BaseCPU : public ::BaseCPU
 {
   public:
-    BaseCPU(BaseCPUParams *params, sc_core::sc_module *_evs);
+    BaseCPU(const BaseCPUParams &params, sc_core::sc_module *_evs);
     virtual ~BaseCPU();
 
     Port &
@@ -128,18 +128,19 @@ template <class TC>
 class CPU : public Iris::BaseCPU
 {
   public:
-    CPU(IrisBaseCPUParams *params, iris::IrisConnectionInterface *iris_if) :
-        BaseCPU(params, params->evs)
+    CPU(const IrisBaseCPUParams &params,
+            iris::IrisConnectionInterface *iris_if) :
+        BaseCPU(params, params.evs)
     {
         const std::string parent_path = evs->name();
-        System *sys = params->system;
+        System *sys = params.system;
 
         int thread_id = 0;
-        for (const std::string &sub_path: params->thread_paths) {
+        for (const std::string &sub_path: params.thread_paths) {
             std::string path = parent_path + "." + sub_path;
             auto id = thread_id++;
-            auto *tc = new TC(this, id, sys, params->dtb, params->itb,
-                    params->isa[id], iris_if, path);
+            auto *tc = new TC(this, id, sys, params.dtb, params.itb,
+                    params.isa[id], iris_if, path);
             threadContexts.push_back(tc);
         }
     }

src/arch/arm/fastmodel/iris/interrupts.cc

@@ -108,7 +108,7 @@ Iris::Interrupts::unserialize(CheckpointIn &cp)
 }
 
 Iris::Interrupts *
-IrisInterruptsParams::create()
+IrisInterruptsParams::create() const
 {
-    return new Iris::Interrupts(this);
+    return new Iris::Interrupts(*this);
 }

src/arch/arm/fastmodel/iris/interrupts.hh

@@ -40,13 +40,13 @@ class Interrupts : public BaseInterrupts
   public:
     typedef IrisInterruptsParams Params;
 
-    const Params *
+    const Params &
     params() const
     {
-        return dynamic_cast<const Params *>(_params);
+        return dynamic_cast<const Params &>(_params);
     }
 
-    Interrupts(Params *p) : BaseInterrupts(p) {}
+    Interrupts(const Params &p) : BaseInterrupts(p) {}
 
     bool checkInterrupts() const override { return false; }
     Fault getInterrupt() override { return NoFault; }

src/arch/arm/fastmodel/iris/isa.cc

@@ -42,7 +42,7 @@ Iris::ISA::serialize(CheckpointOut &cp) const
 }
 
 Iris::ISA *
-IrisISAParams::create()
+IrisISAParams::create() const
 {
-    return new Iris::ISA(this);
+    return new Iris::ISA(*this);
 }

src/arch/arm/fastmodel/iris/isa.hh

@@ -36,7 +36,7 @@ namespace Iris
 class ISA : public BaseISA
 {
   public:
-    ISA(const Params *p) : BaseISA(p) {}
+    ISA(const Params &p) : BaseISA(p) {}
 
     void serialize(CheckpointOut &cp) const;
 };

src/arch/arm/fastmodel/iris/mmu.cc

@@ -38,7 +38,7 @@
 #include "arch/arm/fastmodel/iris/mmu.hh"
 
 Iris::MMU *
-IrisMMUParams::create()
+IrisMMUParams::create() const
 {
-    return new Iris::MMU(this);
+    return new Iris::MMU(*this);
 }

src/arch/arm/fastmodel/iris/mmu.hh

@@ -48,7 +48,7 @@ namespace Iris
 class MMU : public BaseMMU
 {
   public:
-    MMU(const Params *p) : BaseMMU(p) {}
+    MMU(const Params &p) : BaseMMU(p) {}
 };
 
 } // namespace Iris

src/arch/arm/fastmodel/iris/tlb.cc

@@ -67,7 +67,7 @@ Iris::TLB::translateTiming(const RequestPtr &req, ::ThreadContext *tc,
 }
 
 Iris::TLB *
-IrisTLBParams::create()
+IrisTLBParams::create() const
 {
-    return new Iris::TLB(this);
+    return new Iris::TLB(*this);
 }

src/arch/arm/fastmodel/iris/tlb.hh

@@ -36,7 +36,7 @@ namespace Iris
 class TLB : public BaseTLB
 {
   public:
-    TLB(const Params *p) : BaseTLB(p) {}
+    TLB(const Params &p) : BaseTLB(p) {}
 
     void demapPage(Addr vaddr, uint64_t asn) override {}
     void flushAll() override {}

src/arch/arm/freebsd/fs_workload.cc

@@ -51,10 +51,10 @@ using namespace FreeBSD;
 namespace ArmISA
 {
 
-FsFreebsd::FsFreebsd(Params *p) : ArmISA::FsWorkload(p),
-    enableContextSwitchStatsDump(p->enable_context_switch_stats_dump)
+FsFreebsd::FsFreebsd(const Params &p) : ArmISA::FsWorkload(p),
+    enableContextSwitchStatsDump(p.enable_context_switch_stats_dump)
 {
-    if (p->panic_on_panic) {
+    if (p.panic_on_panic) {
         kernelPanic = addKernelFuncEventOrPanic<PanicPCEvent>(
             "panic", "Kernel panic in simulated kernel");
     } else {
@@ -63,7 +63,7 @@ FsFreebsd::FsFreebsd(Params *p) : ArmISA::FsWorkload(p),
 #endif
     }
 
-    if (p->panic_on_oops) {
+    if (p.panic_on_oops) {
         kernelOops = addKernelFuncEventOrPanic<PanicPCEvent>(
             "oops_exit", "Kernel oops in guest");
     }
@@ -80,7 +80,7 @@ FsFreebsd::initState()
     // Load symbols at physical address, we might not want
     // to do this permanently, for but early bootup work
     // it is helpful.
-    if (params()->early_kernel_symbols) {
+    if (params().early_kernel_symbols) {
         auto phys_globals = kernelObj->symtab().globals()->mask(_loadAddrMask);
         kernelSymtab.insert(*phys_globals);
         Loader::debugSymbolTable.insert(*phys_globals);
@@ -90,33 +90,33 @@ FsFreebsd::initState()
     // device trees.
     fatal_if(kernelSymtab.find("fdt_get_range") == kernelSymtab.end(),
              "Kernel must have fdt support.");
-    fatal_if(params()->dtb_filename == "", "dtb file is not specified.");
+    fatal_if(params().dtb_filename == "", "dtb file is not specified.");
 
     // Kernel supports flattened device tree and dtb file specified.
     // Using Device Tree Blob to describe system configuration.
-    inform("Loading DTB file: %s at address %#x\n", params()->dtb_filename,
-            params()->atags_addr + _loadAddrOffset);
+    inform("Loading DTB file: %s at address %#x\n", params().dtb_filename,
+            params().atags_addr + _loadAddrOffset);
 
-    auto *dtb_file = new ::Loader::DtbFile(params()->dtb_filename);
+    auto *dtb_file = new ::Loader::DtbFile(params().dtb_filename);
 
     warn_if(!dtb_file->addBootCmdLine(commandLine.c_str(), commandLine.size()),
             "Couldn't append bootargs to DTB file: %s",
-            params()->dtb_filename);
+            params().dtb_filename);
 
     Addr ra = dtb_file->findReleaseAddr();
     if (ra)
         bootReleaseAddr = ra & ~ULL(0x7F);
 
     dtb_file->buildImage().
-        offset(params()->atags_addr + _loadAddrOffset).
+        offset(params().atags_addr + _loadAddrOffset).
         write(system->physProxy);
     delete dtb_file;
 
     // Kernel boot requirements to set up r0, r1 and r2 in ARMv7
     for (auto *tc: system->threads) {
         tc->setIntReg(0, 0);
-        tc->setIntReg(1, params()->machine_type);
-        tc->setIntReg(2, params()->atags_addr + _loadAddrOffset);
+        tc->setIntReg(1, params().machine_type);
+        tc->setIntReg(2, params().atags_addr + _loadAddrOffset);
     }
 }
 
@@ -128,7 +128,7 @@ FsFreebsd::~FsFreebsd()
 } // namespace ArmISA
 
 ArmISA::FsFreebsd *
-ArmFsFreebsdParams::create()
+ArmFsFreebsdParams::create() const
 {
-    return new ArmISA::FsFreebsd(this);
+    return new ArmISA::FsFreebsd(*this);
 }

src/arch/arm/freebsd/fs_workload.hh

@@ -47,10 +47,10 @@ class FsFreebsd : public ArmISA::FsWorkload
   public:
     /** Boilerplate params code */
     typedef ArmFsFreebsdParams Params;
-    const Params *
+    const Params &
     params() const
     {
-        return dynamic_cast<const Params *>(&_params);
+        return dynamic_cast<const Params &>(_params);
     }
 
     /** When enabled, dump stats/task info on context switches for
@@ -67,7 +67,7 @@ class FsFreebsd : public ArmISA::FsWorkload
      * mappings between taskIds and OS process IDs */
     std::ostream* taskFile;
 
-    FsFreebsd(Params *p);
+    FsFreebsd(const Params &p);
     ~FsFreebsd();
 
     void initState() override;

src/arch/arm/freebsd/process.cc

@@ -62,7 +62,7 @@ class ArmFreebsdObjectFileLoader : public Process::Loader
 {
   public:
     Process *
-    load(ProcessParams *params, ::Loader::ObjectFile *obj_file) override
+    load(const ProcessParams &params, ::Loader::ObjectFile *obj_file) override
     {
         auto arch = obj_file->getArch();
         auto opsys = obj_file->getOpSys();
@@ -150,12 +150,12 @@ static SyscallDescTable<ArmFreebsdProcess64::SyscallABI> syscallDescs64 = {
     {  477, "mmap", mmapFunc<ArmFreebsd64> }
 };
 
-ArmFreebsdProcess32::ArmFreebsdProcess32(ProcessParams * params,
+ArmFreebsdProcess32::ArmFreebsdProcess32(const ProcessParams &params,
         ::Loader::ObjectFile *objFile, ::Loader::Arch _arch) :
     ArmProcess32(params, objFile, _arch)
 {}
 
-ArmFreebsdProcess64::ArmFreebsdProcess64(ProcessParams * params,
+ArmFreebsdProcess64::ArmFreebsdProcess64(const ProcessParams &params,
         ::Loader::ObjectFile *objFile, ::Loader::Arch _arch) :
     ArmProcess64(params, objFile, _arch)
 {}

src/arch/arm/freebsd/process.hh

@@ -77,8 +77,8 @@ struct Result<ABI, SyscallReturn,
 class ArmFreebsdProcess32 : public ArmProcess32, public ArmFreebsdProcessBits
 {
   public:
-    ArmFreebsdProcess32(ProcessParams * params, ::Loader::ObjectFile *objFile,
-                        ::Loader::Arch _arch);
+    ArmFreebsdProcess32(const ProcessParams &params,
+                        ::Loader::ObjectFile *objFile, ::Loader::Arch _arch);
 
     void initState() override;
 
@@ -96,8 +96,8 @@ class ArmFreebsdProcess32 : public ArmProcess32, public ArmFreebsdProcessBits
 class ArmFreebsdProcess64 : public ArmProcess64, public ArmFreebsdProcessBits
 {
   public:
-    ArmFreebsdProcess64(ProcessParams * params, ::Loader::ObjectFile *objFile,
-                        ::Loader::Arch _arch);
+    ArmFreebsdProcess64(const ProcessParams &params,
+                        ::Loader::ObjectFile *objFile, ::Loader::Arch _arch);
 
     void initState() override;
     void syscall(ThreadContext *tc) override;

src/arch/arm/fs_workload.cc

@@ -69,15 +69,15 @@ SkipFunc::returnFromFuncIn(ThreadContext *tc)
     }
 }
 
-FsWorkload::FsWorkload(Params *p) : KernelWorkload(*p)
+FsWorkload::FsWorkload(const Params &p) : KernelWorkload(p)
 {
     if (kernelObj) {
         kernelEntry = (kernelObj->entryPoint() & loadAddrMask()) +
             loadAddrOffset();
     }
 
-    bootLoaders.reserve(p->boot_loader.size());
-    for (const auto &bl : p->boot_loader) {
+    bootLoaders.reserve(p.boot_loader.size());
+    for (const auto &bl : p.boot_loader) {
         std::unique_ptr<Loader::ObjectFile> bl_obj;
         bl_obj.reset(Loader::createObjectFile(bl));
 
@@ -120,18 +120,18 @@ FsWorkload::initState()
         // Put the address of the boot loader into r7 so we know
         // where to branch to after the reset fault
         // All other values needed by the boot loader to know what to do
-        fatal_if(!arm_sys->params()->flags_addr,
+        fatal_if(!arm_sys->params().flags_addr,
                  "flags_addr must be set with bootloader");
 
-        fatal_if(!arm_sys->params()->gic_cpu_addr && is_gic_v2,
+        fatal_if(!arm_sys->params().gic_cpu_addr && is_gic_v2,
                  "gic_cpu_addr must be set with bootloader");
 
         for (auto *tc: arm_sys->threads) {
             if (!arm_sys->highestELIs64())
                 tc->setIntReg(3, kernelEntry);
             if (is_gic_v2)
-                tc->setIntReg(4, arm_sys->params()->gic_cpu_addr);
-            tc->setIntReg(5, arm_sys->params()->flags_addr);
+                tc->setIntReg(4, arm_sys->params().gic_cpu_addr);
+            tc->setIntReg(5, arm_sys->params().flags_addr);
         }
         inform("Using kernel entry physical address at %#x\n", kernelEntry);
     } else {
@@ -159,7 +159,7 @@ FsWorkload::getBootLoader(Loader::ObjectFile *const obj)
 } // namespace ArmISA
 
 ArmISA::FsWorkload *
-ArmFsWorkloadParams::create()
+ArmFsWorkloadParams::create() const
 {
-    return new ArmISA::FsWorkload(this);
+    return new ArmISA::FsWorkload(*this);
 }

src/arch/arm/fs_workload.hh

@@ -88,10 +88,10 @@ class FsWorkload : public KernelWorkload
 
   public:
     typedef ArmFsWorkloadParams Params;
-    const Params *
+    const Params &
     params() const
     {
-        return dynamic_cast<const Params *>(&_params);
+        return dynamic_cast<const Params &>(_params);
     }
 
     Addr
@@ -114,7 +114,7 @@ class FsWorkload : public KernelWorkload
             return Loader::Arm64;
     }
 
-    FsWorkload(Params *p);
+    FsWorkload(const Params &p);
 
     void initState() override;
 

src/arch/arm/interrupts.cc

@@ -40,9 +40,9 @@
 #include "arch/arm/system.hh"
 
 ArmISA::Interrupts *
-ArmInterruptsParams::create()
+ArmInterruptsParams::create() const
 {
-    return new ArmISA::Interrupts(this);
+    return new ArmISA::Interrupts(*this);
 }
 
 bool

src/arch/arm/interrupts.hh

@@ -76,13 +76,13 @@ class Interrupts : public BaseInterrupts
 
     typedef ArmInterruptsParams Params;
 
-    const Params *
+    const Params &
     params() const
     {
-        return dynamic_cast<const Params *>(_params);
+        return dynamic_cast<const Params &>(_params);
     }
 
-    Interrupts(Params * p) : BaseInterrupts(p)
+    Interrupts(const Params &p) : BaseInterrupts(p)
     {
         clearAll();
     }

src/arch/arm/isa.cc

@@ -60,9 +60,9 @@
 namespace ArmISA
 {
 
-ISA::ISA(Params *p) : BaseISA(p), system(NULL),
-    _decoderFlavor(p->decoderFlavor), _vecRegRenameMode(Enums::Full),
-    pmu(p->pmu), impdefAsNop(p->impdef_nop),
+ISA::ISA(const Params &p) : BaseISA(p), system(NULL),
+    _decoderFlavor(p.decoderFlavor), _vecRegRenameMode(Enums::Full),
+    pmu(p.pmu), impdefAsNop(p.impdef_nop),
     afterStartup(false)
 {
     miscRegs[MISCREG_SCTLR_RST] = 0;
@@ -76,7 +76,7 @@ ISA::ISA(Params *p) : BaseISA(p), system(NULL),
     // Give all ISA devices a pointer to this ISA
     pmu->setISA(this);
 
-    system = dynamic_cast<ArmSystem *>(p->system);
+    system = dynamic_cast<ArmSystem *>(p.system);
 
     // Cache system-level properties
     if (FullSystem && system) {
@@ -102,7 +102,7 @@ ISA::ISA(Params *p) : BaseISA(p), system(NULL),
         haveSVE = true;
         havePAN = false;
         haveSecEL2 = true;
-        sveVL = p->sve_vl_se;
+        sveVL = p.sve_vl_se;
         haveLSE = true;
         haveTME = true;
     }
@@ -120,16 +120,16 @@ ISA::ISA(Params *p) : BaseISA(p), system(NULL),
 
 std::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS);
 
-const ArmISAParams *
+const ArmISAParams &
 ISA::params() const
 {
-    return dynamic_cast<const Params *>(_params);
+    return dynamic_cast<const Params &>(_params);
 }
 
 void
 ISA::clear()
 {
-    const Params *p(params());
+    const Params &p(params());
 
     // Invalidate cached copies of miscregs in the TLBs
     if (tc) {
@@ -220,7 +220,7 @@ ISA::clear()
 }
 
 void
-ISA::clear32(const ArmISAParams *p, const SCTLR &sctlr_rst)
+ISA::clear32(const ArmISAParams &p, const SCTLR &sctlr_rst)
 {
     CPSR cpsr = 0;
     cpsr.mode = MODE_USER;
@@ -249,7 +249,7 @@ ISA::clear32(const ArmISAParams *p, const SCTLR &sctlr_rst)
 
     miscRegs[MISCREG_CPACR] = 0;
 
-    miscRegs[MISCREG_FPSID] = p->fpsid;
+    miscRegs[MISCREG_FPSID] = p.fpsid;
 
     if (haveLPAE) {
         TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS];
@@ -272,7 +272,7 @@ ISA::clear32(const ArmISAParams *p, const SCTLR &sctlr_rst)
 }
 
 void
-ISA::clear64(const ArmISAParams *p)
+ISA::clear64(const ArmISAParams &p)
 {
     CPSR cpsr = 0;
     Addr rvbar = system->resetAddr();
@@ -321,13 +321,13 @@ ISA::clear64(const ArmISAParams *p)
 }
 
 void
-ISA::initID32(const ArmISAParams *p)
+ISA::initID32(const ArmISAParams &p)
 {
     // Initialize configurable default values
 
     uint32_t midr;
-    if (p->midr != 0x0)
-        midr = p->midr;
+    if (p.midr != 0x0)
+        midr = p.midr;
     else if (highestELIs64)
         // Cortex-A57 TRM r0p0 MIDR
         midr = 0x410fd070;
@@ -339,17 +339,17 @@ ISA::initID32(const ArmISAParams *p)
     miscRegs[MISCREG_MIDR_EL1] = midr;
     miscRegs[MISCREG_VPIDR] = midr;
 
-    miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
-    miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
-    miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
-    miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
-    miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
-    miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
+    miscRegs[MISCREG_ID_ISAR0] = p.id_isar0;
+    miscRegs[MISCREG_ID_ISAR1] = p.id_isar1;
+    miscRegs[MISCREG_ID_ISAR2] = p.id_isar2;
+    miscRegs[MISCREG_ID_ISAR3] = p.id_isar3;
+    miscRegs[MISCREG_ID_ISAR4] = p.id_isar4;
+    miscRegs[MISCREG_ID_ISAR5] = p.id_isar5;
 
-    miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
-    miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
-    miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
-    miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
+    miscRegs[MISCREG_ID_MMFR0] = p.id_mmfr0;
+    miscRegs[MISCREG_ID_MMFR1] = p.id_mmfr1;
+    miscRegs[MISCREG_ID_MMFR2] = p.id_mmfr2;
+    miscRegs[MISCREG_ID_MMFR3] = p.id_mmfr3;
 
     miscRegs[MISCREG_ID_ISAR5] = insertBits(
         miscRegs[MISCREG_ID_ISAR5], 19, 4,
@@ -357,24 +357,24 @@ ISA::initID32(const ArmISAParams *p)
 }
 
 void
-ISA::initID64(const ArmISAParams *p)
+ISA::initID64(const ArmISAParams &p)
 {
     // Initialize configurable id registers
-    miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1;
-    miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1;
+    miscRegs[MISCREG_ID_AA64AFR0_EL1] = p.id_aa64afr0_el1;
+    miscRegs[MISCREG_ID_AA64AFR1_EL1] = p.id_aa64afr1_el1;
     miscRegs[MISCREG_ID_AA64DFR0_EL1] =
-        (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) |
-        (p->pmu ?             0x0000000000000100ULL : 0); // Enable PMUv3
+        (p.id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) |
+        (p.pmu ?             0x0000000000000100ULL : 0); // Enable PMUv3
 
-    miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1;
-    miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1;
-    miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1;
-    miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1;
-    miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1;
-    miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p->id_aa64mmfr2_el1;
+    miscRegs[MISCREG_ID_AA64DFR1_EL1] = p.id_aa64dfr1_el1;
+    miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p.id_aa64isar0_el1;
+    miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p.id_aa64isar1_el1;
+    miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p.id_aa64mmfr0_el1;
+    miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p.id_aa64mmfr1_el1;
+    miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p.id_aa64mmfr2_el1;
 
     miscRegs[MISCREG_ID_DFR0_EL1] =
-        (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3
+        (p.pmu ? 0x03000000ULL : 0); // Enable PMUv3
 
     miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1];
 
@@ -2481,7 +2481,7 @@ ISA::MiscRegLUTEntryInitializer::highest(ArmSystem *const sys) const
 }  // namespace ArmISA
 
 ArmISA::ISA *
-ArmISAParams::create()
+ArmISAParams::create() const
 {
-    return new ArmISA::ISA(this);
+    return new ArmISA::ISA(*this);
 }

src/arch/arm/isa.hh

@@ -461,10 +461,10 @@ namespace ArmISA
         void clear();
 
       protected:
-        void clear32(const ArmISAParams *p, const SCTLR &sctlr_rst);
-        void clear64(const ArmISAParams *p);
-        void initID32(const ArmISAParams *p);
-        void initID64(const ArmISAParams *p);
+        void clear32(const ArmISAParams &p, const SCTLR &sctlr_rst);
+        void clear64(const ArmISAParams &p);
+        void initID32(const ArmISAParams &p);
+        void initID64(const ArmISAParams &p);
 
         void addressTranslation(TLB::ArmTranslationType tran_type,
             BaseTLB::Mode mode, Request::Flags flags, RegVal val);
@@ -853,9 +853,9 @@ namespace ArmISA
 
         typedef ArmISAParams Params;
 
-        const Params *params() const;
+        const Params &params() const;
 
-        ISA(Params *p);
+        ISA(const Params &p);
     };
 }
 

src/arch/arm/kvm/arm_cpu.cc

@@ -241,7 +241,7 @@ ArmKvmCPU::KvmCoreMiscRegInfo ArmKvmCPU::kvmCoreMiscRegs[] = {
     { 0, NUM_MISCREGS }
 };
 
-ArmKvmCPU::ArmKvmCPU(ArmKvmCPUParams *params)
+ArmKvmCPU::ArmKvmCPU(const ArmKvmCPUParams &params)
     : BaseKvmCPU(params),
       irqAsserted(false), fiqAsserted(false)
 {
@@ -843,7 +843,7 @@ ArmKvmCPU::updateTCStateVFP(uint64_t id, bool show_warnings)
 }
 
 ArmKvmCPU *
-ArmKvmCPUParams::create()
+ArmKvmCPUParams::create() const
 {
-    return new ArmKvmCPU(this);
+    return new ArmKvmCPU(*this);
 }

src/arch/arm/kvm/arm_cpu.hh

@@ -59,7 +59,7 @@
 class ArmKvmCPU : public BaseKvmCPU
 {
   public:
-    ArmKvmCPU(ArmKvmCPUParams *params);
+    ArmKvmCPU(const ArmKvmCPUParams &params);
     virtual ~ArmKvmCPU();
 
     void startup();

src/arch/arm/kvm/armv8_cpu.cc

@@ -123,7 +123,7 @@ const std::vector<ArmV8KvmCPU::MiscRegInfo> ArmV8KvmCPU::miscRegIdMap = {
     MiscRegInfo(SYS_MPIDR_EL1, MISCREG_MPIDR_EL1, "MPIDR(EL1)"),
 };
 
-ArmV8KvmCPU::ArmV8KvmCPU(ArmV8KvmCPUParams *params)
+ArmV8KvmCPU::ArmV8KvmCPU(const ArmV8KvmCPUParams &params)
     : BaseArmKvmCPU(params)
 {
 }
@@ -397,7 +397,7 @@ ArmV8KvmCPU::getSysRegMap() const
 }
 
 ArmV8KvmCPU *
-ArmV8KvmCPUParams::create()
+ArmV8KvmCPUParams::create() const
 {
-    return new ArmV8KvmCPU(this);
+    return new ArmV8KvmCPU(*this);
 }

src/arch/arm/kvm/armv8_cpu.hh

@@ -79,7 +79,7 @@ struct ArmV8KvmCPUParams;
 class ArmV8KvmCPU : public BaseArmKvmCPU
 {
   public:
-    ArmV8KvmCPU(ArmV8KvmCPUParams *params);
+    ArmV8KvmCPU(const ArmV8KvmCPUParams &params);
     virtual ~ArmV8KvmCPU();
 
     void startup() override;

src/arch/arm/kvm/base_cpu.cc

@@ -59,7 +59,7 @@ using namespace ArmISA;
     INTERRUPT_ID(KVM_ARM_IRQ_TYPE_CPU, vcpu, KVM_ARM_IRQ_CPU_FIQ)
 
 
-BaseArmKvmCPU::BaseArmKvmCPU(BaseArmKvmCPUParams *params)
+BaseArmKvmCPU::BaseArmKvmCPU(const BaseArmKvmCPUParams &params)
     : BaseKvmCPU(params),
       irqAsserted(false), fiqAsserted(false),
       virtTimerPin(nullptr), prevDeviceIRQLevel(0)
@@ -90,7 +90,7 @@ BaseArmKvmCPU::startup()
 
     if (!vm.hasKernelIRQChip())
         virtTimerPin = static_cast<ArmSystem *>(system)\
-            ->getGenericTimer()->params()->int_virt->get(tc);
+            ->getGenericTimer()->params().int_virt->get(tc);
 }
 
 Tick

src/arch/arm/kvm/base_cpu.hh

@@ -48,7 +48,7 @@ struct BaseArmKvmCPUParams;
 class BaseArmKvmCPU : public BaseKvmCPU
 {
   public:
-    BaseArmKvmCPU(BaseArmKvmCPUParams *params);
+    BaseArmKvmCPU(const BaseArmKvmCPUParams &params);
     virtual ~BaseArmKvmCPU();
 
     void startup() override;

src/arch/arm/kvm/gic.cc

@@ -164,15 +164,15 @@ KvmKernelGicV2::writeCpu(ContextID ctx, Addr daddr, uint32_t data)
 
 
 
-MuxingKvmGic::MuxingKvmGic(const MuxingKvmGicParams *p)
+MuxingKvmGic::MuxingKvmGic(const MuxingKvmGicParams &p)
     : GicV2(p),
-      system(*p->system),
+      system(*p.system),
       kernelGic(nullptr),
       usingKvm(false)
 {
     if (auto vm = system.getKvmVM()) {
-        kernelGic = new KvmKernelGicV2(*vm, p->cpu_addr, p->dist_addr,
-                                       p->it_lines);
+        kernelGic = new KvmKernelGicV2(*vm, p.cpu_addr, p.dist_addr,
+                                       p.it_lines);
     }
 }
 
@@ -427,7 +427,7 @@ MuxingKvmGic::fromKvmToGicV2()
 }
 
 MuxingKvmGic *
-MuxingKvmGicParams::create()
+MuxingKvmGicParams::create() const
 {
-    return new MuxingKvmGic(this);
+    return new MuxingKvmGic(*this);
 }

src/arch/arm/kvm/gic.hh

@@ -168,7 +168,7 @@ struct MuxingKvmGicParams;
 class MuxingKvmGic : public GicV2
 {
   public: // SimObject / Serializable / Drainable
-    MuxingKvmGic(const MuxingKvmGicParams *p);
+    MuxingKvmGic(const MuxingKvmGicParams &p);
     ~MuxingKvmGic();
 
     void startup() override;

src/arch/arm/linux/fs_workload.cc

@@ -63,8 +63,8 @@ using namespace Linux;
 namespace ArmISA
 {
 
-FsLinux::FsLinux(Params *p) : ArmISA::FsWorkload(p),
-    enableContextSwitchStatsDump(p->enable_context_switch_stats_dump)
+FsLinux::FsLinux(const Params &p) : ArmISA::FsWorkload(p),
+    enableContextSwitchStatsDump(p.enable_context_switch_stats_dump)
 {}
 
 void
@@ -75,7 +75,7 @@ FsLinux::initState()
     // Load symbols at physical address, we might not want
     // to do this permanently, for but early bootup work
     // it is helpful.
-    if (params()->early_kernel_symbols) {
+    if (params().early_kernel_symbols) {
         auto phys_globals = kernelObj->symtab().globals()->mask(_loadAddrMask);
         kernelSymtab.insert(*phys_globals);
         Loader::debugSymbolTable.insert(*phys_globals);
@@ -86,24 +86,24 @@ FsLinux::initState()
     // device trees.
     bool kernel_has_fdt_support =
         kernelSymtab.find("unflatten_device_tree") != kernelSymtab.end();
-    bool dtb_file_specified = params()->dtb_filename != "";
+    bool dtb_file_specified = params().dtb_filename != "";
 
     if (kernel_has_fdt_support && dtb_file_specified) {
         // Kernel supports flattened device tree and dtb file specified.
         // Using Device Tree Blob to describe system configuration.
-        inform("Loading DTB file: %s at address %#x\n", params()->dtb_filename,
-                params()->atags_addr + _loadAddrOffset);
+        inform("Loading DTB file: %s at address %#x\n", params().dtb_filename,
+                params().atags_addr + _loadAddrOffset);
 
-        auto *dtb_file = new ::Loader::DtbFile(params()->dtb_filename);
+        auto *dtb_file = new ::Loader::DtbFile(params().dtb_filename);
 
         if (!dtb_file->addBootCmdLine(
                     commandLine.c_str(), commandLine.size())) {
             warn("couldn't append bootargs to DTB file: %s\n",
-                 params()->dtb_filename);
+                 params().dtb_filename);
         }
 
         dtb_file->buildImage().
-            offset(params()->atags_addr + _loadAddrOffset).
+            offset(params().atags_addr + _loadAddrOffset).
             write(system->physProxy);
         delete dtb_file;
     } else {
@@ -152,7 +152,7 @@ FsLinux::initState()
         DPRINTF(Loader, "Boot atags was %d bytes in total\n", size << 2);
         DDUMP(Loader, boot_data, size << 2);
 
-        system->physProxy.writeBlob(params()->atags_addr + _loadAddrOffset,
+        system->physProxy.writeBlob(params().atags_addr + _loadAddrOffset,
                                     boot_data, size << 2);
 
         delete[] boot_data;
@@ -161,8 +161,8 @@ FsLinux::initState()
     // Kernel boot requirements to set up r0, r1 and r2 in ARMv7
     for (auto *tc: system->threads) {
         tc->setIntReg(0, 0);
-        tc->setIntReg(1, params()->machine_type);
-        tc->setIntReg(2, params()->atags_addr + _loadAddrOffset);
+        tc->setIntReg(1, params().machine_type);
+        tc->setIntReg(2, params().atags_addr + _loadAddrOffset);
     }
 }
 
@@ -203,7 +203,7 @@ FsLinux::startup()
     }
 
     const std::string dmesg_output = name() + ".dmesg";
-    if (params()->panic_on_panic) {
+    if (params().panic_on_panic) {
         kernelPanic = addKernelFuncEventOrPanic<Linux::KernelPanic>(
             "panic", "Kernel panic in simulated kernel", dmesg_output);
     } else {
@@ -211,7 +211,7 @@ FsLinux::startup()
             "panic", "Kernel panic in simulated kernel", dmesg_output);
     }
 
-    if (params()->panic_on_oops) {
+    if (params().panic_on_oops) {
         kernelOops = addKernelFuncEventOrPanic<Linux::KernelPanic>(
             "oops_exit", "Kernel oops in guest", dmesg_output);
     } else {
@@ -360,7 +360,7 @@ DumpStats::process(ThreadContext *tc)
 } // namespace ArmISA
 
 ArmISA::FsLinux *
-ArmFsLinuxParams::create()
+ArmFsLinuxParams::create() const
 {
-    return new ArmISA::FsLinux(this);
+    return new ArmISA::FsLinux(*this);
 }

src/arch/arm/linux/fs_workload.hh

@@ -85,10 +85,10 @@ class FsLinux : public ArmISA::FsWorkload
   public:
     /** Boilerplate params code */
     typedef ArmFsLinuxParams Params;
-    const Params *
+    const Params &
     params() const
     {
-        return dynamic_cast<const Params *>(&_params);
+        return dynamic_cast<const Params &>(_params);
     }
 
     /** When enabled, dump stats/task info on context switches for
@@ -105,7 +105,7 @@ class FsLinux : public ArmISA::FsWorkload
      * mappings between taskIds and OS process IDs */
     OutputStream *taskFile = nullptr;
 
-    FsLinux(Params *p);
+    FsLinux(const Params &p);
     ~FsLinux();
 
     void initState() override;

src/arch/arm/linux/process.cc

@@ -64,7 +64,7 @@ class ArmLinuxObjectFileLoader : public Process::Loader
 {
   public:
     Process *
-    load(ProcessParams *params, ::Loader::ObjectFile *obj_file) override
+    load(const ProcessParams &params, ::Loader::ObjectFile *obj_file) override
     {
         auto arch = obj_file->getArch();
         auto opsys = obj_file->getOpSys();
@@ -845,12 +845,12 @@ static SyscallDescTable<ArmLinuxProcess64::SyscallABI> privSyscallDescs64 = {
     { 0x1005, "set_tls", setTLSFunc64 }
 };
 
-ArmLinuxProcess32::ArmLinuxProcess32(ProcessParams * params,
+ArmLinuxProcess32::ArmLinuxProcess32(const ProcessParams &params,
         ::Loader::ObjectFile *objFile, ::Loader::Arch _arch) :
     ArmProcess32(params, objFile, _arch)
 {}
 
-ArmLinuxProcess64::ArmLinuxProcess64(ProcessParams * params,
+ArmLinuxProcess64::ArmLinuxProcess64(const ProcessParams &params,
         ::Loader::ObjectFile *objFile, ::Loader::Arch _arch) :
     ArmProcess64(params, objFile, _arch)
 {}

src/arch/arm/linux/process.hh

@@ -77,8 +77,8 @@ struct Result<ABI, SyscallReturn,
 class ArmLinuxProcess32 : public ArmProcess32, public ArmLinuxProcessBits
 {
   public:
-    ArmLinuxProcess32(ProcessParams * params, ::Loader::ObjectFile *objFile,
-                      ::Loader::Arch _arch);
+    ArmLinuxProcess32(const ProcessParams &params,
+                      ::Loader::ObjectFile *objFile, ::Loader::Arch _arch);
 
     void initState() override;
 
@@ -96,8 +96,8 @@ class ArmLinuxProcess32 : public ArmProcess32, public ArmLinuxProcessBits
 class ArmLinuxProcess64 : public ArmProcess64, public ArmLinuxProcessBits
 {
   public:
-    ArmLinuxProcess64(ProcessParams * params, ::Loader::ObjectFile *objFile,
-                      ::Loader::Arch _arch);
+    ArmLinuxProcess64(const ProcessParams &params,
+                      ::Loader::ObjectFile *objFile, ::Loader::Arch _arch);
 
     void initState() override;
     void syscall(ThreadContext *tc) override;

src/arch/arm/mmu.cc

@@ -38,7 +38,7 @@
 #include "arch/arm/mmu.hh"
 
 ArmISA::MMU *
-ArmMMUParams::create()
+ArmMMUParams::create() const
 {
-    return new ArmISA::MMU(this);
+    return new ArmISA::MMU(*this);
 }

src/arch/arm/mmu.hh

@@ -47,7 +47,7 @@ namespace ArmISA {
 class MMU : public BaseMMU
 {
   public:
-    MMU(const ArmMMUParams *p)
+    MMU(const ArmMMUParams &p)
       : BaseMMU(p)
     {}
 };

src/arch/arm/nativetrace.cc

@@ -225,7 +225,7 @@ Trace::ArmNativeTrace::check(NativeTraceRecord *record)
 //  ExeTracer Simulation Object
 //
 Trace::ArmNativeTrace *
-ArmNativeTraceParams::create()
+ArmNativeTraceParams::create() const
 {
-    return new Trace::ArmNativeTrace(this);
+    return new Trace::ArmNativeTrace(*this);
 }

src/arch/arm/nativetrace.hh

@@ -98,14 +98,14 @@ class ArmNativeTrace : public NativeTrace
   public:
     typedef ArmNativeTraceParams Params;
 
-    const Params *
+    const Params &
     params() const
     {
-        return dynamic_cast<const Params *>(_params);
+        return dynamic_cast<const Params &>(_params);
     }
 
-    ArmNativeTrace(const Params *p) :
-        NativeTrace(p), stopOnPCError(p->stop_on_pc_error)
+    ArmNativeTrace(const Params &p) :
+        NativeTrace(p), stopOnPCError(p.stop_on_pc_error)
     {}
 
     void check(NativeTraceRecord *record);

src/arch/arm/pmu.cc

@@ -51,15 +51,15 @@ namespace ArmISA {
 
 const RegVal PMU::reg_pmcr_wr_mask = 0x39;
 
-PMU::PMU(const ArmPMUParams *p)
+PMU::PMU(const ArmPMUParams &p)
     : SimObject(p), BaseISADevice(),
       reg_pmcnten(0), reg_pmcr(0),
       reg_pmselr(0), reg_pminten(0), reg_pmovsr(0),
       reg_pmceid0(0),reg_pmceid1(0),
       clock_remainder(0),
-      maximumCounterCount(p->eventCounters),
+      maximumCounterCount(p.eventCounters),
       cycleCounter(*this, maximumCounterCount),
-      cycleCounterEventId(p->cycleEventId),
+      cycleCounterEventId(p.cycleEventId),
       swIncrementEvent(nullptr),
       reg_pmcr_conf(0),
       interrupt(nullptr)
@@ -71,13 +71,13 @@ PMU::PMU(const ArmPMUParams *p)
               maximumCounterCount);
     }
 
-    warn_if(!p->interrupt, "ARM PMU: No interrupt specified, interrupt " \
+    warn_if(!p.interrupt, "ARM PMU: No interrupt specified, interrupt " \
             "delivery disabled.\n");
 
     /* Setup the performance counter ID registers */
     reg_pmcr_conf.imp = 0x41;    // ARM Ltd.
     reg_pmcr_conf.idcode = 0x00;
-    reg_pmcr_conf.n = p->eventCounters;
+    reg_pmcr_conf.n = p.eventCounters;
 
     // Setup the hard-coded cycle counter, which is equivalent to
     // architected counter event type 0x11.
@@ -92,10 +92,10 @@ void
 PMU::setThreadContext(ThreadContext *tc)
 {
     DPRINTF(PMUVerbose, "Assigning PMU to ContextID %i.\n", tc->contextId());
-    auto pmu_params = static_cast<const ArmPMUParams *>(params());
+    const auto &pmu_params = static_cast<const ArmPMUParams &>(params());
 
-    if (pmu_params->interrupt)
-        interrupt = pmu_params->interrupt->get(tc);
+    if (pmu_params.interrupt)
+        interrupt = pmu_params.interrupt->get(tc);
 }
 
 void
@@ -809,7 +809,7 @@ PMU::SWIncrementEvent::write(uint64_t val)
 } // namespace ArmISA
 
 ArmISA::PMU *
-ArmPMUParams::create()
+ArmPMUParams::create() const
 {
-    return new ArmISA::PMU(this);
+    return new ArmISA::PMU(*this);
 }

src/arch/arm/pmu.hh

@@ -93,7 +93,7 @@ namespace ArmISA {
  */
 class PMU : public SimObject, public ArmISA::BaseISADevice {
   public:
-    PMU(const ArmPMUParams *p);
+    PMU(const ArmPMUParams &p);
     ~PMU();
 
     void addEventProbe(unsigned int id, SimObject *obj, const char *name);

src/arch/arm/process.cc

@@ -58,17 +58,17 @@
 using namespace std;
 using namespace ArmISA;
 
-ArmProcess::ArmProcess(ProcessParams *params, ::Loader::ObjectFile *objFile,
-                       ::Loader::Arch _arch)
+ArmProcess::ArmProcess(const ProcessParams &params,
+                       ::Loader::ObjectFile *objFile, ::Loader::Arch _arch)
     : Process(params,
-              new EmulationPageTable(params->name, params->pid, PageBytes),
+              new EmulationPageTable(params.name, params.pid, PageBytes),
               objFile),
       arch(_arch)
 {
-    fatal_if(params->useArchPT, "Arch page tables not implemented.");
+    fatal_if(params.useArchPT, "Arch page tables not implemented.");
 }
 
-ArmProcess32::ArmProcess32(ProcessParams *params,
+ArmProcess32::ArmProcess32(const ProcessParams &params,
         ::Loader::ObjectFile *objFile, ::Loader::Arch _arch)
     : ArmProcess(params, objFile, _arch)
 {
@@ -84,7 +84,7 @@ ArmProcess32::ArmProcess32(ProcessParams *params,
 }
 
 ArmProcess64::ArmProcess64(
-        ProcessParams *params, ::Loader::ObjectFile *objFile,
+        const ProcessParams &params, ::Loader::ObjectFile *objFile,
         ::Loader::Arch _arch)
     : ArmProcess(params, objFile, _arch)
 {

src/arch/arm/process.hh

@@ -54,7 +54,7 @@ class ArmProcess : public Process
 {
   protected:
     ::Loader::Arch arch;
-    ArmProcess(ProcessParams * params, ::Loader::ObjectFile *objFile,
+    ArmProcess(const ProcessParams &params, ::Loader::ObjectFile *objFile,
                ::Loader::Arch _arch);
     template<class IntType>
     void argsInit(int pageSize, ArmISA::IntRegIndex spIndex);
@@ -74,7 +74,7 @@ class ArmProcess : public Process
 class ArmProcess32 : public ArmProcess
 {
   protected:
-    ArmProcess32(ProcessParams * params, ::Loader::ObjectFile *objFile,
+    ArmProcess32(const ProcessParams &params, ::Loader::ObjectFile *objFile,
                  ::Loader::Arch _arch);
 
     void initState() override;
@@ -117,7 +117,7 @@ struct Argument<ABI, Arg,
 class ArmProcess64 : public ArmProcess
 {
   protected:
-    ArmProcess64(ProcessParams * params, ::Loader::ObjectFile *objFile,
+    ArmProcess64(const ProcessParams &params, ::Loader::ObjectFile *objFile,
                  ::Loader::Arch _arch);
 
     void initState() override;

src/arch/arm/semihosting.cc

@@ -138,21 +138,21 @@ const std::map<const std::string, FILE *> ArmSemihosting::stdioMap{
     {"stderr", ::stderr},
 };
 
-ArmSemihosting::ArmSemihosting(const ArmSemihostingParams *p)
+ArmSemihosting::ArmSemihosting(const ArmSemihostingParams &p)
     : SimObject(p),
-      cmdLine(p->cmd_line),
-      memReserve(p->mem_reserve),
-      stackSize(p->stack_size),
-      timeBase([p]{ struct tm t = p->time; return mkutctime(&t); }()),
+      cmdLine(p.cmd_line),
+      memReserve(p.mem_reserve),
+      stackSize(p.stack_size),
+      timeBase([p]{ struct tm t = p.time; return mkutctime(&t); }()),
       tickShift(calcTickShift()),
       semiErrno(0),
-      filesRootDir(!p->files_root_dir.empty() &&
-                   p->files_root_dir.back() != '/' ?
-                   p->files_root_dir + '/' : p->files_root_dir),
-      stdin(getSTDIO("stdin", p->stdin, "r")),
-      stdout(getSTDIO("stdout", p->stdout, "w")),
-      stderr(p->stderr == p->stdout ?
-             stdout : getSTDIO("stderr", p->stderr, "w"))
+      filesRootDir(!p.files_root_dir.empty() &&
+                   p.files_root_dir.back() != '/' ?
+                   p.files_root_dir + '/' : p.files_root_dir),
+      stdin(getSTDIO("stdin", p.stdin, "r")),
+      stdout(getSTDIO("stdout", p.stdout, "w")),
+      stderr(p.stderr == p.stdout ?
+             stdout : getSTDIO("stderr", p.stderr, "w"))
 {
     // Create an empty place-holder file for position 0 as semi-hosting
     // calls typically expect non-zero file handles.
@@ -1046,7 +1046,7 @@ operator << (std::ostream &os, const ArmSemihosting::InPlaceArg &ipa)
 
 
 ArmSemihosting *
-ArmSemihostingParams::create()
+ArmSemihostingParams::create() const
 {
-    return new ArmSemihosting(this);
+    return new ArmSemihosting(*this);
 }

src/arch/arm/semihosting.hh

@@ -224,7 +224,7 @@ class ArmSemihosting : public SimObject
         SYS_GEM5_PSEUDO_OP = 0x100
     };
 
-    ArmSemihosting(const ArmSemihostingParams *p);
+    ArmSemihosting(const ArmSemihostingParams &p);
 
     /** Perform an Arm Semihosting call from aarch64 code. */
     bool call64(ThreadContext *tc, bool gem5_ops);

src/arch/arm/stage2_mmu.cc

@@ -46,10 +46,10 @@
 
 using namespace ArmISA;
 
-Stage2MMU::Stage2MMU(const Params *p)
-    : SimObject(p), _stage1Tlb(p->tlb), _stage2Tlb(p->stage2_tlb),
-      port(_stage1Tlb->getTableWalker(), p->sys),
-      requestorId(p->sys->getRequestorId(_stage1Tlb->getTableWalker()))
+Stage2MMU::Stage2MMU(const Params &p)
+    : SimObject(p), _stage1Tlb(p.tlb), _stage2Tlb(p.stage2_tlb),
+      port(_stage1Tlb->getTableWalker(), p.sys),
+      requestorId(p.sys->getRequestorId(_stage1Tlb->getTableWalker()))
 {
     // we use the stage-one table walker as the parent of the port,
     // and to get our requestor id, this is done to keep things
@@ -142,7 +142,7 @@ Stage2MMU::Stage2Translation::finish(const Fault &_fault,
 }
 
 ArmISA::Stage2MMU *
-ArmStage2MMUParams::create()
+ArmStage2MMUParams::create() const
 {
-    return new ArmISA::Stage2MMU(this);
+    return new ArmISA::Stage2MMU(*this);
 }

src/arch/arm/stage2_mmu.hh

@@ -102,7 +102,7 @@ class Stage2MMU : public SimObject
     };
 
     typedef ArmStage2MMUParams Params;
-    Stage2MMU(const Params *p);
+    Stage2MMU(const Params &p);
 
     /**
      * Get the port that ultimately belongs to the stage-two MMU, but

src/arch/arm/system.cc

@@ -55,31 +55,31 @@ using namespace std;
 using namespace Linux;
 using namespace ArmISA;
 
-ArmSystem::ArmSystem(Params *p)
+ArmSystem::ArmSystem(const Params &p)
     : System(p),
-      _haveSecurity(p->have_security),
-      _haveLPAE(p->have_lpae),
-      _haveVirtualization(p->have_virtualization),
-      _haveCrypto(p->have_crypto),
+      _haveSecurity(p.have_security),
+      _haveLPAE(p.have_lpae),
+      _haveVirtualization(p.have_virtualization),
+      _haveCrypto(p.have_crypto),
       _genericTimer(nullptr),
       _gic(nullptr),
       _pwrCtrl(nullptr),
-      _highestELIs64(p->highest_el_is_64),
-      _physAddrRange64(p->phys_addr_range_64),
-      _haveLargeAsid64(p->have_large_asid_64),
-      _haveTME(p->have_tme),
-      _haveSVE(p->have_sve),
-      _sveVL(p->sve_vl),
-      _haveLSE(p->have_lse),
-      _havePAN(p->have_pan),
-      _haveSecEL2(p->have_secel2),
-      semihosting(p->semihosting),
-      multiProc(p->multi_proc)
+      _highestELIs64(p.highest_el_is_64),
+      _physAddrRange64(p.phys_addr_range_64),
+      _haveLargeAsid64(p.have_large_asid_64),
+      _haveTME(p.have_tme),
+      _haveSVE(p.have_sve),
+      _sveVL(p.sve_vl),
+      _haveLSE(p.have_lse),
+      _havePAN(p.have_pan),
+      _haveSecEL2(p.have_secel2),
+      semihosting(p.semihosting),
+      multiProc(p.multi_proc)
 {
-    if (p->auto_reset_addr) {
+    if (p.auto_reset_addr) {
         _resetAddr = workload->getEntry();
     } else {
-        _resetAddr = p->reset_addr;
+        _resetAddr = p.reset_addr;
         warn_if(workload->getEntry() != _resetAddr,
                 "Workload entry point %#x and reset address %#x are different",
                 workload->getEntry(), _resetAddr);
@@ -236,7 +236,7 @@ ArmSystem::callClearWakeRequest(ThreadContext *tc)
 }
 
 ArmSystem *
-ArmSystemParams::create()
+ArmSystemParams::create() const
 {
-    return new ArmSystem(this);
+    return new ArmSystem(*this);
 }

src/arch/arm/system.hh

@@ -146,13 +146,13 @@ class ArmSystem : public System
     static constexpr Addr PageShift = ArmISA::PageShift;
 
     typedef ArmSystemParams Params;
-    const Params *
+    const Params &
     params() const
     {
-        return dynamic_cast<const Params *>(_params);
+        return dynamic_cast<const Params &>(_params);
     }
 
-    ArmSystem(Params *p);
+    ArmSystem(const Params &p);
 
     /** true if this a multiprocessor system */
     bool multiProc;

src/arch/arm/table_walker.cc

@@ -53,12 +53,12 @@
 
 using namespace ArmISA;
 
-TableWalker::TableWalker(const Params *p)
+TableWalker::TableWalker(const Params &p)
     : ClockedObject(p),
       stage2Mmu(NULL), port(NULL), requestorId(Request::invldRequestorId),
-      isStage2(p->is_stage2), tlb(NULL),
+      isStage2(p.is_stage2), tlb(NULL),
       currState(NULL), pending(false),
-      numSquashable(p->num_squash_per_cycle),
+      numSquashable(p.num_squash_per_cycle),
       stats(this),
       pendingReqs(0),
       pendingChangeTick(curTick()),
@@ -76,7 +76,7 @@ TableWalker::TableWalker(const Params *p)
 
     // Cache system-level properties
     if (FullSystem) {
-        ArmSystem *armSys = dynamic_cast<ArmSystem *>(p->sys);
+        ArmSystem *armSys = dynamic_cast<ArmSystem *>(p.sys);
         assert(armSys);
         haveSecurity = armSys->haveSecurity();
         _haveLPAE = armSys->haveLPAE();
@@ -178,7 +178,7 @@ TableWalker::drain()
 void
 TableWalker::drainResume()
 {
-    if (params()->sys->isTimingMode() && currState) {
+    if (params().sys->isTimingMode() && currState) {
         delete currState;
         currState = NULL;
         pendingChange();
@@ -2252,9 +2252,9 @@ TableWalker::insertTableEntry(DescriptorBase &descriptor, bool longDescriptor)
 }
 
 ArmISA::TableWalker *
-ArmTableWalkerParams::create()
+ArmTableWalkerParams::create() const
 {
-    return new ArmISA::TableWalker(this);
+    return new ArmISA::TableWalker(*this);
 }
 
 LookupLevel

src/arch/arm/table_walker.hh

@@ -914,13 +914,13 @@ class TableWalker : public ClockedObject
 
   public:
    typedef ArmTableWalkerParams Params;
-    TableWalker(const Params *p);
+    TableWalker(const Params &p);
     virtual ~TableWalker();
 
-    const Params *
+    const Params &
     params() const
     {
-        return dynamic_cast<const Params *>(_params);
+        return dynamic_cast<const Params &>(_params);
     }
 
     void init() override;

src/arch/arm/tlb.cc

@@ -72,16 +72,16 @@
 using namespace std;
 using namespace ArmISA;
 
-TLB::TLB(const ArmTLBParams *p)
-    : BaseTLB(p), table(new TlbEntry[p->size]), size(p->size),
-      isStage2(p->is_stage2), stage2Req(false), stage2DescReq(false), _attr(0),
-      directToStage2(false), tableWalker(p->walker), stage2Tlb(NULL),
+TLB::TLB(const ArmTLBParams &p)
+    : BaseTLB(p), table(new TlbEntry[p.size]), size(p.size),
+      isStage2(p.is_stage2), stage2Req(false), stage2DescReq(false), _attr(0),
+      directToStage2(false), tableWalker(p.walker), stage2Tlb(NULL),
       stage2Mmu(NULL), test(nullptr), stats(this),  rangeMRU(1),
       aarch64(false), aarch64EL(EL0), isPriv(false), isSecure(false),
       isHyp(false), asid(0), vmid(0), hcr(0), dacr(0),
       miscRegValid(false), miscRegContext(0), curTranType(NormalTran)
 {
-    const ArmSystem *sys = dynamic_cast<const ArmSystem *>(p->sys);
+    const ArmSystem *sys = dynamic_cast<const ArmSystem *>(p.sys);
 
     tableWalker->setTlb(this);
 
@@ -1641,7 +1641,7 @@ TLB::testWalk(Addr pa, Addr size, Addr va, bool is_secure, Mode mode,
 
 
 ArmISA::TLB *
-ArmTLBParams::create()
+ArmTLBParams::create() const
 {
-    return new ArmISA::TLB(this);
+    return new ArmISA::TLB(*this);
 }

src/arch/arm/tlb.hh

@@ -195,8 +195,8 @@ class TLB : public BaseTLB
     int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU
 
   public:
-    TLB(const ArmTLBParams *p);
-    TLB(const Params *p, int _size, TableWalker *_walker);
+    TLB(const ArmTLBParams &p);
+    TLB(const Params &p, int _size, TableWalker *_walker);
 
     /** Lookup an entry in the TLB
      * @param vpn virtual address
@@ -439,10 +439,10 @@ protected:
                        ArmTranslationType tranType = NormalTran);
 
 public:
-    const Params *
+    const Params &
     params() const
     {
-        return dynamic_cast<const Params *>(_params);
+        return dynamic_cast<const Params &>(_params);
     }
     inline void invalidateMiscReg() { miscRegValid = false; }
 

src/arch/arm/tracers/tarmac_parser.cc

@@ -1365,7 +1365,7 @@ TarmacParserRecord::iSetStateToStr(ISetState isetstate) const
 } // namespace Trace
 
 Trace::TarmacParser *
-TarmacParserParams::create()
+TarmacParserParams::create() const
 {
-    return new Trace::TarmacParser(this);
+    return new Trace::TarmacParser(*this);
 }

src/arch/arm/tracers/tarmac_parser.hh

@@ -216,17 +216,17 @@ class TarmacParser : public InstTracer
   public:
     typedef TarmacParserParams Params;
 
-    TarmacParser(const Params *p) : InstTracer(p), startPc(p->start_pc),
-                                    exitOnDiff(p->exit_on_diff),
-                                    exitOnInsnDiff(p->exit_on_insn_diff),
-                                    memWrCheck(p->mem_wr_check),
-                                    ignoredAddrRange(p->ignore_mem_addr),
-                                    cpuId(p->cpu_id),
+    TarmacParser(const Params &p) : InstTracer(p), startPc(p.start_pc),
+                                    exitOnDiff(p.exit_on_diff),
+                                    exitOnInsnDiff(p.exit_on_insn_diff),
+                                    memWrCheck(p.mem_wr_check),
+                                    ignoredAddrRange(p.ignore_mem_addr),
+                                    cpuId(p.cpu_id),
                                     macroopInProgress(false)
     {
         assert(!(exitOnDiff && exitOnInsnDiff));
 
-        trace.open(p->path_to_trace.c_str());
+        trace.open(p.path_to_trace.c_str());
         if (startPc == 0x0) {
             started = true;
         } else {

src/arch/arm/tracers/tarmac_tracer.cc

@@ -51,10 +51,10 @@ TarmacContext::tarmacCpuName() const
     return "cpu" + std::to_string(id);
 }
 
-TarmacTracer::TarmacTracer(const Params *p)
+TarmacTracer::TarmacTracer(const Params &p)
   : InstTracer(p),
-    startTick(p->start_tick),
-    endTick(p->end_tick)
+    startTick(p.start_tick),
+    endTick(p.end_tick)
 {
     // Wrong parameter setting: The trace end happens before the
     // trace start.
@@ -95,7 +95,7 @@ TarmacTracer::getInstRecord(Tick when, ThreadContext *tc,
 } // namespace Trace
 
 Trace::TarmacTracer *
-TarmacTracerParams::create()
+TarmacTracerParams::create() const
 {
-    return new Trace::TarmacTracer(this);
+    return new Trace::TarmacTracer(*this);
 }

src/arch/arm/tracers/tarmac_tracer.hh

@@ -87,7 +87,7 @@ class TarmacTracer : public InstTracer
   public:
     typedef TarmacTracerParams Params;
 
-    TarmacTracer(const Params *p);
+    TarmacTracer(const Params &p);
 
     /**
      * Generates a TarmacTracerRecord, depending on the Tarmac version.

src/arch/generic/interrupts.hh

@@ -42,14 +42,14 @@ class BaseInterrupts : public SimObject
   public:
     typedef BaseInterruptsParams Params;
 
-    BaseInterrupts(Params *p) : SimObject(p) {}
+    BaseInterrupts(const Params &p) : SimObject(p) {}
 
     virtual void setThreadContext(ThreadContext *_tc) { tc = _tc; }
 
-    const Params *
+    const Params &
     params() const
     {
-        return dynamic_cast<const Params *>(_params);
+        return dynamic_cast<const Params &>(_params);
     }
 
     /*

src/arch/generic/mmu.hh

@@ -47,8 +47,8 @@ class BaseMMU : public SimObject
   protected:
     typedef BaseMMUParams Params;
 
-    BaseMMU(const Params *p)
-      : SimObject(p), dtb(p->dtb), itb(p->itb)
+    BaseMMU(const Params &p)
+      : SimObject(p), dtb(p.dtb), itb(p.itb)
     {}
 
   public:

src/arch/generic/tlb.hh

@@ -50,7 +50,7 @@ class ThreadContext;
 class BaseTLB : public SimObject
 {
   protected:
-    BaseTLB(const Params *p) : SimObject(p) {}
+    BaseTLB(const Params &p) : SimObject(p) {}
 
   public:
 

src/arch/mips/interrupts.cc

@@ -186,7 +186,7 @@ Interrupts::interruptsPending() const
 }
 
 MipsISA::Interrupts *
-MipsInterruptsParams::create()
+MipsInterruptsParams::create() const
 {
-    return new MipsISA::Interrupts(this);
+    return new MipsISA::Interrupts(*this);
 }

src/arch/mips/interrupts.hh

@@ -49,13 +49,13 @@ class Interrupts : public BaseInterrupts
   public:
     typedef MipsInterruptsParams Params;
 
-    const Params *
+    const Params &
     params() const
     {
-        return dynamic_cast<const Params *>(_params);
+        return dynamic_cast<const Params &>(_params);
     }
 
-    Interrupts(Params * p) : BaseInterrupts(p) {}
+    Interrupts(const Params &p) : BaseInterrupts(p) {}
 
     //  post(int int_num, int index) is responsible
     //  for posting an interrupt. It sets a bit

src/arch/mips/isa.cc

@@ -87,8 +87,8 @@ ISA::miscRegNames[NumMiscRegs] =
     "LLFlag"
 };
 
-ISA::ISA(Params *p) : BaseISA(p), numThreads(p->num_threads),
-    numVpes(p->num_vpes)
+ISA::ISA(const Params &p) : BaseISA(p), numThreads(p.num_threads),
+    numVpes(p.num_vpes)
 {
     miscRegFile.resize(NumMiscRegs);
     bankType.resize(NumMiscRegs);
@@ -140,10 +140,10 @@ ISA::ISA(Params *p) : BaseISA(p), numThreads(p->num_threads),
     clear();
 }
 
-const MipsISAParams *
+const MipsISAParams &
 ISA::params() const
 {
-    return dynamic_cast<const Params *>(_params);
+    return dynamic_cast<const Params &>(_params);
 }
 
 void
@@ -570,7 +570,7 @@ ISA::processCP0Event(BaseCPU *cpu, CP0EventType cp0EventType)
 }
 
 MipsISA::ISA *
-MipsISAParams::create()
+MipsISAParams::create() const
 {
-    return new MipsISA::ISA(this);
+    return new MipsISA::ISA(*this);
 }

src/arch/mips/isa.hh

@@ -128,9 +128,9 @@ namespace MipsISA
         static std::string miscRegNames[NumMiscRegs];
 
       public:
-        const Params *params() const;
+        const Params &params() const;
 
-        ISA(Params *p);
+        ISA(const Params &p);
 
         RegId flattenRegId(const RegId& regId) const { return regId; }
 

src/arch/mips/linux/process.cc

@@ -52,7 +52,7 @@ class MipsLinuxObjectFileLoader : public Process::Loader
 {
   public:
     Process *
-    load(ProcessParams *params, ::Loader::ObjectFile *obj_file) override
+    load(const ProcessParams &params, ::Loader::ObjectFile *obj_file) override
     {
         if (obj_file->getArch() != ::Loader::Mips)
             return nullptr;
@@ -470,7 +470,7 @@ SyscallDescTable<MipsProcess::SyscallABI> MipsLinuxProcess::syscallDescs = {
     { 4319, "eventfd" }
 };
 
-MipsLinuxProcess::MipsLinuxProcess(ProcessParams * params,
+MipsLinuxProcess::MipsLinuxProcess(const ProcessParams &params,
                                    ::Loader::ObjectFile *objFile) :
     MipsProcess(params, objFile)
 {}

src/arch/mips/linux/process.hh

@@ -39,7 +39,8 @@ class MipsLinuxProcess : public MipsProcess
 {
   public:
     /// Constructor.
-    MipsLinuxProcess(ProcessParams * params, ::Loader::ObjectFile *objFile);
+    MipsLinuxProcess(const ProcessParams &params,
+                     ::Loader::ObjectFile *objFile);
 
     /// The target system's hostname.
     static const char *hostname;

src/arch/mips/mmu.cc

@@ -38,7 +38,7 @@
 #include "arch/mips/mmu.hh"
 
 MipsISA::MMU *
-MipsMMUParams::create()
+MipsMMUParams::create() const
 {
-    return new MipsISA::MMU(this);
+    return new MipsISA::MMU(*this);
 }

src/arch/mips/mmu.hh

@@ -47,7 +47,7 @@ namespace MipsISA {
 class MMU : public BaseMMU
 {
   public:
-    MMU(const MipsMMUParams *p)
+    MMU(const MipsMMUParams &p)
       : BaseMMU(p)
     {}
 };

src/arch/mips/process.cc

@@ -45,12 +45,13 @@
 using namespace std;
 using namespace MipsISA;
 
-MipsProcess::MipsProcess(ProcessParams *params, ::Loader::ObjectFile *objFile)
+MipsProcess::MipsProcess(const ProcessParams &params,
+                         ::Loader::ObjectFile *objFile)
     : Process(params,
-              new EmulationPageTable(params->name, params->pid, PageBytes),
+              new EmulationPageTable(params.name, params.pid, PageBytes),
               objFile)
 {
-    fatal_if(params->useArchPT, "Arch page tables not implemented.");
+    fatal_if(params.useArchPT, "Arch page tables not implemented.");
     // Set up stack. On MIPS, stack starts at the top of kuseg
     // user address space. MIPS stack grows down from here
     Addr stack_base = 0x7FFFFFFF;

src/arch/mips/process.hh

@@ -44,7 +44,7 @@ class ObjectFile;
 class MipsProcess : public Process
 {
   protected:
-    MipsProcess(ProcessParams * params, ::Loader::ObjectFile *objFile);
+    MipsProcess(const ProcessParams &params, ::Loader::ObjectFile *objFile);
 
     void initState();
 

src/arch/mips/tlb.cc

@@ -54,8 +54,7 @@ using namespace MipsISA;
 //  MIPS TLB
 //
 
-TLB::TLB(const Params *p)
-    : BaseTLB(p), size(p->size), nlu(0)
+TLB::TLB(const Params &p) : BaseTLB(p), size(p.size), nlu(0)
 {
     table = new PTE[size];
     memset(table, 0, sizeof(PTE[size]));
@@ -259,7 +258,7 @@ TLB::index(bool advance)
 }
 
 MipsISA::TLB *
-MipsTLBParams::create()
+MipsTLBParams::create() const
 {
-    return new MipsISA::TLB(this);
+    return new MipsISA::TLB(*this);
 }

src/arch/mips/tlb.hh

@@ -63,7 +63,7 @@ class TLB : public BaseTLB
 
   public:
     typedef MipsTLBParams Params;
-    TLB(const Params *p);
+    TLB(const Params &p);
 
     int probeEntry(Addr vpn,uint8_t) const;
     MipsISA::PTE *getEntry(unsigned) const;

src/arch/power/interrupts.cc

@@ -29,7 +29,7 @@
 #include "arch/power/interrupts.hh"
 
 PowerISA::Interrupts *
-PowerInterruptsParams::create()
+PowerInterruptsParams::create() const
 {
-    return new PowerISA::Interrupts(this);
+    return new PowerISA::Interrupts(*this);
 }

src/arch/power/interrupts.hh

@@ -43,13 +43,13 @@ class Interrupts : public BaseInterrupts
   public:
     typedef PowerInterruptsParams Params;
 
-    const Params *
+    const Params &
     params() const
     {
-        return dynamic_cast<const Params *>(_params);
+        return dynamic_cast<const Params &>(_params);
     }
 
-    Interrupts(Params *p) : BaseInterrupts(p) {}
+    Interrupts(const Params &p) : BaseInterrupts(p) {}
 
     void
     post(int int_num, int index)

src/arch/power/isa.cc

@@ -42,22 +42,22 @@
 namespace PowerISA
 {
 
-ISA::ISA(Params *p) : BaseISA(p)
+ISA::ISA(const Params &p) : BaseISA(p)
 {
     clear();
 }
 
-const PowerISAParams *
+const PowerISAParams &
 ISA::params() const
 {
-    return dynamic_cast<const Params *>(_params);
+    return dynamic_cast<const Params &>(_params);
 }
 
 }
 
 PowerISA::ISA *
-PowerISAParams::create()
+PowerISAParams::create() const
 {
-    return new PowerISA::ISA(this);
+    return new PowerISA::ISA(*this);
 }
 

src/arch/power/isa.hh

@@ -128,9 +128,9 @@ class ISA : public BaseISA
         return reg;
     }
 
-    const Params *params() const;
+    const Params &params() const;
 
-    ISA(Params *p);
+    ISA(const Params &p);
 };
 
 } // namespace PowerISA

src/arch/power/linux/process.cc

@@ -51,7 +51,7 @@ class PowerLinuxObjectFileLoader : public Process::Loader
 {
   public:
     Process *
-    load(ProcessParams *params, ::Loader::ObjectFile *obj_file) override
+    load(const ProcessParams &params, ::Loader::ObjectFile *obj_file) override
     {
         if (obj_file->getArch() != ::Loader::Power)
             return nullptr;
@@ -439,8 +439,8 @@ SyscallDescTable<PowerProcess::SyscallABI> PowerLinuxProcess::syscallDescs = {
     { 346, "epoll_pwait" },
 };
 
-PowerLinuxProcess::PowerLinuxProcess(ProcessParams * params,
-        ::Loader::ObjectFile *objFile) :
+PowerLinuxProcess::PowerLinuxProcess(const ProcessParams &params,
+                                     ::Loader::ObjectFile *objFile) :
     PowerProcess(params, objFile)
 {}
 

src/arch/power/linux/process.hh

@@ -38,7 +38,8 @@
 class PowerLinuxProcess : public PowerProcess
 {
   public:
-    PowerLinuxProcess(ProcessParams * params, ::Loader::ObjectFile *objFile);
+    PowerLinuxProcess(const ProcessParams &params,
+                      ::Loader::ObjectFile *objFile);
 
     void initState() override;
 

src/arch/power/mmu.cc

@@ -38,7 +38,7 @@
 #include "arch/power/mmu.hh"
 
 PowerISA::MMU *
-PowerMMUParams::create()
+PowerMMUParams::create() const
 {
-    return new PowerISA::MMU(this);
+    return new PowerISA::MMU(*this);
 }

src/arch/power/mmu.hh

@@ -47,7 +47,7 @@ namespace PowerISA {
 class MMU : public BaseMMU
 {
   public:
-    MMU(const PowerMMUParams *p)
+    MMU(const PowerMMUParams &p)
       : BaseMMU(p)
     {}
 };

src/arch/power/process.cc

@@ -47,12 +47,12 @@ using namespace std;
 using namespace PowerISA;
 
 PowerProcess::PowerProcess(
-        ProcessParams *params, ::Loader::ObjectFile *objFile)
+       const ProcessParams &params, ::Loader::ObjectFile *objFile)
     : Process(params,
-              new EmulationPageTable(params->name, params->pid, PageBytes),
+              new EmulationPageTable(params.name, params.pid, PageBytes),
               objFile)
 {
-    fatal_if(params->useArchPT, "Arch page tables not implemented.");
+    fatal_if(params.useArchPT, "Arch page tables not implemented.");
     // Set up break point (Top of Heap)
     Addr brk_point = image.maxAddr();
     brk_point = roundUp(brk_point, PageBytes);

src/arch/power/process.hh

@@ -45,7 +45,7 @@ class ObjectFile;
 class PowerProcess : public Process
 {
   protected:
-    PowerProcess(ProcessParams * params, ::Loader::ObjectFile *objFile);
+    PowerProcess(const ProcessParams &params, ::Loader::ObjectFile *objFile);
 
     void initState() override;
 

src/arch/power/tlb.cc

@@ -58,8 +58,7 @@ using namespace PowerISA;
 
 #define MODE2MASK(X) (1 << (X))
 
-TLB::TLB(const Params *p)
-    : BaseTLB(p), size(p->size), nlu(0)
+TLB::TLB(const Params &p) : BaseTLB(p), size(p.size), nlu(0)
 {
     table = new PowerISA::PTE[size];
     memset(table, 0, sizeof(PowerISA::PTE[size]));
@@ -281,7 +280,7 @@ TLB::index(bool advance)
 }
 
 PowerISA::TLB *
-PowerTLBParams::create()
+PowerTLBParams::create() const
 {
-    return new PowerISA::TLB(this);
+    return new PowerISA::TLB(*this);
 }

src/arch/power/tlb.hh

@@ -112,7 +112,7 @@ class TLB : public BaseTLB
 
   public:
     typedef PowerTLBParams Params;
-    TLB(const Params *p);
+    TLB(const Params &p);
     virtual ~TLB();
 
     void takeOverFrom(BaseTLB *otlb) override {}

src/arch/riscv/bare_metal/fs_workload.cc

@@ -36,10 +36,10 @@
 namespace RiscvISA
 {
 
-BareMetal::BareMetal(Params *p) : RiscvISA::FsWorkload(p),
-      bootloader(Loader::createObjectFile(p->bootloader))
+BareMetal::BareMetal(const Params &p) : RiscvISA::FsWorkload(p),
+      bootloader(Loader::createObjectFile(p.bootloader))
 {
-    fatal_if(!bootloader, "Could not load bootloader file %s.", p->bootloader);
+    fatal_if(!bootloader, "Could not load bootloader file %s.", p.bootloader);
     _resetVect = bootloader->entryPoint();
     bootloaderSymtab = bootloader->symtab();
 }
@@ -71,7 +71,7 @@ BareMetal::initState()
 } // namespace RiscvISA
 
 RiscvISA::BareMetal *
-RiscvBareMetalParams::create()
+RiscvBareMetalParams::create() const
 {
-    return new RiscvISA::BareMetal(this);
+    return new RiscvISA::BareMetal(*this);
 }

src/arch/riscv/bare_metal/fs_workload.hh

@@ -43,7 +43,7 @@ class BareMetal : public RiscvISA::FsWorkload
 
   public:
     typedef RiscvBareMetalParams Params;
-    BareMetal(Params *p);
+    BareMetal(const Params &p);
     ~BareMetal();
 
     void initState() override;

src/arch/riscv/fs_workload.hh

@@ -46,8 +46,8 @@ class FsWorkload : public Workload
     Addr _resetVect;
 
   public:
-    FsWorkload(RiscvFsWorkloadParams *p) : Workload(p),
-        _isBareMetal(p->bare_metal), _resetVect(p->reset_vect)
+    FsWorkload(const RiscvFsWorkloadParams &p) : Workload(p),
+        _isBareMetal(p.bare_metal), _resetVect(p.reset_vect)
     {}
 
     // return reset vector

src/arch/riscv/interrupts.cc

@@ -29,7 +29,7 @@
 #include "arch/riscv/interrupts.hh"
 
 RiscvISA::Interrupts *
-RiscvInterruptsParams::create()
+RiscvInterruptsParams::create() const
 {
-    return new RiscvISA::Interrupts(this);
+    return new RiscvISA::Interrupts(*this);
 }

src/arch/riscv/interrupts.hh

@@ -59,13 +59,13 @@ class Interrupts : public BaseInterrupts
   public:
     typedef RiscvInterruptsParams Params;
 
-    const Params *
+    const Params &
     params() const
     {
-        return dynamic_cast<const Params *>(_params);
+        return dynamic_cast<const Params &>(_params);
     }
 
-    Interrupts(Params * p) : BaseInterrupts(p), ip(0), ie(0) {}
+    Interrupts(const Params &p) : BaseInterrupts(p), ip(0), ie(0) {}
 
     std::bitset<NumInterruptTypes>
     globalMask() const

src/arch/riscv/isa.cc

@@ -176,16 +176,16 @@ M5_VAR_USED const std::array<const char *, NumMiscRegs> MiscRegNames = {{
     [MISCREG_FRM]           = "FRM",
 }};
 
-ISA::ISA(Params *p) : BaseISA(p)
+ISA::ISA(const Params &p) : BaseISA(p)
 {
     miscRegFile.resize(NumMiscRegs);
     clear();
 }
 
-const RiscvISAParams *
+const RiscvISAParams &
 ISA::params() const
 {
-    return dynamic_cast<const Params *>(_params);
+    return dynamic_cast<const Params &>(_params);
 }
 
 void ISA::clear()
@@ -413,7 +413,7 @@ ISA::unserialize(CheckpointIn &cp)
 }
 
 RiscvISA::ISA *
-RiscvISAParams::create()
+RiscvISAParams::create() const
 {
-    return new RiscvISA::ISA(this);
+    return new RiscvISA::ISA(*this);
 }

src/arch/riscv/isa.hh

@@ -98,9 +98,9 @@ class ISA : public BaseISA
     void serialize(CheckpointOut &cp) const;
     void unserialize(CheckpointIn &cp);
 
-    const Params *params() const;
+    const Params &params() const;
 
-    ISA(Params *p);
+    ISA(const Params &p);
 };
 
 } // namespace RiscvISA

src/arch/riscv/linux/process.cc

@@ -55,7 +55,7 @@ class RiscvLinuxObjectFileLoader : public Process::Loader
 {
   public:
     Process *
-    load(ProcessParams *params, ::Loader::ObjectFile *obj_file) override
+    load(const ProcessParams &params, ::Loader::ObjectFile *obj_file) override
     {
         auto arch = obj_file->getArch();
         auto opsys = obj_file->getOpSys();
@@ -776,7 +776,7 @@ SyscallDescTable<RiscvProcess::SyscallABI>
     { 2011, "getmainvars" }
 };
 
-RiscvLinuxProcess64::RiscvLinuxProcess64(ProcessParams * params,
+RiscvLinuxProcess64::RiscvLinuxProcess64(const ProcessParams &params,
     ::Loader::ObjectFile *objFile) : RiscvProcess64(params, objFile)
 {}
 
@@ -787,7 +787,7 @@ RiscvLinuxProcess64::syscall(ThreadContext *tc)
     syscallDescs.get(tc->readIntReg(SyscallNumReg))->doSyscall(tc);
 }
 
-RiscvLinuxProcess32::RiscvLinuxProcess32(ProcessParams * params,
+RiscvLinuxProcess32::RiscvLinuxProcess32(const ProcessParams &params,
     ::Loader::ObjectFile *objFile) : RiscvProcess32(params, objFile)
 {}
 

src/arch/riscv/linux/process.hh

@@ -42,7 +42,8 @@ class RiscvLinuxProcess64 : public RiscvProcess64
 {
   public:
     /// Constructor.
-    RiscvLinuxProcess64(ProcessParams * params, ::Loader::ObjectFile *objFile);
+    RiscvLinuxProcess64(const ProcessParams &params,
+                        ::Loader::ObjectFile *objFile);
 
     /// The target system's hostname.
     static const char *hostname;
@@ -60,7 +61,8 @@ class RiscvLinuxProcess32 : public RiscvProcess32
 {
   public:
     /// Constructor.
-    RiscvLinuxProcess32(ProcessParams * params, ::Loader::ObjectFile *objFile);
+    RiscvLinuxProcess32(const ProcessParams &params,
+                        ::Loader::ObjectFile *objFile);
 
     /// The target system's hostname.
     static const char *hostname;

src/arch/riscv/mmu.cc

@@ -38,7 +38,7 @@
 #include "arch/riscv/mmu.hh"
 
 RiscvISA::MMU *
-RiscvMMUParams::create()
+RiscvMMUParams::create() const
 {
-    return new RiscvISA::MMU(this);
+    return new RiscvISA::MMU(*this);
 }

src/arch/riscv/mmu.hh

@@ -47,7 +47,7 @@ namespace RiscvISA {
 class MMU : public BaseMMU
 {
   public:
-    MMU(const RiscvMMUParams *p)
+    MMU(const RiscvMMUParams &p)
       : BaseMMU(p)
     {}
 };