From 916bcbb4c49557a35ba3f95fae484a326d1a0428 Mon Sep 17 00:00:00 2001 From: Roger Chang Date: Tue, 3 Jan 2023 10:31:12 +0800 Subject: [PATCH] arch-riscv: Remove Riscv32CPU instance To use riscv 32 bits CPU, we can simply speficy by RiscvXXXCPU parameters like RiscvAtomicSimpleCPU(isa=RiscvISA(riscv_type="RV32"...)) Change-Id: I7ec66957f978062eda609b1a7e63468d23b5bab5 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66871 Reviewed-by: Jui-min Lee Maintainer: Bobby Bruce Tested-by: kokoro Reviewed-by: Bobby Bruce Reviewed-by: Yu-hsin Wang --- src/arch/riscv/RiscvCPU.py | 29 ----------------------------- 1 file changed, 29 deletions(-) diff --git a/src/arch/riscv/RiscvCPU.py b/src/arch/riscv/RiscvCPU.py index 678c3295c6..1c77045c67 100644 --- a/src/arch/riscv/RiscvCPU.py +++ b/src/arch/riscv/RiscvCPU.py @@ -23,8 +23,6 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -import functools - from m5.objects.BaseAtomicSimpleCPU import BaseAtomicSimpleCPU from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU @@ -43,13 +41,6 @@ class RiscvCPU: ArchISA = RiscvISA -class Riscv32CPU: - ArchDecoder = RiscvDecoder - ArchMMU = RiscvMMU - ArchInterrupts = RiscvInterrupts - ArchISA = functools.partial(RiscvISA, riscv_type="RV32") - - class RiscvAtomicSimpleCPU(BaseAtomicSimpleCPU, RiscvCPU): mmu = RiscvMMU() @@ -68,23 +59,3 @@ class RiscvO3CPU(BaseO3CPU, RiscvCPU): class RiscvMinorCPU(BaseMinorCPU, RiscvCPU): mmu = RiscvMMU() - - -class Riscv32AtomicSimpleCPU(BaseAtomicSimpleCPU, Riscv32CPU): - mmu = RiscvMMU() - - -class Riscv32NonCachingSimpleCPU(BaseNonCachingSimpleCPU, Riscv32CPU): - mmu = RiscvMMU() - - -class Riscv32TimingSimpleCPU(BaseTimingSimpleCPU, Riscv32CPU): - mmu = RiscvMMU() - - -class Riscv32O3CPU(BaseO3CPU, Riscv32CPU): - mmu = RiscvMMU() - - -class Riscv32MinorCPU(BaseMinorCPU, Riscv32CPU): - mmu = RiscvMMU()