From 9057eeabec7304df714f48e0df3641ddf60910d2 Mon Sep 17 00:00:00 2001 From: Hoa Nguyen Date: Tue, 19 Sep 2023 12:54:18 -0700 Subject: [PATCH] cpu: Explicitly define cache_line_size -> 64-bit unsigned int While it makes sense to define the cache_line_size as a 32-bit unsigned int, the use of cache_line_size is way out of its original scope. cache_line_size has been used to produce an address mask, which masking out the offset bits from an address. For example, [1], [2], [3], and [4]. However, since the cache_line_size is an "unsigned int", the type of the value is not guaranteed to be 64-bit long. Subsequently, the bit twiddling hacks in [1], [2], [3], and [4] produce 32-bit mask, i.e., 0x00000000FFFFFFC0. This behavior at least caused a problem in LLSC in RISC-V [5], where the load reservation (LR) relies on the mask to produce the cache block address. Two distinct 64-bit addresses can be mapped to the same cache block using the above mask. This patch explicitly defines cache_line_size as a 64-bit unsigned int so the cache block mask can be produced correctly for 64-bit addresses. [1] https://github.com/gem5/gem5/blob/3bdcfd6f7abdf0c9125ec37018df76a29998a055/src/cpu/simple/atomic.hh#L147 [2] https://github.com/gem5/gem5/blob/3bdcfd6f7abdf0c9125ec37018df76a29998a055/src/cpu/simple/timing.hh#L224 [3] https://github.com/gem5/gem5/blob/3bdcfd6f7abdf0c9125ec37018df76a29998a055/src/cpu/o3/lsq_unit.cc#L241 [4] https://github.com/gem5/gem5/blob/3bdcfd6f7abdf0c9125ec37018df76a29998a055/src/cpu/minor/lsq.cc#L1425 [5] https://github.com/gem5/gem5/blob/3bdcfd6f7abdf0c9125ec37018df76a29998a055/src/arch/riscv/isa.cc#L787 Change-Id: I29abc7aaab266a37326846bbf7a82219071c4ffe Signed-off-by: Hoa Nguyen --- src/cpu/base.hh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/cpu/base.hh b/src/cpu/base.hh index 3976b66fe4..a05102a107 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -143,7 +143,7 @@ class BaseCPU : public ClockedObject bool _switchedOut; /** Cache the cache line size that we get from the system */ - const unsigned int _cacheLineSize; + const uint64_t _cacheLineSize; /** Global CPU statistics that are merged into the Root object. */ struct GlobalStats : public statistics::Group @@ -394,7 +394,7 @@ class BaseCPU : public ClockedObject /** * Get the cache line size of the system. */ - inline unsigned int cacheLineSize() const { return _cacheLineSize; } + inline uint64_t cacheLineSize() const { return _cacheLineSize; } /** * Serialize this object to the given output stream.