From 3a8e5599b5082ac909256f50c310d4623184f3ac Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Mon, 12 Jul 2004 22:47:46 -0400 Subject: [PATCH 1/2] modified ccdrv to print out raw data. util/ccdrv/devtime.c: modified to print out raw data. --HG-- extra : convert_revision : 1f76ab8a022476e6a5ed787aa38547dd0ca99e36 --- util/ccdrv/devtime.c | 29 +++++++++++++++++++++-------- 1 file changed, 21 insertions(+), 8 deletions(-) diff --git a/util/ccdrv/devtime.c b/util/ccdrv/devtime.c index 5c17bf5ef7..c3897e597d 100644 --- a/util/ccdrv/devtime.c +++ b/util/ccdrv/devtime.c @@ -46,7 +46,6 @@ #define DRIVER_DESC "Interface to time uncacachable read and writes to device registers" #define DRIVER_VER "0.1" -static unsigned long devCnt, devSum, devSsq; static char *dataAddr = NULL; static int count = 0; @@ -58,7 +57,8 @@ static int __init devtime_start(void) uint32_t t1, t2; uint32_t trash; int x; - + uint32_t *times; + uint32_t num = 0; struct net_device *dev; @@ -68,15 +68,19 @@ static int __init devtime_start(void) { addr = simple_strtoull(dataAddr, NULL, 0); - devSum = 0; - devCnt = count; - addr = ioremap(addr, PAGE_SIZE); /** * Make sure that the remapping actually worked. On alpha we have * linear addressing, so its not a problem. But it can fail in x86 * if physical memory is mapped to this address. */ + times = kmalloc(sizeof(uint32_t) * count, GFP_USER); + if (!times) + { + printk("Could not allocate memory... Try again later.\n"); + return -1; + } + if (addr) { printk("Preparing to read %#llx %d times.\n", addr, count); @@ -86,7 +90,7 @@ static int __init devtime_start(void) { trash = readl(addr); t2 = cycleCounter(trash); - devSum += t2 - t1; + times[num++] = t2 - t1; t1 = t2; } @@ -95,7 +99,16 @@ static int __init devtime_start(void) */ iounmap(addr); - printk("Read Address %#llx %ld times. Average latency %ld.\n", addr, devCnt, devSum/devCnt); + printk("Measurements:\n"); + for (x = 0; x < count; x++) + { + printk("%d ", times[x]); + if (((x+1) % 10) == 0) + printk("\n"); + } + printk("\nDone.\n"); + + } else printk("Unable to remap address. Please try again later.\n"); @@ -154,7 +167,7 @@ static void __exit devtime_end(void) { module_init(devtime_start); module_exit(devtime_end); -MODULE_LICENSE("BSD"); +MODULE_LICENSE("Dual BSD/GPL"); MODULE_AUTHOR(DRIVER_AUTHOR); MODULE_DESCRIPTION(DRIVER_DESC); module_param(dataAddr, charp, 0); From 6c954de33ea598dfd356f315b3cea620acc3b8b7 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Mon, 2 Aug 2004 17:10:02 -0400 Subject: [PATCH 2/2] added m5 debug and m5 switch cpu instruction (doesn't work yet) and a p4 memory/cpu config arch/alpha/alpha_memory.cc: Added code to fault on an unaligned access arch/alpha/isa_desc: arch/alpha/pseudo_inst.cc: arch/alpha/pseudo_inst.hh: Added m5debug break and m5switchcpu (the latter doesn't work) --HG-- extra : convert_revision : 409e73adb151600a4fea49f35bf6f503f66fa916 --- arch/alpha/alpha_memory.cc | 8 ++++++++ arch/alpha/isa_desc | 13 ++++++++++++- arch/alpha/pseudo_inst.cc | 16 ++++++++++++++++ arch/alpha/pseudo_inst.hh | 2 ++ 4 files changed, 38 insertions(+), 1 deletion(-) diff --git a/arch/alpha/alpha_memory.cc b/arch/alpha/alpha_memory.cc index 5d9a5fc6f7..9f5ab185e1 100644 --- a/arch/alpha/alpha_memory.cc +++ b/arch/alpha/alpha_memory.cc @@ -491,6 +491,14 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const AlphaISA::mode_type mode = (AlphaISA::mode_type)DTB_CM_CM(ipr[AlphaISA::IPR_DTB_CM]); + + /* @todo this should actually be in there but for whatever reason + * Its not working at present. + */ + if (req->vaddr & (req->size - 1)) { + return Alignment_Fault; + } + if (PC_PAL(pc)) { mode = (req->flags & ALTMODE) ? (AlphaISA::mode_type)ALT_MODE_AM(ipr[AlphaISA::IPR_ALT_MODE]) diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc index fa24e52152..d6b99a8ae1 100644 --- a/arch/alpha/isa_desc +++ b/arch/alpha/isa_desc @@ -2400,7 +2400,11 @@ decode OPCODE default Unknown::unknown() { format BasicOperate { 0xc000: rpcc({{ #ifdef FULL_SYSTEM - Ra = xc->readIpr(AlphaISA::IPR_CC, fault); + /* Rb is a fake dependency so here is a fun way to get + * the parser to understand that. + */ + Ra = xc->readIpr(AlphaISA::IPR_CC, fault) + (Rb & 0); + #else Ra = curTick; #endif @@ -2543,6 +2547,13 @@ decode OPCODE default Unknown::unknown() { 0x50: m5readfile({{ AlphaPseudo::readfile(xc->xcBase()); }}, IsNonSpeculative); + 0x51: m5break({{ + AlphaPseudo::debugbreak(xc->xcBase()); + }}, IsNonSpeculative); + 0x52: m5switchcpu({{ + AlphaPseudo::switchcpu(xc->xcBase()); + }}, IsNonSpeculative); + } } diff --git a/arch/alpha/pseudo_inst.cc b/arch/alpha/pseudo_inst.cc index 3702669092..fd67428015 100644 --- a/arch/alpha/pseudo_inst.cc +++ b/arch/alpha/pseudo_inst.cc @@ -35,6 +35,7 @@ #include "arch/alpha/pseudo_inst.hh" #include "arch/alpha/vtophys.hh" #include "cpu/base_cpu.hh" +#include "cpu/sampling_cpu/sampling_cpu.hh" #include "cpu/exec_context.hh" #include "sim/param.hh" #include "sim/serialize.hh" @@ -42,8 +43,12 @@ #include "sim/stat_control.hh" #include "sim/stats.hh" #include "sim/system.hh" +#include "sim/debug.hh" using namespace std; + +extern SamplingCPU *SampCPU; + using namespace Stats; namespace AlphaPseudo @@ -219,4 +224,15 @@ namespace AlphaPseudo doStatisticsInsts = __statistics; doCheckpointInsts = __checkpoint; } + + void debugbreak(ExecContext *xc) + { + debug_break(); + } + + void switchcpu(ExecContext *xc) + { + if (SampCPU) + SampCPU->switchCPUs(); + } } diff --git a/arch/alpha/pseudo_inst.hh b/arch/alpha/pseudo_inst.hh index 22e5d43aec..46347ad695 100644 --- a/arch/alpha/pseudo_inst.hh +++ b/arch/alpha/pseudo_inst.hh @@ -48,4 +48,6 @@ namespace AlphaPseudo void dumpresetstats(ExecContext *xc); void m5checkpoint(ExecContext *xc); void readfile(ExecContext *xc); + void debugbreak(ExecContext *xc); + void switchcpu(ExecContext *xc); }