From 8f199c9b7cd51ea64c7682aea26c6333d6b196ba Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Sun, 19 Dec 2021 08:15:24 +0100 Subject: [PATCH] arch-arm: Reimplement decodeAArch64SysReg using new decode map Signed-off-by: Giacomo Travaglini Change-Id: Ief6c9d666b01248ea4e01414f575a5c5758618ba Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55605 Reviewed-by: Richard Cooper Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg Tested-by: kokoro --- src/arch/arm/regs/misc.cc | 1965 +------------------------------------ 1 file changed, 19 insertions(+), 1946 deletions(-) diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index 212a4ff9cf..99ea64bfef 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -1450,1952 +1450,6 @@ canWriteAArch64SysReg(MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr, } } -MiscRegIndex -decodeAArch64SysReg(unsigned op0, unsigned op1, - unsigned crn, unsigned crm, - unsigned op2) -{ - switch (op0) { - case 1: - switch (crn) { - case 7: - switch (op1) { - case 0: - switch (crm) { - case 1: - switch (op2) { - case 0: - return MISCREG_IC_IALLUIS; - } - break; - case 5: - switch (op2) { - case 0: - return MISCREG_IC_IALLU; - } - break; - case 6: - switch (op2) { - case 1: - return MISCREG_DC_IVAC_Xt; - case 2: - return MISCREG_DC_ISW_Xt; - } - break; - case 8: - switch (op2) { - case 0: - return MISCREG_AT_S1E1R_Xt; - case 1: - return MISCREG_AT_S1E1W_Xt; - case 2: - return MISCREG_AT_S1E0R_Xt; - case 3: - return MISCREG_AT_S1E0W_Xt; - } - break; - case 10: - switch (op2) { - case 2: - return MISCREG_DC_CSW_Xt; - } - break; - case 14: - switch (op2) { - case 2: - return MISCREG_DC_CISW_Xt; - } - break; - } - break; - case 3: - switch (crm) { - case 4: - switch (op2) { - case 1: - return MISCREG_DC_ZVA_Xt; - } - break; - case 5: - switch (op2) { - case 1: - return MISCREG_IC_IVAU_Xt; - } - break; - case 10: - switch (op2) { - case 1: - return MISCREG_DC_CVAC_Xt; - } - break; - case 11: - switch (op2) { - case 1: - return MISCREG_DC_CVAU_Xt; - } - break; - case 14: - switch (op2) { - case 1: - return MISCREG_DC_CIVAC_Xt; - } - break; - } - break; - case 4: - switch (crm) { - case 8: - switch (op2) { - case 0: - return MISCREG_AT_S1E2R_Xt; - case 1: - return MISCREG_AT_S1E2W_Xt; - case 4: - return MISCREG_AT_S12E1R_Xt; - case 5: - return MISCREG_AT_S12E1W_Xt; - case 6: - return MISCREG_AT_S12E0R_Xt; - case 7: - return MISCREG_AT_S12E0W_Xt; - } - break; - } - break; - case 6: - switch (crm) { - case 8: - switch (op2) { - case 0: - return MISCREG_AT_S1E3R_Xt; - case 1: - return MISCREG_AT_S1E3W_Xt; - } - break; - } - break; - } - break; - case 8: - switch (op1) { - case 0: - switch (crm) { - case 3: - switch (op2) { - case 0: - return MISCREG_TLBI_VMALLE1IS; - case 1: - return MISCREG_TLBI_VAE1IS_Xt; - case 2: - return MISCREG_TLBI_ASIDE1IS_Xt; - case 3: - return MISCREG_TLBI_VAAE1IS_Xt; - case 5: - return MISCREG_TLBI_VALE1IS_Xt; - case 7: - return MISCREG_TLBI_VAALE1IS_Xt; - } - break; - case 7: - switch (op2) { - case 0: - return MISCREG_TLBI_VMALLE1; - case 1: - return MISCREG_TLBI_VAE1_Xt; - case 2: - return MISCREG_TLBI_ASIDE1_Xt; - case 3: - return MISCREG_TLBI_VAAE1_Xt; - case 5: - return MISCREG_TLBI_VALE1_Xt; - case 7: - return MISCREG_TLBI_VAALE1_Xt; - } - break; - } - break; - case 4: - switch (crm) { - case 0: - switch (op2) { - case 1: - return MISCREG_TLBI_IPAS2E1IS_Xt; - case 5: - return MISCREG_TLBI_IPAS2LE1IS_Xt; - } - break; - case 3: - switch (op2) { - case 0: - return MISCREG_TLBI_ALLE2IS; - case 1: - return MISCREG_TLBI_VAE2IS_Xt; - case 4: - return MISCREG_TLBI_ALLE1IS; - case 5: - return MISCREG_TLBI_VALE2IS_Xt; - case 6: - return MISCREG_TLBI_VMALLS12E1IS; - } - break; - case 4: - switch (op2) { - case 1: - return MISCREG_TLBI_IPAS2E1_Xt; - case 5: - return MISCREG_TLBI_IPAS2LE1_Xt; - } - break; - case 7: - switch (op2) { - case 0: - return MISCREG_TLBI_ALLE2; - case 1: - return MISCREG_TLBI_VAE2_Xt; - case 4: - return MISCREG_TLBI_ALLE1; - case 5: - return MISCREG_TLBI_VALE2_Xt; - case 6: - return MISCREG_TLBI_VMALLS12E1; - } - break; - } - break; - case 6: - switch (crm) { - case 3: - switch (op2) { - case 0: - return MISCREG_TLBI_ALLE3IS; - case 1: - return MISCREG_TLBI_VAE3IS_Xt; - case 5: - return MISCREG_TLBI_VALE3IS_Xt; - } - break; - case 7: - switch (op2) { - case 0: - return MISCREG_TLBI_ALLE3; - case 1: - return MISCREG_TLBI_VAE3_Xt; - case 5: - return MISCREG_TLBI_VALE3_Xt; - } - break; - } - break; - } - break; - case 11: - case 15: - // SYS Instruction with CRn = { 11, 15 } - // (Trappable by HCR_EL2.TIDCP) - return MISCREG_IMPDEF_UNIMPL; - } - break; - case 2: - switch (crn) { - case 0: - switch (op1) { - case 0: - switch (crm) { - case 0: - switch (op2) { - case 2: - return MISCREG_OSDTRRX_EL1; - case 4: - return MISCREG_DBGBVR0_EL1; - case 5: - return MISCREG_DBGBCR0_EL1; - case 6: - return MISCREG_DBGWVR0_EL1; - case 7: - return MISCREG_DBGWCR0_EL1; - } - break; - case 1: - switch (op2) { - case 4: - return MISCREG_DBGBVR1_EL1; - case 5: - return MISCREG_DBGBCR1_EL1; - case 6: - return MISCREG_DBGWVR1_EL1; - case 7: - return MISCREG_DBGWCR1_EL1; - } - break; - case 2: - switch (op2) { - case 0: - return MISCREG_MDCCINT_EL1; - case 2: - return MISCREG_MDSCR_EL1; - case 4: - return MISCREG_DBGBVR2_EL1; - case 5: - return MISCREG_DBGBCR2_EL1; - case 6: - return MISCREG_DBGWVR2_EL1; - case 7: - return MISCREG_DBGWCR2_EL1; - } - break; - case 3: - switch (op2) { - case 2: - return MISCREG_OSDTRTX_EL1; - case 4: - return MISCREG_DBGBVR3_EL1; - case 5: - return MISCREG_DBGBCR3_EL1; - case 6: - return MISCREG_DBGWVR3_EL1; - case 7: - return MISCREG_DBGWCR3_EL1; - } - break; - case 4: - switch (op2) { - case 4: - return MISCREG_DBGBVR4_EL1; - case 5: - return MISCREG_DBGBCR4_EL1; - case 6: - return MISCREG_DBGWVR4_EL1; - case 7: - return MISCREG_DBGWCR4_EL1; - } - break; - case 5: - switch (op2) { - case 4: - return MISCREG_DBGBVR5_EL1; - case 5: - return MISCREG_DBGBCR5_EL1; - case 6: - return MISCREG_DBGWVR5_EL1; - case 7: - return MISCREG_DBGWCR5_EL1; - } - break; - case 6: - switch (op2) { - case 2: - return MISCREG_OSECCR_EL1; - case 4: - return MISCREG_DBGBVR6_EL1; - case 5: - return MISCREG_DBGBCR6_EL1; - case 6: - return MISCREG_DBGWVR6_EL1; - case 7: - return MISCREG_DBGWCR6_EL1; - } - break; - case 7: - switch (op2) { - case 4: - return MISCREG_DBGBVR7_EL1; - case 5: - return MISCREG_DBGBCR7_EL1; - case 6: - return MISCREG_DBGWVR7_EL1; - case 7: - return MISCREG_DBGWCR7_EL1; - } - break; - case 8: - switch (op2) { - case 4: - return MISCREG_DBGBVR8_EL1; - case 5: - return MISCREG_DBGBCR8_EL1; - case 6: - return MISCREG_DBGWVR8_EL1; - case 7: - return MISCREG_DBGWCR8_EL1; - } - break; - case 9: - switch (op2) { - case 4: - return MISCREG_DBGBVR9_EL1; - case 5: - return MISCREG_DBGBCR9_EL1; - case 6: - return MISCREG_DBGWVR9_EL1; - case 7: - return MISCREG_DBGWCR9_EL1; - } - break; - case 10: - switch (op2) { - case 4: - return MISCREG_DBGBVR10_EL1; - case 5: - return MISCREG_DBGBCR10_EL1; - case 6: - return MISCREG_DBGWVR10_EL1; - case 7: - return MISCREG_DBGWCR10_EL1; - } - break; - case 11: - switch (op2) { - case 4: - return MISCREG_DBGBVR11_EL1; - case 5: - return MISCREG_DBGBCR11_EL1; - case 6: - return MISCREG_DBGWVR11_EL1; - case 7: - return MISCREG_DBGWCR11_EL1; - } - break; - case 12: - switch (op2) { - case 4: - return MISCREG_DBGBVR12_EL1; - case 5: - return MISCREG_DBGBCR12_EL1; - case 6: - return MISCREG_DBGWVR12_EL1; - case 7: - return MISCREG_DBGWCR12_EL1; - } - break; - case 13: - switch (op2) { - case 4: - return MISCREG_DBGBVR13_EL1; - case 5: - return MISCREG_DBGBCR13_EL1; - case 6: - return MISCREG_DBGWVR13_EL1; - case 7: - return MISCREG_DBGWCR13_EL1; - } - break; - case 14: - switch (op2) { - case 4: - return MISCREG_DBGBVR14_EL1; - case 5: - return MISCREG_DBGBCR14_EL1; - case 6: - return MISCREG_DBGWVR14_EL1; - case 7: - return MISCREG_DBGWCR14_EL1; - } - break; - case 15: - switch (op2) { - case 4: - return MISCREG_DBGBVR15_EL1; - case 5: - return MISCREG_DBGBCR15_EL1; - case 6: - return MISCREG_DBGWVR15_EL1; - case 7: - return MISCREG_DBGWCR15_EL1; - } - break; - } - break; - case 2: - switch (crm) { - case 0: - switch (op2) { - case 0: - return MISCREG_TEECR32_EL1; - } - break; - } - break; - case 3: - switch (crm) { - case 1: - switch (op2) { - case 0: - return MISCREG_MDCCSR_EL0; - } - break; - case 4: - switch (op2) { - case 0: - return MISCREG_MDDTR_EL0; - } - break; - case 5: - switch (op2) { - case 0: - return MISCREG_MDDTRRX_EL0; - } - break; - } - break; - case 4: - switch (crm) { - case 7: - switch (op2) { - case 0: - return MISCREG_DBGVCR32_EL2; - } - break; - } - break; - } - break; - case 1: - switch (op1) { - case 0: - switch (crm) { - case 0: - switch (op2) { - case 0: - return MISCREG_MDRAR_EL1; - case 4: - return MISCREG_OSLAR_EL1; - } - break; - case 1: - switch (op2) { - case 4: - return MISCREG_OSLSR_EL1; - } - break; - case 3: - switch (op2) { - case 4: - return MISCREG_OSDLR_EL1; - } - break; - case 4: - switch (op2) { - case 4: - return MISCREG_DBGPRCR_EL1; - } - break; - } - break; - case 2: - switch (crm) { - case 0: - switch (op2) { - case 0: - return MISCREG_TEEHBR32_EL1; - } - break; - } - break; - } - break; - case 7: - switch (op1) { - case 0: - switch (crm) { - case 8: - switch (op2) { - case 6: - return MISCREG_DBGCLAIMSET_EL1; - } - break; - case 9: - switch (op2) { - case 6: - return MISCREG_DBGCLAIMCLR_EL1; - } - break; - case 14: - switch (op2) { - case 6: - return MISCREG_DBGAUTHSTATUS_EL1; - } - break; - } - break; - } - break; - } - break; - case 3: - switch (crn) { - case 0: - switch (op1) { - case 0: - switch (crm) { - case 0: - switch (op2) { - case 0: - return MISCREG_MIDR_EL1; - case 5: - return MISCREG_MPIDR_EL1; - case 6: - return MISCREG_REVIDR_EL1; - } - break; - case 1: - switch (op2) { - case 0: - return MISCREG_ID_PFR0_EL1; - case 1: - return MISCREG_ID_PFR1_EL1; - case 2: - return MISCREG_ID_DFR0_EL1; - case 3: - return MISCREG_ID_AFR0_EL1; - case 4: - return MISCREG_ID_MMFR0_EL1; - case 5: - return MISCREG_ID_MMFR1_EL1; - case 6: - return MISCREG_ID_MMFR2_EL1; - case 7: - return MISCREG_ID_MMFR3_EL1; - } - break; - case 2: - switch (op2) { - case 0: - return MISCREG_ID_ISAR0_EL1; - case 1: - return MISCREG_ID_ISAR1_EL1; - case 2: - return MISCREG_ID_ISAR2_EL1; - case 3: - return MISCREG_ID_ISAR3_EL1; - case 4: - return MISCREG_ID_ISAR4_EL1; - case 5: - return MISCREG_ID_ISAR5_EL1; - case 6: - return MISCREG_ID_MMFR4_EL1; - case 7: - return MISCREG_ID_ISAR6_EL1; - } - break; - case 3: - switch (op2) { - case 0: - return MISCREG_MVFR0_EL1; - case 1: - return MISCREG_MVFR1_EL1; - case 2: - return MISCREG_MVFR2_EL1; - case 3 ... 7: - return MISCREG_RAZ; - } - break; - case 4: - switch (op2) { - case 0: - return MISCREG_ID_AA64PFR0_EL1; - case 1: - return MISCREG_ID_AA64PFR1_EL1; - case 2 ... 3: - return MISCREG_RAZ; - case 4: - return MISCREG_ID_AA64ZFR0_EL1; - case 5 ... 7: - return MISCREG_RAZ; - } - break; - case 5: - switch (op2) { - case 0: - return MISCREG_ID_AA64DFR0_EL1; - case 1: - return MISCREG_ID_AA64DFR1_EL1; - case 4: - return MISCREG_ID_AA64AFR0_EL1; - case 5: - return MISCREG_ID_AA64AFR1_EL1; - case 2: - case 3: - case 6: - case 7: - return MISCREG_RAZ; - } - break; - case 6: - switch (op2) { - case 0: - return MISCREG_ID_AA64ISAR0_EL1; - case 1: - return MISCREG_ID_AA64ISAR1_EL1; - case 2 ... 7: - return MISCREG_RAZ; - } - break; - case 7: - switch (op2) { - case 0: - return MISCREG_ID_AA64MMFR0_EL1; - case 1: - return MISCREG_ID_AA64MMFR1_EL1; - case 2: - return MISCREG_ID_AA64MMFR2_EL1; - case 3 ... 7: - return MISCREG_RAZ; - } - break; - } - break; - case 1: - switch (crm) { - case 0: - switch (op2) { - case 0: - return MISCREG_CCSIDR_EL1; - case 1: - return MISCREG_CLIDR_EL1; - case 7: - return MISCREG_AIDR_EL1; - } - break; - } - break; - case 2: - switch (crm) { - case 0: - switch (op2) { - case 0: - return MISCREG_CSSELR_EL1; - } - break; - } - break; - case 3: - switch (crm) { - case 0: - switch (op2) { - case 1: - return MISCREG_CTR_EL0; - case 7: - return MISCREG_DCZID_EL0; - } - break; - } - break; - case 4: - switch (crm) { - case 0: - switch (op2) { - case 0: - return MISCREG_VPIDR_EL2; - case 5: - return MISCREG_VMPIDR_EL2; - } - break; - } - break; - } - break; - case 1: - switch (op1) { - case 0: - switch (crm) { - case 0: - switch (op2) { - case 0: - return MISCREG_SCTLR_EL1; - case 1: - return MISCREG_ACTLR_EL1; - case 2: - return MISCREG_CPACR_EL1; - } - break; - case 2: - switch (op2) { - case 0: - return MISCREG_ZCR_EL1; - } - break; - } - break; - case 4: - switch (crm) { - case 0: - switch (op2) { - case 0: - return MISCREG_SCTLR_EL2; - case 1: - return MISCREG_ACTLR_EL2; - } - break; - case 1: - switch (op2) { - case 0: - return MISCREG_HCR_EL2; - case 1: - return MISCREG_MDCR_EL2; - case 2: - return MISCREG_CPTR_EL2; - case 3: - return MISCREG_HSTR_EL2; - case 7: - return MISCREG_HACR_EL2; - } - break; - case 2: - switch (op2) { - case 0: - return MISCREG_ZCR_EL2; - } - break; - } - break; - case 5: - /* op0: 3 Crn:1 op1:5 */ - switch (crm) { - case 0: - switch (op2) { - case 0: - return MISCREG_SCTLR_EL12; - case 2: - return MISCREG_CPACR_EL12; - } - break; - case 2: - switch (op2) { - case 0: - return MISCREG_ZCR_EL12; - } - break; - } - break; - case 6: - switch (crm) { - case 0: - switch (op2) { - case 0: - return MISCREG_SCTLR_EL3; - case 1: - return MISCREG_ACTLR_EL3; - } - break; - case 1: - switch (op2) { - case 0: - return MISCREG_SCR_EL3; - case 1: - return MISCREG_SDER32_EL3; - case 2: - return MISCREG_CPTR_EL3; - } - break; - case 2: - switch (op2) { - case 0: - return MISCREG_ZCR_EL3; - } - break; - case 3: - switch (op2) { - case 1: - return MISCREG_MDCR_EL3; - } - break; - } - break; - } - break; - case 2: - switch (op1) { - case 0: - switch (crm) { - case 0: - switch (op2) { - case 0: - return MISCREG_TTBR0_EL1; - case 1: - return MISCREG_TTBR1_EL1; - case 2: - return MISCREG_TCR_EL1; - } - break; - case 0x1: - switch (op2) { - case 0x0: - return MISCREG_APIAKeyLo_EL1; - case 0x1: - return MISCREG_APIAKeyHi_EL1; - case 0x2: - return MISCREG_APIBKeyLo_EL1; - case 0x3: - return MISCREG_APIBKeyHi_EL1; - } - break; - case 0x2: - switch (op2) { - case 0x0: - return MISCREG_APDAKeyLo_EL1; - case 0x1: - return MISCREG_APDAKeyHi_EL1; - case 0x2: - return MISCREG_APDBKeyLo_EL1; - case 0x3: - return MISCREG_APDBKeyHi_EL1; - } - break; - - case 0x3: - switch (op2) { - case 0x0: - return MISCREG_APGAKeyLo_EL1; - case 0x1: - return MISCREG_APGAKeyHi_EL1; - } - break; - } - break; - case 4: - switch (crm) { - case 0: - switch (op2) { - case 0: - return MISCREG_TTBR0_EL2; - case 1: - return MISCREG_TTBR1_EL2; - case 2: - return MISCREG_TCR_EL2; - } - break; - case 1: - switch (op2) { - case 0: - return MISCREG_VTTBR_EL2; - case 2: - return MISCREG_VTCR_EL2; - } - break; - case 6: - switch (op2) { - case 0: - return MISCREG_VSTTBR_EL2; - case 2: - return MISCREG_VSTCR_EL2; - } - break; - } - break; - case 5: - /* op0: 3 Crn:2 op1:5 */ - switch (crm) { - case 0: - switch (op2) { - case 0: - return MISCREG_TTBR0_EL12; - case 1: - return MISCREG_TTBR1_EL12; - case 2: - return MISCREG_TCR_EL12; - } - break; - } - break; - case 6: - switch (crm) { - case 0: - switch (op2) { - case 0: - return MISCREG_TTBR0_EL3; - case 2: - return MISCREG_TCR_EL3; - } - break; - } - break; - } - break; - case 3: - switch (op1) { - case 4: - switch (crm) { - case 0: - switch (op2) { - case 0: - return MISCREG_DACR32_EL2; - } - break; - } - break; - } - break; - case 4: - switch (op1) { - case 0: - switch (crm) { - case 0: - switch (op2) { - case 0: - return MISCREG_SPSR_EL1; - case 1: - return MISCREG_ELR_EL1; - } - break; - case 1: - switch (op2) { - case 0: - return MISCREG_SP_EL0; - } - break; - case 2: - switch (op2) { - case 0: - return MISCREG_SPSEL; - case 2: - return MISCREG_CURRENTEL; - case 3: - return MISCREG_PAN; - case 4: - return MISCREG_UAO; - } - break; - case 6: - switch (op2) { - case 0: - return MISCREG_ICC_PMR_EL1; - } - break; - } - break; - case 3: - switch (crm) { - case 2: - switch (op2) { - case 0: - return MISCREG_NZCV; - case 1: - return MISCREG_DAIF; - } - break; - case 4: - switch (op2) { - case 0: - return MISCREG_FPCR; - case 1: - return MISCREG_FPSR; - } - break; - case 5: - switch (op2) { - case 0: - return MISCREG_DSPSR_EL0; - case 1: - return MISCREG_DLR_EL0; - } - break; - } - break; - case 4: - switch (crm) { - case 0: - switch (op2) { - case 0: - return MISCREG_SPSR_EL2; - case 1: - return MISCREG_ELR_EL2; - } - break; - case 1: - switch (op2) { - case 0: - return MISCREG_SP_EL1; - } - break; - case 3: - switch (op2) { - case 0: - return MISCREG_SPSR_IRQ_AA64; - case 1: - return MISCREG_SPSR_ABT_AA64; - case 2: - return MISCREG_SPSR_UND_AA64; - case 3: - return MISCREG_SPSR_FIQ_AA64; - } - break; - } - break; - case 5: - switch (crm) { - case 0: - switch (op2) { - case 0: - return MISCREG_SPSR_EL12; - case 1: - return MISCREG_ELR_EL12; - } - break; - } - break; - case 6: - switch (crm) { - case 0: - switch (op2) { - case 0: - return MISCREG_SPSR_EL3; - case 1: - return MISCREG_ELR_EL3; - } - break; - case 1: - switch (op2) { - case 0: - return MISCREG_SP_EL2; - } - break; - } - break; - } - break; - case 5: - switch (op1) { - case 0: - switch (crm) { - case 1: - switch (op2) { - case 0: - return MISCREG_AFSR0_EL1; - case 1: - return MISCREG_AFSR1_EL1; - } - break; - case 2: - switch (op2) { - case 0: - return MISCREG_ESR_EL1; - } - break; - case 3: - switch (op2) { - case 0: - return MISCREG_ERRIDR_EL1; - case 1: - return MISCREG_ERRSELR_EL1; - } - break; - case 4: - switch (op2) { - case 0: - return MISCREG_ERXFR_EL1; - case 1: - return MISCREG_ERXCTLR_EL1; - case 2: - return MISCREG_ERXSTATUS_EL1; - case 3: - return MISCREG_ERXADDR_EL1; - } - break; - case 5: - switch (op2) { - case 0: - return MISCREG_ERXMISC0_EL1; - case 1: - return MISCREG_ERXMISC1_EL1; - } - break; - } - break; - case 4: - switch (crm) { - case 0: - switch (op2) { - case 1: - return MISCREG_IFSR32_EL2; - } - break; - case 1: - switch (op2) { - case 0: - return MISCREG_AFSR0_EL2; - case 1: - return MISCREG_AFSR1_EL2; - } - break; - case 2: - switch (op2) { - case 0: - return MISCREG_ESR_EL2; - case 3: - return MISCREG_VSESR_EL2; - } - break; - case 3: - switch (op2) { - case 0: - return MISCREG_FPEXC32_EL2; - } - break; - } - break; - case 5: - switch (crm) { - case 1: - switch (op2) { - case 0: - return MISCREG_AFSR0_EL12; - case 1: - return MISCREG_AFSR1_EL12; - } - break; - case 2: - switch (op2) { - case 0: - return MISCREG_ESR_EL12; - } - break; - } - break; - case 6: - switch (crm) { - case 1: - switch (op2) { - case 0: - return MISCREG_AFSR0_EL3; - case 1: - return MISCREG_AFSR1_EL3; - } - break; - case 2: - switch (op2) { - case 0: - return MISCREG_ESR_EL3; - } - break; - } - break; - } - break; - case 6: - switch (op1) { - case 0: - switch (crm) { - case 0: - switch (op2) { - case 0: - return MISCREG_FAR_EL1; - } - break; - } - break; - case 4: - switch (crm) { - case 0: - switch (op2) { - case 0: - return MISCREG_FAR_EL2; - case 4: - return MISCREG_HPFAR_EL2; - } - break; - } - break; - case 5: - switch (crm) { - case 0: - switch (op2) { - case 0: - return MISCREG_FAR_EL12; - } - break; - } - break; - case 6: - switch (crm) { - case 0: - switch (op2) { - case 0: - return MISCREG_FAR_EL3; - } - break; - } - break; - } - break; - case 7: - switch (op1) { - case 0: - switch (crm) { - case 4: - switch (op2) { - case 0: - return MISCREG_PAR_EL1; - } - break; - } - break; - } - break; - case 9: - switch (op1) { - case 0: - switch (crm) { - case 14: - switch (op2) { - case 1: - return MISCREG_PMINTENSET_EL1; - case 2: - return MISCREG_PMINTENCLR_EL1; - } - break; - } - break; - case 3: - switch (crm) { - case 12: - switch (op2) { - case 0: - return MISCREG_PMCR_EL0; - case 1: - return MISCREG_PMCNTENSET_EL0; - case 2: - return MISCREG_PMCNTENCLR_EL0; - case 3: - return MISCREG_PMOVSCLR_EL0; - case 4: - return MISCREG_PMSWINC_EL0; - case 5: - return MISCREG_PMSELR_EL0; - case 6: - return MISCREG_PMCEID0_EL0; - case 7: - return MISCREG_PMCEID1_EL0; - } - break; - case 13: - switch (op2) { - case 0: - return MISCREG_PMCCNTR_EL0; - case 1: - return MISCREG_PMXEVTYPER_EL0; - case 2: - return MISCREG_PMXEVCNTR_EL0; - } - break; - case 14: - switch (op2) { - case 0: - return MISCREG_PMUSERENR_EL0; - case 3: - return MISCREG_PMOVSSET_EL0; - } - break; - } - break; - } - break; - case 10: - switch (op1) { - case 0: - switch (crm) { - case 2: - switch (op2) { - case 0: - return MISCREG_MAIR_EL1; - } - break; - case 3: - switch (op2) { - case 0: - return MISCREG_AMAIR_EL1; - } - break; - } - break; - case 4: - switch (crm) { - case 2: - switch (op2) { - case 0: - return MISCREG_MAIR_EL2; - } - break; - case 3: - switch (op2) { - case 0: - return MISCREG_AMAIR_EL2; - } - break; - } - break; - case 5: - switch (crm) { - case 2: - switch (op2) { - case 0: - return MISCREG_MAIR_EL12; - } - break; - case 3: - switch (op2) { - case 0: - return MISCREG_AMAIR_EL12; - } - break; - } - break; - case 6: - switch (crm) { - case 2: - switch (op2) { - case 0: - return MISCREG_MAIR_EL3; - } - break; - case 3: - switch (op2) { - case 0: - return MISCREG_AMAIR_EL3; - } - break; - } - break; - } - break; - case 11: - switch (op1) { - case 1: - switch (crm) { - case 0: - switch (op2) { - case 2: - return MISCREG_L2CTLR_EL1; - case 3: - return MISCREG_L2ECTLR_EL1; - } - break; - } - [[fallthrough]]; - default: - // S3__11__ - return MISCREG_IMPDEF_UNIMPL; - } - GEM5_UNREACHABLE; - case 12: - switch (op1) { - case 0: - switch (crm) { - case 0: - switch (op2) { - case 0: - return MISCREG_VBAR_EL1; - case 1: - return MISCREG_RVBAR_EL1; - } - break; - case 1: - switch (op2) { - case 0: - return MISCREG_ISR_EL1; - case 1: - return MISCREG_DISR_EL1; - } - break; - case 8: - switch (op2) { - case 0: - return MISCREG_ICC_IAR0_EL1; - case 1: - return MISCREG_ICC_EOIR0_EL1; - case 2: - return MISCREG_ICC_HPPIR0_EL1; - case 3: - return MISCREG_ICC_BPR0_EL1; - case 4: - return MISCREG_ICC_AP0R0_EL1; - case 5: - return MISCREG_ICC_AP0R1_EL1; - case 6: - return MISCREG_ICC_AP0R2_EL1; - case 7: - return MISCREG_ICC_AP0R3_EL1; - } - break; - case 9: - switch (op2) { - case 0: - return MISCREG_ICC_AP1R0_EL1; - case 1: - return MISCREG_ICC_AP1R1_EL1; - case 2: - return MISCREG_ICC_AP1R2_EL1; - case 3: - return MISCREG_ICC_AP1R3_EL1; - } - break; - case 11: - switch (op2) { - case 1: - return MISCREG_ICC_DIR_EL1; - case 3: - return MISCREG_ICC_RPR_EL1; - case 5: - return MISCREG_ICC_SGI1R_EL1; - case 6: - return MISCREG_ICC_ASGI1R_EL1; - case 7: - return MISCREG_ICC_SGI0R_EL1; - } - break; - case 12: - switch (op2) { - case 0: - return MISCREG_ICC_IAR1_EL1; - case 1: - return MISCREG_ICC_EOIR1_EL1; - case 2: - return MISCREG_ICC_HPPIR1_EL1; - case 3: - return MISCREG_ICC_BPR1_EL1; - case 4: - return MISCREG_ICC_CTLR_EL1; - case 5: - return MISCREG_ICC_SRE_EL1; - case 6: - return MISCREG_ICC_IGRPEN0_EL1; - case 7: - return MISCREG_ICC_IGRPEN1_EL1; - } - break; - } - break; - case 4: - switch (crm) { - case 0: - switch (op2) { - case 0: - return MISCREG_VBAR_EL2; - case 1: - return MISCREG_RVBAR_EL2; - } - break; - case 1: - switch (op2) { - case 1: - return MISCREG_VDISR_EL2; - } - break; - case 8: - switch (op2) { - case 0: - return MISCREG_ICH_AP0R0_EL2; - case 1: - return MISCREG_ICH_AP0R1_EL2; - case 2: - return MISCREG_ICH_AP0R2_EL2; - case 3: - return MISCREG_ICH_AP0R3_EL2; - } - break; - case 9: - switch (op2) { - case 0: - return MISCREG_ICH_AP1R0_EL2; - case 1: - return MISCREG_ICH_AP1R1_EL2; - case 2: - return MISCREG_ICH_AP1R2_EL2; - case 3: - return MISCREG_ICH_AP1R3_EL2; - case 5: - return MISCREG_ICC_SRE_EL2; - } - break; - case 11: - switch (op2) { - case 0: - return MISCREG_ICH_HCR_EL2; - case 1: - return MISCREG_ICH_VTR_EL2; - case 2: - return MISCREG_ICH_MISR_EL2; - case 3: - return MISCREG_ICH_EISR_EL2; - case 5: - return MISCREG_ICH_ELRSR_EL2; - case 7: - return MISCREG_ICH_VMCR_EL2; - } - break; - case 12: - switch (op2) { - case 0: - return MISCREG_ICH_LR0_EL2; - case 1: - return MISCREG_ICH_LR1_EL2; - case 2: - return MISCREG_ICH_LR2_EL2; - case 3: - return MISCREG_ICH_LR3_EL2; - case 4: - return MISCREG_ICH_LR4_EL2; - case 5: - return MISCREG_ICH_LR5_EL2; - case 6: - return MISCREG_ICH_LR6_EL2; - case 7: - return MISCREG_ICH_LR7_EL2; - } - break; - case 13: - switch (op2) { - case 0: - return MISCREG_ICH_LR8_EL2; - case 1: - return MISCREG_ICH_LR9_EL2; - case 2: - return MISCREG_ICH_LR10_EL2; - case 3: - return MISCREG_ICH_LR11_EL2; - case 4: - return MISCREG_ICH_LR12_EL2; - case 5: - return MISCREG_ICH_LR13_EL2; - case 6: - return MISCREG_ICH_LR14_EL2; - case 7: - return MISCREG_ICH_LR15_EL2; - } - break; - } - break; - case 5: - switch (crm) { - case 0: - switch (op2) { - case 0: - return MISCREG_VBAR_EL12; - } - break; - } - break; - case 6: - switch (crm) { - case 0: - switch (op2) { - case 0: - return MISCREG_VBAR_EL3; - case 1: - return MISCREG_RVBAR_EL3; - case 2: - return MISCREG_RMR_EL3; - } - break; - case 12: - switch (op2) { - case 4: - return MISCREG_ICC_CTLR_EL3; - case 5: - return MISCREG_ICC_SRE_EL3; - case 7: - return MISCREG_ICC_IGRPEN1_EL3; - } - break; - } - break; - } - break; - case 13: - switch (op1) { - case 0: - switch (crm) { - case 0: - switch (op2) { - case 1: - return MISCREG_CONTEXTIDR_EL1; - case 4: - return MISCREG_TPIDR_EL1; - } - break; - } - break; - case 3: - switch (crm) { - case 0: - switch (op2) { - case 2: - return MISCREG_TPIDR_EL0; - case 3: - return MISCREG_TPIDRRO_EL0; - } - break; - } - break; - case 4: - switch (crm) { - case 0: - switch (op2) { - case 1: - return MISCREG_CONTEXTIDR_EL2; - case 2: - return MISCREG_TPIDR_EL2; - } - break; - } - break; - case 5: - switch (crm) { - case 0: - switch (op2) { - case 1: - return MISCREG_CONTEXTIDR_EL12; - } - break; - } - break; - case 6: - switch (crm) { - case 0: - switch (op2) { - case 2: - return MISCREG_TPIDR_EL3; - } - break; - } - break; - } - break; - case 14: - switch (op1) { - case 0: - switch (crm) { - case 1: - switch (op2) { - case 0: - return MISCREG_CNTKCTL_EL1; - } - break; - } - break; - case 3: - switch (crm) { - case 0: - switch (op2) { - case 0: - return MISCREG_CNTFRQ_EL0; - case 1: - return MISCREG_CNTPCT_EL0; - case 2: - return MISCREG_CNTVCT_EL0; - } - break; - case 2: - switch (op2) { - case 0: - return MISCREG_CNTP_TVAL_EL0; - case 1: - return MISCREG_CNTP_CTL_EL0; - case 2: - return MISCREG_CNTP_CVAL_EL0; - } - break; - case 3: - switch (op2) { - case 0: - return MISCREG_CNTV_TVAL_EL0; - case 1: - return MISCREG_CNTV_CTL_EL0; - case 2: - return MISCREG_CNTV_CVAL_EL0; - } - break; - case 8: - switch (op2) { - case 0: - return MISCREG_PMEVCNTR0_EL0; - case 1: - return MISCREG_PMEVCNTR1_EL0; - case 2: - return MISCREG_PMEVCNTR2_EL0; - case 3: - return MISCREG_PMEVCNTR3_EL0; - case 4: - return MISCREG_PMEVCNTR4_EL0; - case 5: - return MISCREG_PMEVCNTR5_EL0; - } - break; - case 12: - switch (op2) { - case 0: - return MISCREG_PMEVTYPER0_EL0; - case 1: - return MISCREG_PMEVTYPER1_EL0; - case 2: - return MISCREG_PMEVTYPER2_EL0; - case 3: - return MISCREG_PMEVTYPER3_EL0; - case 4: - return MISCREG_PMEVTYPER4_EL0; - case 5: - return MISCREG_PMEVTYPER5_EL0; - } - break; - case 15: - switch (op2) { - case 7: - return MISCREG_PMCCFILTR_EL0; - } - } - break; - case 4: - switch (crm) { - case 0: - switch (op2) { - case 3: - return MISCREG_CNTVOFF_EL2; - } - break; - case 1: - switch (op2) { - case 0: - return MISCREG_CNTHCTL_EL2; - } - break; - case 2: - switch (op2) { - case 0: - return MISCREG_CNTHP_TVAL_EL2; - case 1: - return MISCREG_CNTHP_CTL_EL2; - case 2: - return MISCREG_CNTHP_CVAL_EL2; - } - break; - case 3: - switch (op2) { - case 0: - return MISCREG_CNTHV_TVAL_EL2; - case 1: - return MISCREG_CNTHV_CTL_EL2; - case 2: - return MISCREG_CNTHV_CVAL_EL2; - } - break; - } - break; - case 5: - switch (crm) { - case 1: - switch (op2) { - case 0: - return MISCREG_CNTKCTL_EL12; - } - break; - case 2: - switch (op2) { - case 0: - return MISCREG_CNTP_TVAL_EL02; - case 1: - return MISCREG_CNTP_CTL_EL02; - case 2: - return MISCREG_CNTP_CVAL_EL02; - } - break; - case 3: - switch (op2) { - case 0: - return MISCREG_CNTV_TVAL_EL02; - case 1: - return MISCREG_CNTV_CTL_EL02; - case 2: - return MISCREG_CNTV_CVAL_EL02; - } - break; - } - break; - case 7: - switch (crm) { - case 2: - switch (op2) { - case 0: - return MISCREG_CNTPS_TVAL_EL1; - case 1: - return MISCREG_CNTPS_CTL_EL1; - case 2: - return MISCREG_CNTPS_CVAL_EL1; - } - break; - } - break; - } - break; - case 15: - switch (op1) { - case 0: - switch (crm) { - case 0: - switch (op2) { - case 0: - return MISCREG_IL1DATA0_EL1; - case 1: - return MISCREG_IL1DATA1_EL1; - case 2: - return MISCREG_IL1DATA2_EL1; - case 3: - return MISCREG_IL1DATA3_EL1; - } - break; - case 1: - switch (op2) { - case 0: - return MISCREG_DL1DATA0_EL1; - case 1: - return MISCREG_DL1DATA1_EL1; - case 2: - return MISCREG_DL1DATA2_EL1; - case 3: - return MISCREG_DL1DATA3_EL1; - case 4: - return MISCREG_DL1DATA4_EL1; - } - break; - } - break; - case 1: - switch (crm) { - case 0: - switch (op2) { - case 0: - return MISCREG_L2ACTLR_EL1; - } - break; - case 2: - switch (op2) { - case 0: - return MISCREG_CPUACTLR_EL1; - case 1: - return MISCREG_CPUECTLR_EL1; - case 2: - return MISCREG_CPUMERRSR_EL1; - case 3: - return MISCREG_L2MERRSR_EL1; - } - break; - case 3: - switch (op2) { - case 0: - return MISCREG_CBAR_EL1; - - } - break; - } - break; - } - // S3__15__ - return MISCREG_IMPDEF_UNIMPL; - } - break; - } - - return MISCREG_UNKNOWN; -} - std::bitset miscRegInfo[NUM_MISCREGS]; // initialized below namespace { @@ -3874,6 +1928,25 @@ std::unordered_map miscRegNumToIdx{ } +MiscRegIndex +decodeAArch64SysReg(unsigned op0, unsigned op1, + unsigned crn, unsigned crm, + unsigned op2) +{ + MiscRegNum64 sys_reg(op0, op1, crn, crm, op2); + auto it = miscRegNumToIdx.find(sys_reg); + if (it != miscRegNumToIdx.end()) { + return it->second; + } else { + // Check for a pseudo register before returning MISCREG_UNKNOWN + if ((op0 == 1 || op0 == 3) && (crn == 11 || crn == 15)) { + return MISCREG_IMPDEF_UNIMPL; + } else { + return MISCREG_UNKNOWN; + } + } +} + void ISA::initializeMiscRegMetadata() {