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cpu: Use PCStateBase in the branch predictors.

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Use PCStateBase instead of TheISA::PCState in the branch predictors.

Change-Id: I0b0867bc09b6191a54d7658813c0b9656c436811
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52055
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Earl Ou <shunhsingou@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-10-14 02:41:50 -07:00
parent 732e0bfe9e
commit 8ef9f70fcb
12 changed files with 116 additions and 116 deletions
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10
src/cpu/minor/fetch2.cc
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@@ -156,7 +156,7 @@ Fetch2::updateBranchPrediction(const BranchData &branch)
/* Unpredicted branch or barrier */
DPRINTF(Branch, "Unpredicted branch seen inst: %s\n", *inst);
branchPredictor.squash(inst->id.fetchSeqNum,
branch.target->as<TheISA::PCState>(), true, inst->id.threadId);
*branch.target, true, inst->id.threadId);
// Update after squashing to accomodate O3CPU
// using the branch prediction code.
branchPredictor.update(inst->id.fetchSeqNum,
@@ -172,8 +172,7 @@ Fetch2::updateBranchPrediction(const BranchData &branch)
/* Predicted taken, not taken */
DPRINTF(Branch, "Branch mis-predicted inst: %s\n", *inst);
branchPredictor.squash(inst->id.fetchSeqNum,
branch.target->as<TheISA::PCState>() /* Not used */,
false, inst->id.threadId);
*branch.target /* Not used */, false, inst->id.threadId);
// Update after squashing to accomodate O3CPU
// using the branch prediction code.
branchPredictor.update(inst->id.fetchSeqNum,
@@ -184,7 +183,7 @@ Fetch2::updateBranchPrediction(const BranchData &branch)
DPRINTF(Branch, "Branch mis-predicted target inst: %s target: %s\n",
*inst, *branch.target);
branchPredictor.squash(inst->id.fetchSeqNum,
branch.target->as<TheISA::PCState>(), true, inst->id.threadId);
*branch.target, true, inst->id.threadId);
break;
}
}
@@ -206,8 +205,7 @@ Fetch2::predictBranch(MinorDynInstPtr inst, BranchData &branch)
DPRINTF(Branch, "Trying to predict for inst: %s\n", *inst);
if (branchPredictor.predict(inst->staticInst,
inst->id.fetchSeqNum, inst_pc->as<TheISA::PCState>(),
inst->id.threadId)) {
inst->id.fetchSeqNum, *inst_pc, inst->id.threadId)) {
set(branch.target, *inst_pc);
inst->predictedTaken = true;
set(inst->predictedTarget, inst_pc);