From 8e5e6030419eca0ed7bdf51c19d8fe315240b359 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Wed, 14 Apr 2021 12:52:26 +0100 Subject: [PATCH] misc: Fix VecPredReg coding style * get_bits -> getBits * set_bits -> setBits * set_raw -> setRaw * get_raw -> getRaw Change-Id: I57c0217dc399b7e1c5b007ed862d7ed221d5ac0b Signed-off-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44505 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- src/arch/arm/fastmodel/iris/thread_context.cc | 4 ++-- src/arch/arm/isa/insts/sve.isa | 8 ++++---- src/arch/generic/vec_pred_reg.hh | 12 ++++++------ 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/src/arch/arm/fastmodel/iris/thread_context.cc b/src/arch/arm/fastmodel/iris/thread_context.cc index 9567b11163..b2173e1a2e 100644 --- a/src/arch/arm/fastmodel/iris/thread_context.cc +++ b/src/arch/arm/fastmodel/iris/thread_context.cc @@ -693,13 +693,13 @@ ThreadContext::readVecPredReg(const RegId ®_id) const size_t num_bits = reg.NUM_BITS; uint8_t *bytes = (uint8_t *)result.data.data(); while (num_bits > 8) { - reg.set_bits(offset, 8, *bytes); + reg.setBits(offset, 8, *bytes); offset += 8; num_bits -= 8; bytes++; } if (num_bits) - reg.set_bits(offset, num_bits, *bytes); + reg.setBits(offset, num_bits, *bytes); return reg; } diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa index 03775ca9b2..8a4e724f6a 100644 --- a/src/arch/arm/isa/insts/sve.isa +++ b/src/arch/arm/isa/insts/sve.isa @@ -2623,7 +2623,7 @@ let {{ code +=''' const SElement& srcElem1 = auxPOp1[i];''' code += ''' - destPred.set_raw(i, 0); + destPred.setRaw(i, 0); PDest_xd[i] = srcElem1;''' else: if unpackHalf == Unpack.High: @@ -2836,8 +2836,8 @@ let {{ ArmISA::VecPredRegContainer tmpPredC; auto auxPOp1 = tmpPredC.as(); for (unsigned i = 0; i < eCount; ++i) { - uint8_t v = POp1_x.get_raw(i); - auxPOp1.set_raw(i, v); + uint8_t v = POp1_x.getRaw(i); + auxPOp1.setRaw(i, v); } PDest_x[0] = 0;''' else: @@ -2854,7 +2854,7 @@ let {{ AA64FpDest_x[i] = auxOp1[eCount - i - 1];''' else: code += ''' - destPred.set_raw(i, auxPOp1.get_raw(eCount - i - 1));''' + destPred.setRaw(i, auxPOp1.getRaw(eCount - i - 1));''' code += ''' }''' iop = ArmInstObjParams(name, 'Sve' + Name, 'SveUnaryUnpredOp', diff --git a/src/arch/generic/vec_pred_reg.hh b/src/arch/generic/vec_pred_reg.hh index b238357f4b..46f6f2ff61 100644 --- a/src/arch/generic/vec_pred_reg.hh +++ b/src/arch/generic/vec_pred_reg.hh @@ -118,18 +118,18 @@ class VecPredRegT /// Return an element of the predicate register as it appears /// in the raw (untyped) internal representation uint8_t - get_raw(size_t idx) const + getRaw(size_t idx) const { - return container.get_bits(idx * (Packed ? 1 : sizeof(VecElem)), + return container.getBits(idx * (Packed ? 1 : sizeof(VecElem)), (Packed ? 1 : sizeof(VecElem))); } /// Write a raw value in an element of the predicate register template std::enable_if_t - set_raw(size_t idx, uint8_t val) + setRaw(size_t idx, uint8_t val) { - container.set_bits(idx * (Packed ? 1 : sizeof(VecElem)), + container.setBits(idx * (Packed ? 1 : sizeof(VecElem)), (Packed ? 1 : sizeof(VecElem)), val); } @@ -302,7 +302,7 @@ class VecPredRegContainer /// Returns a subset of bits starting from a specific element in the /// container. uint8_t - get_bits(size_t idx, uint8_t nbits) const + getBits(size_t idx, uint8_t nbits) const { assert(nbits > 0 && nbits <= 8 && (idx + nbits - 1) < NumBits); uint8_t v = 0; @@ -317,7 +317,7 @@ class VecPredRegContainer /// Set a subset of bits starting from a specific element in the /// container. void - set_bits(size_t idx, uint8_t nbits, uint8_t bval) + setBits(size_t idx, uint8_t nbits, uint8_t bval) { assert(nbits > 0 && nbits <= 8 && (idx + nbits - 1) < NumBits); for (int i = 0; i < nbits; ++i, ++idx) {