From 8dffadf4e4247620c6cbcf454619eb9ef5b9045e Mon Sep 17 00:00:00 2001
From: Hoa Nguyen <hoanguyen@ucdavis.edu>
Date: Fri, 30 Jul 2021 15:44:31 -0700
Subject: [PATCH] arch-riscv: Fix illegal instruction error message

Previously, the reason for the fault was not printed to the output.

Change-Id: I931b0de96fbb241f24ba69ad7e84d5d1c9db9e60
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48923
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---
 src/arch/riscv/faults.hh | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/arch/riscv/faults.hh b/src/arch/riscv/faults.hh
index 38c56389d1..a8df3f50fe 100644
--- a/src/arch/riscv/faults.hh
+++ b/src/arch/riscv/faults.hh
@@ -166,7 +166,8 @@ class IllegalInstFault : public InstFault
 
   public:
     IllegalInstFault(std::string r, const ExtMachInst inst)
-        : InstFault("Illegal instruction", inst)
+        : InstFault("Illegal instruction", inst),
+          reason(r)
     {}
 
     void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;