Changed Fault * to Fault, which is a typedef to FaultBase *, which is the old Fault class renamed.

--HG--
extra : convert_revision : 5b2f457401f8ff94fe39fe071288eb117814b7bb

dev/alpha_console.cc

@@ -100,7 +100,7 @@ AlphaConsole::startup()
     alphaAccess->intrClockFrequency = platform->intrFrequency();
 }
 
-Fault *
+Fault
 AlphaConsole::read(MemReqPtr &req, uint8_t *data)
 {
     memset(data, 0, req->size);
@@ -190,7 +190,7 @@ AlphaConsole::read(MemReqPtr &req, uint8_t *data)
     return NoFault;
 }
 
-Fault *
+Fault
 AlphaConsole::write(MemReqPtr &req, const uint8_t *data)
 {
     uint64_t val;

dev/alpha_console.hh

@@ -110,8 +110,8 @@ class AlphaConsole : public PioDevice
     /**
      * memory mapped reads and writes
      */
-    virtual Fault * read(MemReqPtr &req, uint8_t *data);
-    virtual Fault * write(MemReqPtr &req, const uint8_t *data);
+    virtual Fault read(MemReqPtr &req, uint8_t *data);
+    virtual Fault write(MemReqPtr &req, const uint8_t *data);
 
     /**
      * standard serialization routines for checkpointing

dev/baddev.cc

@@ -62,7 +62,7 @@ BadDevice::BadDevice(const string &name, Addr a, MemoryController *mmu,
 
 }
 
-Fault *
+Fault
 BadDevice::read(MemReqPtr &req, uint8_t *data)
 {
 
@@ -70,7 +70,7 @@ BadDevice::read(MemReqPtr &req, uint8_t *data)
     return NoFault;
 }
 
-Fault *
+Fault
 BadDevice::write(MemReqPtr &req, const uint8_t *data)
 {
     panic("Device %s not imlpmented\n", devname);

dev/baddev.hh

@@ -71,7 +71,7 @@ class BadDevice : public PioDevice
       * @param data A pointer to write the read data to.
       * @return The fault condition of the access.
       */
-    virtual Fault * read(MemReqPtr &req, uint8_t *data);
+    virtual Fault read(MemReqPtr &req, uint8_t *data);
 
     /**
       * On a write event we just panic aand hopefully print a
@@ -80,7 +80,7 @@ class BadDevice : public PioDevice
       * @param data The data to write.
       * @return The fault condition of the access.
       */
-    virtual Fault * write(MemReqPtr &req, const uint8_t *data);
+    virtual Fault write(MemReqPtr &req, const uint8_t *data);
 
     /**
      * Return how long this access will take.

dev/ide_ctrl.cc

@@ -391,7 +391,7 @@ IdeController::writeConfig(int offset, int size, const uint8_t *data)
     }
 }
 
-Fault *
+Fault
 IdeController::read(MemReqPtr &req, uint8_t *data)
 {
     Addr offset;
@@ -461,7 +461,7 @@ IdeController::read(MemReqPtr &req, uint8_t *data)
     return NoFault;
 }
 
-Fault *
+Fault
 IdeController::write(MemReqPtr &req, const uint8_t *data)
 {
     Addr offset;

dev/ide_ctrl.hh

@@ -213,7 +213,7 @@ class IdeController : public PciDev
      * @param data Return the field read.
      * @return The fault condition of the access.
      */
-    virtual Fault * read(MemReqPtr &req, uint8_t *data);
+    virtual Fault read(MemReqPtr &req, uint8_t *data);
 
     /**
      * Write to the mmapped I/O control registers.
@@ -221,7 +221,7 @@ class IdeController : public PciDev
      * @param data The data to write.
      * @return The fault condition of the access.
      */
-    virtual Fault * write(MemReqPtr &req, const uint8_t *data);
+    virtual Fault write(MemReqPtr &req, const uint8_t *data);
 
     /**
      * Serialize this object to the given output stream.

dev/isa_fake.cc

@@ -60,7 +60,7 @@ IsaFake::IsaFake(const string &name, Addr a, MemoryController *mmu,
     }
 }
 
-Fault *
+Fault
 IsaFake::read(MemReqPtr &req, uint8_t *data)
 {
     DPRINTF(Tsunami, "read  va=%#x size=%d\n",
@@ -93,7 +93,7 @@ IsaFake::read(MemReqPtr &req, uint8_t *data)
     return NoFault;
 }
 
-Fault *
+Fault
 IsaFake::write(MemReqPtr &req, const uint8_t *data)
 {
     DPRINTF(Tsunami, "write - va=%#x size=%d \n",

dev/isa_fake.hh

@@ -65,14 +65,14 @@ class IsaFake : public PioDevice
      * @param req The memory request.
      * @param data Where to put the data.
      */
-    virtual Fault * read(MemReqPtr &req, uint8_t *data);
+    virtual Fault read(MemReqPtr &req, uint8_t *data);
 
     /**
      * All writes are simply ignored.
      * @param req The memory request.
      * @param data the data to not write.
      */
-    virtual Fault * write(MemReqPtr &req, const uint8_t *data);
+    virtual Fault write(MemReqPtr &req, const uint8_t *data);
 
     /**
      * Return how long this access will take.

dev/ns_gige.cc

@@ -557,7 +557,7 @@ NSGigE::writeConfig(int offset, int size, const uint8_t* data)
  * This reads the device registers, which are detailed in the NS83820
  * spec sheet
  */
-Fault *
+Fault
 NSGigE::read(MemReqPtr &req, uint8_t *data)
 {
     assert(ioEnable);
@@ -786,7 +786,7 @@ NSGigE::read(MemReqPtr &req, uint8_t *data)
     return NoFault;
 }
 
-Fault *
+Fault
 NSGigE::write(MemReqPtr &req, const uint8_t *data)
 {
     assert(ioEnable);

dev/ns_gige.hh

@@ -395,8 +395,8 @@ class NSGigE : public PciDev
     virtual void writeConfig(int offset, int size, const uint8_t *data);
     virtual void readConfig(int offset, int size, uint8_t *data);
 
-    virtual Fault * read(MemReqPtr &req, uint8_t *data);
-    virtual Fault * write(MemReqPtr &req, const uint8_t *data);
+    virtual Fault read(MemReqPtr &req, uint8_t *data);
+    virtual Fault write(MemReqPtr &req, const uint8_t *data);
 
     bool cpuIntrPending() const;
     void cpuIntrAck() { cpuIntrClear(); }

dev/pciconfigall.cc

@@ -96,7 +96,7 @@ PciConfigAll::startup()
 
 }
 
-Fault *
+Fault
 PciConfigAll::read(MemReqPtr &req, uint8_t *data)
 {
 
@@ -144,7 +144,7 @@ PciConfigAll::read(MemReqPtr &req, uint8_t *data)
     return NoFault;
 }
 
-Fault *
+Fault
 PciConfigAll::write(MemReqPtr &req, const uint8_t *data)
 {
     Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask));

dev/pciconfigall.hh

@@ -103,7 +103,7 @@ class PciConfigAll : public PioDevice
      * @param data Return the field read.
      * @return The fault condition of the access.
      */
-    virtual Fault * read(MemReqPtr &req, uint8_t *data);
+    virtual Fault read(MemReqPtr &req, uint8_t *data);
 
     /**
      * Write to PCI config spcae. If the device does not exit the simulator
@@ -114,7 +114,7 @@ class PciConfigAll : public PioDevice
      * @return The fault condition of the access.
      */
 
-    virtual Fault * write(MemReqPtr &req, const uint8_t *data);
+    virtual Fault write(MemReqPtr &req, const uint8_t *data);
 
     /**
      * Start up function to check if more than one person is using an interrupt line

dev/pcidev.cc

@@ -70,59 +70,59 @@ PciDev::PciDev(Params *p)
         p->configSpace->registerDevice(p->deviceNum, p->functionNum, this);
 }
 
-Fault *
+Fault
 PciDev::read(MemReqPtr &req, uint8_t *data)
 { return NoFault; }
 
-Fault *
+Fault
 PciDev::write(MemReqPtr &req, const uint8_t *data)
 { return NoFault; }
 
-Fault *
+Fault
 PciDev::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data)
 { panic("not implemented"); }
 
-Fault *
+Fault
 PciDev::readBar1(MemReqPtr &req, Addr daddr, uint8_t *data)
 { panic("not implemented"); }
 
-Fault *
+Fault
 PciDev::readBar2(MemReqPtr &req, Addr daddr, uint8_t *data)
 { panic("not implemented"); }
 
-Fault *
+Fault
 PciDev::readBar3(MemReqPtr &req, Addr daddr, uint8_t *data)
 { panic("not implemented"); }
 
-Fault *
+Fault
 PciDev::readBar4(MemReqPtr &req, Addr daddr, uint8_t *data)
 { panic("not implemented"); }
 
-Fault *
+Fault
 PciDev::readBar5(MemReqPtr &req, Addr daddr, uint8_t *data)
 { panic("not implemented"); }
 
-Fault *
+Fault
 PciDev::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data)
 { panic("not implemented"); }
 
-Fault *
+Fault
 PciDev::writeBar1(MemReqPtr &req, Addr daddr, const uint8_t *data)
 { panic("not implemented"); }
 
-Fault *
+Fault
 PciDev::writeBar2(MemReqPtr &req, Addr daddr, const uint8_t *data)
 { panic("not implemented"); }
 
-Fault *
+Fault
 PciDev::writeBar3(MemReqPtr &req, Addr daddr, const uint8_t *data)
 { panic("not implemented"); }
 
-Fault *
+Fault
 PciDev::writeBar4(MemReqPtr &req, Addr daddr, const uint8_t *data)
 { panic("not implemented"); }
 
-Fault *
+Fault
 PciDev::writeBar5(MemReqPtr &req, Addr daddr, const uint8_t *data)
 { panic("not implemented"); }
 

dev/pcidev.hh

@@ -189,37 +189,37 @@ class PciDev : public DmaDevice
      */
     PciDev(Params *params);
 
-    virtual Fault * read(MemReqPtr &req, uint8_t *data);
-    virtual Fault * write(MemReqPtr &req, const uint8_t *data);
+    virtual Fault read(MemReqPtr &req, uint8_t *data);
+    virtual Fault write(MemReqPtr &req, const uint8_t *data);
 
   public:
     /**
      * Implement the read/write as BAR accesses
      */
-    Fault * readBar(MemReqPtr &req, uint8_t *data);
-    Fault * writeBar(MemReqPtr &req, const uint8_t *data);
+    Fault readBar(MemReqPtr &req, uint8_t *data);
+    Fault writeBar(MemReqPtr &req, const uint8_t *data);
 
   public:
     /**
      * Read from a specific BAR
      */
-    virtual Fault * readBar0(MemReqPtr &req, Addr daddr, uint8_t *data);
-    virtual Fault * readBar1(MemReqPtr &req, Addr daddr, uint8_t *data);
-    virtual Fault * readBar2(MemReqPtr &req, Addr daddr, uint8_t *data);
-    virtual Fault * readBar3(MemReqPtr &req, Addr daddr, uint8_t *data);
-    virtual Fault * readBar4(MemReqPtr &req, Addr daddr, uint8_t *data);
-    virtual Fault * readBar5(MemReqPtr &req, Addr daddr, uint8_t *data);
+    virtual Fault readBar0(MemReqPtr &req, Addr daddr, uint8_t *data);
+    virtual Fault readBar1(MemReqPtr &req, Addr daddr, uint8_t *data);
+    virtual Fault readBar2(MemReqPtr &req, Addr daddr, uint8_t *data);
+    virtual Fault readBar3(MemReqPtr &req, Addr daddr, uint8_t *data);
+    virtual Fault readBar4(MemReqPtr &req, Addr daddr, uint8_t *data);
+    virtual Fault readBar5(MemReqPtr &req, Addr daddr, uint8_t *data);
 
   public:
     /**
      * Write to a specific BAR
      */
-    virtual Fault * writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data);
-    virtual Fault * writeBar1(MemReqPtr &req, Addr daddr, const uint8_t *data);
-    virtual Fault * writeBar2(MemReqPtr &req, Addr daddr, const uint8_t *data);
-    virtual Fault * writeBar3(MemReqPtr &req, Addr daddr, const uint8_t *data);
-    virtual Fault * writeBar4(MemReqPtr &req, Addr daddr, const uint8_t *data);
-    virtual Fault * writeBar5(MemReqPtr &req, Addr daddr, const uint8_t *data);
+    virtual Fault writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data);
+    virtual Fault writeBar1(MemReqPtr &req, Addr daddr, const uint8_t *data);
+    virtual Fault writeBar2(MemReqPtr &req, Addr daddr, const uint8_t *data);
+    virtual Fault writeBar3(MemReqPtr &req, Addr daddr, const uint8_t *data);
+    virtual Fault writeBar4(MemReqPtr &req, Addr daddr, const uint8_t *data);
+    virtual Fault writeBar5(MemReqPtr &req, Addr daddr, const uint8_t *data);
 
   public:
     /**
@@ -257,7 +257,7 @@ class PciDev : public DmaDevice
     virtual void unserialize(Checkpoint *cp, const std::string &section);
 };
 
-inline Fault *
+inline Fault
 PciDev::readBar(MemReqPtr &req, uint8_t *data)
 {
     if (isBAR(req->paddr, 0))
@@ -275,7 +275,7 @@ PciDev::readBar(MemReqPtr &req, uint8_t *data)
     return MachineCheckFault;
 }
 
-inline Fault *
+inline Fault
 PciDev::writeBar(MemReqPtr &req, const uint8_t *data)
 {
     if (isBAR(req->paddr, 0))

dev/sinic.cc

@@ -357,11 +357,11 @@ Device::prepareWrite(int cpu, int index)
 /**
  * I/O read of device register
  */
-Fault *
+Fault
 Device::read(MemReqPtr &req, uint8_t *data)
 {
     assert(config.command & PCI_CMD_MSE);
-    Fault * fault = readBar(req, data);
+    Fault fault = readBar(req, data);
 
     if (fault == MachineCheckFault) {
         panic("address does not map to a BAR pa=%#x va=%#x size=%d",
@@ -373,7 +373,7 @@ Device::read(MemReqPtr &req, uint8_t *data)
     return fault;
 }
 
-Fault *
+Fault
 Device::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data)
 {
     int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff;
@@ -423,7 +423,7 @@ Device::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data)
 /**
  * IPR read of device register
  */
-Fault *
+Fault
 Device::iprRead(Addr daddr, int cpu, uint64_t &result)
 {
     if (!regValid(daddr))
@@ -453,11 +453,11 @@ Device::iprRead(Addr daddr, int cpu, uint64_t &result)
 /**
  * I/O write of device register
  */
-Fault *
+Fault
 Device::write(MemReqPtr &req, const uint8_t *data)
 {
     assert(config.command & PCI_CMD_MSE);
-    Fault * fault = writeBar(req, data);
+    Fault fault = writeBar(req, data);
 
     if (fault == MachineCheckFault) {
         panic("address does not map to a BAR pa=%#x va=%#x size=%d",
@@ -469,7 +469,7 @@ Device::write(MemReqPtr &req, const uint8_t *data)
     return fault;
 }
 
-Fault *
+Fault
 Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data)
 {
     int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff;

dev/sinic.hh

@@ -271,15 +271,15 @@ class Device : public Base
  * Memory Interface
  */
   public:
-    virtual Fault * read(MemReqPtr &req, uint8_t *data);
-    virtual Fault * write(MemReqPtr &req, const uint8_t *data);
+    virtual Fault read(MemReqPtr &req, uint8_t *data);
+    virtual Fault write(MemReqPtr &req, const uint8_t *data);
 
     void prepareIO(int cpu, int index);
     void prepareRead(int cpu, int index);
     void prepareWrite(int cpu, int index);
-    Fault * iprRead(Addr daddr, int cpu, uint64_t &result);
-    Fault * readBar0(MemReqPtr &req, Addr daddr, uint8_t *data);
-    Fault * writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data);
+    Fault iprRead(Addr daddr, int cpu, uint64_t &result);
+    Fault readBar0(MemReqPtr &req, Addr daddr, uint8_t *data);
+    Fault writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data);
     void regWrite(Addr daddr, int cpu, const uint8_t *data);
     Tick cacheAccess(MemReqPtr &req);
 

dev/tsunami_cchip.cc

@@ -78,7 +78,7 @@ TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a,
     tsunami->cchip = this;
 }
 
-Fault *
+Fault
 TsunamiCChip::read(MemReqPtr &req, uint8_t *data)
 {
     DPRINTF(Tsunami, "read  va=%#x size=%d\n", req->vaddr, req->size);
@@ -192,7 +192,7 @@ TsunamiCChip::read(MemReqPtr &req, uint8_t *data)
     return NoFault;
 }
 
-Fault *
+Fault
 TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
 {
     DPRINTF(Tsunami, "write - va=%#x value=%#x size=%d \n",

dev/tsunami_cchip.hh

@@ -105,7 +105,7 @@ class TsunamiCChip : public PioDevice
       * @param data A pointer to write the read data to.
       * @return The fault condition of the access.
       */
-    virtual Fault * read(MemReqPtr &req, uint8_t *data);
+    virtual Fault read(MemReqPtr &req, uint8_t *data);
 
 
     /**
@@ -114,7 +114,7 @@ class TsunamiCChip : public PioDevice
       * @param data The data to write.
       * @return The fault condition of the access.
       */
-    virtual Fault * write(MemReqPtr &req, const uint8_t *data);
+    virtual Fault write(MemReqPtr &req, const uint8_t *data);
 
     /**
      * post an RTC interrupt to the CPU

dev/tsunami_io.cc

@@ -446,7 +446,7 @@ TsunamiIO::frequency() const
     return Clock::Frequency / clockInterval;
 }
 
-Fault *
+Fault
 TsunamiIO::read(MemReqPtr &req, uint8_t *data)
 {
     DPRINTF(Tsunami, "io read  va=%#x size=%d IOPorrt=%#x\n",
@@ -523,7 +523,7 @@ TsunamiIO::read(MemReqPtr &req, uint8_t *data)
     return NoFault;
 }
 
-Fault *
+Fault
 TsunamiIO::write(MemReqPtr &req, const uint8_t *data)
 {
 

dev/tsunami_io.hh

@@ -330,7 +330,7 @@ class TsunamiIO : public PioDevice
       * @param data A pointer to write the read data to.
       * @return The fault condition of the access.
       */
-    virtual Fault * read(MemReqPtr &req, uint8_t *data);
+    virtual Fault read(MemReqPtr &req, uint8_t *data);
 
     /**
       * Process a write to one of the devices we emulate.
@@ -338,7 +338,7 @@ class TsunamiIO : public PioDevice
       * @param data The data to write.
       * @return The fault condition of the access.
       */
-    virtual Fault * write(MemReqPtr &req, const uint8_t *data);
+    virtual Fault write(MemReqPtr &req, const uint8_t *data);
 
     /**
      * Post an PIC interrupt to the CPU via the CChip

dev/tsunami_pchip.cc

@@ -78,7 +78,7 @@ TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a,
     tsunami->pchip = this;
 }
 
-Fault *
+Fault
 TsunamiPChip::read(MemReqPtr &req, uint8_t *data)
 {
     DPRINTF(Tsunami, "read  va=%#x size=%d\n",
@@ -167,7 +167,7 @@ TsunamiPChip::read(MemReqPtr &req, uint8_t *data)
     return NoFault;
 }
 
-Fault *
+Fault
 TsunamiPChip::write(MemReqPtr &req, const uint8_t *data)
 {
     DPRINTF(Tsunami, "write - va=%#x size=%d \n",

dev/tsunami_pchip.hh

@@ -99,7 +99,7 @@ class TsunamiPChip : public PioDevice
       * @param data A pointer to write the read data to.
       * @return The fault condition of the access.
       */
-    virtual Fault * read(MemReqPtr &req, uint8_t *data);
+    virtual Fault read(MemReqPtr &req, uint8_t *data);
 
     /**
       * Process a write to the PChip.
@@ -107,7 +107,7 @@ class TsunamiPChip : public PioDevice
       * @param data The data to write.
       * @return The fault condition of the access.
       */
-    virtual Fault * write(MemReqPtr &req, const uint8_t *data);
+    virtual Fault write(MemReqPtr &req, const uint8_t *data);
 
     /**
      * Serialize this object to the given output stream.

dev/uart.hh

@@ -57,8 +57,8 @@ class Uart : public PioDevice
          Addr a, Addr s, HierParams *hier, Bus *bus, Tick pio_latency,
          Platform *p);
 
-    virtual Fault * read(MemReqPtr &req, uint8_t *data) = 0;
-    virtual Fault * write(MemReqPtr &req, const uint8_t *data) = 0;
+    virtual Fault read(MemReqPtr &req, uint8_t *data) = 0;
+    virtual Fault write(MemReqPtr &req, const uint8_t *data) = 0;
 
 
     /**

dev/uart8250.cc

@@ -112,7 +112,7 @@ Uart8250::Uart8250(const string &name, SimConsole *c, MemoryController *mmu,
 
 }
 
-Fault *
+Fault
 Uart8250::read(MemReqPtr &req, uint8_t *data)
 {
     Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
@@ -188,7 +188,7 @@ Uart8250::read(MemReqPtr &req, uint8_t *data)
 
 }
 
-Fault *
+Fault
 Uart8250::write(MemReqPtr &req, const uint8_t *data)
 {
     Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);

dev/uart8250.hh

@@ -82,8 +82,8 @@ class Uart8250 : public Uart
          Addr a, Addr s, HierParams *hier, Bus *pio_bus, Tick pio_latency,
          Platform *p);
 
-    virtual Fault * read(MemReqPtr &req, uint8_t *data);
-    virtual Fault * write(MemReqPtr &req, const uint8_t *data);
+    virtual Fault read(MemReqPtr &req, uint8_t *data);
+    virtual Fault write(MemReqPtr &req, const uint8_t *data);
 
 
     /**