From 8c4d5f8e27c81551f2ed5cb88f06bc73e1f05404 Mon Sep 17 00:00:00 2001
From: Chong-Teng Wang <78740113+QQeg@users.noreply.github.com>
Date: Fri, 10 May 2024 01:17:15 +0800
Subject: [PATCH] arch-riscv: Fix narrowing/widening type-convert instructions
 (#1079)

Correct ei calculation under VectorFloatWideningCvtFormat and
VectorFloatNarrowingCvtFormat.

Change-Id: I08699ffe3b9f8a7d4543023437626cc054344053
---
 src/arch/riscv/isa/formats/vector_arith.isa | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/arch/riscv/isa/formats/vector_arith.isa b/src/arch/riscv/isa/formats/vector_arith.isa
index 0a4acd3db9..3d8afc5bda 100644
--- a/src/arch/riscv/isa/formats/vector_arith.isa
+++ b/src/arch/riscv/isa/formats/vector_arith.isa
@@ -801,7 +801,7 @@ def format VectorFloatWideningCvtFormat(code, category, *flags) {{
     set_src_reg_idx += setSrcWrapper(src3_reg_id)
     set_src_reg_idx += setSrcVm()
     code = maskCondWrapper(code)
-    code = eiDeclarePrefix(code)
+    code = eiDeclarePrefix(code, widening=True)
     code = loopWrapper(code)
     code = fflags_wrapper(code)
 
@@ -858,7 +858,7 @@ def format VectorFloatNarrowingCvtFormat(code, category, *flags) {{
     set_src_reg_idx += setSrcWrapper(src3_reg_id)
     set_src_reg_idx += setSrcVm()
     code = maskCondWrapper(code)
-    code = eiDeclarePrefix(code)
+    code = eiDeclarePrefix(code, widening=True)
     code = loopWrapper(code)
     code = fflags_wrapper(code)
     code = narrowingOpRegisterConstraintChecks(code)