tests: update stats for name changes
This commit is contained in:
Nathan Binkert
@@ -145,6 +145,7 @@ deadlock_threshold=500000
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icache=system.l1_cntrl0.L1IcacheMemory
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max_outstanding_requests=16
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physmem=system.physmem
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using_network_tester=false
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using_ruby_tester=true
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version=0
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physMemPort=system.physmem.port[0]
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@@ -230,6 +231,7 @@ warmup_length=100000
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[system.tester]
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type=RubyTester
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check_flush=false
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checks_to_complete=100
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deadlock_threshold=50000
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wakeup_frequency=10
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@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
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================ End RubySystem Configuration Print ================
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Real time: Feb/08/2011 17:31:55
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Real time: Apr/19/2011 12:12:40
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Profiler Stats
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--------------
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@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
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Elapsed_time_in_hours: 0
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Elapsed_time_in_days: 0
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Virtual_time_in_seconds: 0.79
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Virtual_time_in_minutes: 0.0131667
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Virtual_time_in_hours: 0.000219444
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Virtual_time_in_days: 9.14352e-06
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Virtual_time_in_seconds: 0.36
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Virtual_time_in_minutes: 0.006
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Virtual_time_in_hours: 0.0001
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Virtual_time_in_days: 4.16667e-06
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Ruby_current_time: 352261
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Ruby_start_time: 0
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Ruby_cycles: 352261
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mbytes_resident: 33.6719
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mbytes_total: 208.004
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resident_ratio: 0.161956
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mbytes_resident: 35.7031
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mbytes_total: 206.043
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resident_ratio: 0.173299
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ruby_cycles_executed: [ 352262 ]
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@@ -71,9 +71,9 @@ sequencer_requests_outstanding: [binsize: 1 max: 16 count: 986 average: 15.8337
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All Non-Zero Cycle Demand Cache Accesses
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----------------------------------------
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miss_latency: [binsize: 256 max: 33636 count: 971 average: 5617.58 | standard deviation: 7479.54 | 86 25 67 61 60 60 59 49 37 31 22 33 21 30 13 6 17 12 14 11 11 7 4 2 6 3 6 6 4 2 3 2 4 4 1 1 2 1 0 1 0 1 2 1 0 1 1 0 2 5 0 3 0 1 0 3 2 5 3 5 2 2 4 3 6 4 3 3 2 4 2 4 3 4 5 7 1 2 5 5 5 4 0 3 2 8 5 5 2 7 2 2 4 1 2 1 0 2 3 2 2 1 0 0 3 2 2 2 0 1 0 0 0 0 1 0 1 0 0 0 0 2 0 1 0 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_IFETCH: [binsize: 16 max: 2135 count: 46 average: 937.935 | standard deviation: 408.53 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 2 0 0 0 0 1 1 1 0 0 2 0 1 0 0 1 0 0 0 3 3 1 0 0 0 0 2 1 1 1 0 0 2 0 0 3 0 1 2 0 0 0 0 0 0 1 2 1 0 3 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_LD: [binsize: 256 max: 26910 count: 54 average: 5436.72 | standard deviation: 7279.79 | 4 1 3 3 5 5 2 1 3 1 2 5 1 2 1 1 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_ST: [binsize: 256 max: 33636 count: 871 average: 5875.94 | standard deviation: 7609.86 | 82 18 51 47 46 53 53 48 33 30 20 28 20 28 12 5 16 12 14 11 11 6 4 2 6 3 5 6 4 2 3 2 4 4 1 1 2 1 0 1 0 1 1 1 0 1 1 0 2 5 0 3 0 1 0 3 2 5 2 5 1 1 4 3 6 3 3 3 2 3 2 4 3 3 5 7 1 2 5 5 5 4 0 3 2 8 5 5 1 7 1 2 4 1 1 1 0 2 3 2 2 1 0 0 3 1 2 2 0 1 0 0 0 0 1 0 1 0 0 0 0 2 0 1 0 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_IFETCH: [binsize: 16 max: 2135 count: 46 average: 937.935 | standard deviation: 408.53 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 2 0 0 0 0 1 1 1 0 0 2 0 1 0 0 1 0 0 0 3 3 1 0 0 0 0 2 1 1 1 0 0 2 0 0 3 0 1 2 0 0 0 0 0 0 1 2 1 0 3 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_NULL: [binsize: 256 max: 33636 count: 971 average: 5617.58 | standard deviation: 7479.54 | 86 25 67 61 60 60 59 49 37 31 22 33 21 30 13 6 17 12 14 11 11 7 4 2 6 3 6 6 4 2 3 2 4 4 1 1 2 1 0 1 0 1 2 1 0 1 1 0 2 5 0 3 0 1 0 3 2 5 3 5 2 2 4 3 6 4 3 3 2 4 2 4 3 4 5 7 1 2 5 5 5 4 0 3 2 8 5 5 2 7 2 2 4 1 2 1 0 2 3 2 2 1 0 0 3 2 2 2 0 1 0 0 0 0 1 0 1 0 0 0 0 2 0 1 0 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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@@ -85,9 +85,9 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: N
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miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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imcomplete_dir_Times: 0
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miss_latency_IFETCH_NULL: [binsize: 16 max: 2135 count: 46 average: 937.935 | standard deviation: 408.53 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 2 0 0 0 0 1 1 1 0 0 2 0 1 0 0 1 0 0 0 3 3 1 0 0 0 0 2 1 1 1 0 0 2 0 0 3 0 1 2 0 0 0 0 0 0 1 2 1 0 3 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_LD_NULL: [binsize: 256 max: 26910 count: 54 average: 5436.72 | standard deviation: 7279.79 | 4 1 3 3 5 5 2 1 3 1 2 5 1 2 1 1 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_ST_NULL: [binsize: 256 max: 33636 count: 871 average: 5875.94 | standard deviation: 7609.86 | 82 18 51 47 46 53 53 48 33 30 20 28 20 28 12 5 16 12 14 11 11 6 4 2 6 3 5 6 4 2 3 2 4 4 1 1 2 1 0 1 0 1 1 1 0 1 1 0 2 5 0 3 0 1 0 3 2 5 2 5 1 1 4 3 6 3 3 3 2 3 2 4 3 3 5 7 1 2 5 5 5 4 0 3 2 8 5 5 1 7 1 2 4 1 1 1 0 2 3 2 2 1 0 0 3 1 2 2 0 1 0 0 0 0 1 0 1 0 0 0 0 2 0 1 0 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_IFETCH_NULL: [binsize: 16 max: 2135 count: 46 average: 937.935 | standard deviation: 408.53 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 2 0 0 0 0 1 1 1 0 0 2 0 1 0 0 1 0 0 0 3 3 1 0 0 0 0 2 1 1 1 0 0 2 0 0 3 0 1 2 0 0 0 0 0 0 1 2 1 0 3 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ]
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All Non-Zero Cycle SW Prefetch Requests
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------------------------------------
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@@ -119,11 +119,11 @@ Resource Usage
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page_size: 4096
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user_time: 0
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system_time: 0
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page_reclaims: 9831
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page_reclaims: 9430
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page_faults: 0
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swaps: 0
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block_inputs: 0
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block_outputs: 0
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block_outputs: 48
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Network Stats
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-------------
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@@ -5,10 +5,9 @@ The Regents of The University of Michigan
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All Rights Reserved
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M5 compiled Feb 8 2011 17:31:51
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M5 revision 685719afafe6 7938 default tip brad/increase_ruby_mem_test_threshold qtip
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M5 started Feb 8 2011 17:31:55
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M5 executing on SC2B0617
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M5 compiled Apr 19 2011 12:12:36
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M5 started Apr 19 2011 12:12:40
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M5 executing on maize
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command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory
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Global frequency set at 1000000000 ticks per second
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info: Entering event queue @ 0. Starting simulation...
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@@ -1,8 +1,8 @@
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---------- Begin Simulation Statistics ----------
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host_mem_usage 213000 # Number of bytes of host memory used
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host_seconds 0.47 # Real time elapsed on the host
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host_tick_rate 753338 # Simulator tick rate (ticks/s)
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host_mem_usage 210992 # Number of bytes of host memory used
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host_seconds 0.25 # Real time elapsed on the host
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host_tick_rate 1396782 # Simulator tick rate (ticks/s)
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sim_freq 1000000000 # Frequency of simulated ticks
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sim_seconds 0.000352 # Number of seconds simulated
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sim_ticks 352261 # Number of ticks simulated
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@@ -141,6 +141,7 @@ deadlock_threshold=500000
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icache=system.l1_cntrl0.L1IcacheMemory
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max_outstanding_requests=16
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physmem=system.physmem
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using_network_tester=false
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using_ruby_tester=true
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version=0
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physMemPort=system.physmem.port[0]
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@@ -226,6 +227,7 @@ warmup_length=100000
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[system.tester]
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type=RubyTester
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check_flush=false
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checks_to_complete=100
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deadlock_threshold=50000
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wakeup_frequency=10
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@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
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================ End RubySystem Configuration Print ================
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Real time: Feb/08/2011 17:41:43
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Real time: Apr/19/2011 12:14:52
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Profiler Stats
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--------------
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Elapsed_time_in_seconds: 1
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Elapsed_time_in_minutes: 0.0166667
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Elapsed_time_in_hours: 0.000277778
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Elapsed_time_in_days: 1.15741e-05
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Elapsed_time_in_seconds: 0
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Elapsed_time_in_minutes: 0
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Elapsed_time_in_hours: 0
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Elapsed_time_in_days: 0
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Virtual_time_in_seconds: 0.8
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Virtual_time_in_minutes: 0.0133333
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Virtual_time_in_hours: 0.000222222
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Virtual_time_in_days: 9.25926e-06
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Virtual_time_in_seconds: 0.38
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Virtual_time_in_minutes: 0.00633333
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Virtual_time_in_hours: 0.000105556
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Virtual_time_in_days: 4.39815e-06
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Ruby_current_time: 372291
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Ruby_start_time: 0
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Ruby_cycles: 372291
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mbytes_resident: 33.7734
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mbytes_total: 208.148
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resident_ratio: 0.162313
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mbytes_resident: 35.7773
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mbytes_total: 206.145
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resident_ratio: 0.173574
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ruby_cycles_executed: [ 372292 ]
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@@ -71,9 +71,9 @@ sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1034 average: 15.8404
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All Non-Zero Cycle Demand Cache Accesses
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----------------------------------------
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miss_latency: [binsize: 256 max: 31997 count: 1019 average: 5668.53 | standard deviation: 8073.92 | 94 34 102 118 76 61 60 39 35 29 18 16 23 15 9 14 7 5 5 5 5 5 2 1 1 3 6 1 3 1 0 1 0 2 0 0 1 0 1 1 2 3 0 2 3 1 4 3 0 1 1 2 4 4 1 2 0 2 3 1 1 0 1 0 1 1 2 4 6 5 2 1 3 8 2 7 1 3 9 10 7 6 6 7 4 5 7 6 8 5 3 2 5 7 3 1 2 3 2 2 0 2 3 2 2 0 0 1 0 0 3 2 0 0 1 0 2 1 2 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_IFETCH: [binsize: 8 max: 1286 count: 55 average: 671.836 | standard deviation: 242.921 | 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0 1 1 2 2 0 0 1 0 0 1 0 0 1 0 2 3 1 4 1 0 0 1 0 0 0 0 1 0 1 2 2 1 0 0 1 0 0 1 0 0 1 0 1 1 1 1 0 1 0 0 0 1 0 1 1 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
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miss_latency_LD: [binsize: 256 max: 28569 count: 45 average: 4874.44 | standard deviation: 7882.18 | 6 2 5 9 2 2 3 2 0 0 1 1 0 0 0 1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_ST: [binsize: 256 max: 31997 count: 919 average: 6006.46 | standard deviation: 8225.99 | 86 24 69 94 73 58 57 37 35 29 17 15 23 15 9 13 7 5 5 4 4 5 1 1 1 3 6 1 3 1 0 1 0 2 0 0 1 0 1 1 2 3 0 2 3 1 4 3 0 1 1 1 4 4 1 2 0 2 3 1 1 0 1 0 1 1 2 4 6 5 2 1 3 7 2 7 1 2 8 10 6 6 6 7 4 5 7 5 8 5 3 2 5 7 2 1 2 3 2 2 0 2 3 2 2 0 0 1 0 0 3 1 0 0 1 0 2 1 2 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_IFETCH: [binsize: 8 max: 1286 count: 55 average: 671.836 | standard deviation: 242.921 | 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0 1 1 2 2 0 0 1 0 0 1 0 0 1 0 2 3 1 4 1 0 0 1 0 0 0 0 1 0 1 2 2 1 0 0 1 0 0 1 0 0 1 0 1 1 1 1 0 1 0 0 0 1 0 1 1 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
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miss_latency_NULL: [binsize: 256 max: 31997 count: 1019 average: 5668.53 | standard deviation: 8073.92 | 94 34 102 118 76 61 60 39 35 29 18 16 23 15 9 14 7 5 5 5 5 5 2 1 1 3 6 1 3 1 0 1 0 2 0 0 1 0 1 1 2 3 0 2 3 1 4 3 0 1 1 2 4 4 1 2 0 2 3 1 1 0 1 0 1 1 2 4 6 5 2 1 3 8 2 7 1 3 9 10 7 6 6 7 4 5 7 6 8 5 3 2 5 7 3 1 2 3 2 2 0 2 3 2 2 0 0 1 0 0 3 2 0 0 1 0 2 1 2 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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@@ -85,9 +85,9 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: N
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miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
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imcomplete_dir_Times: 0
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miss_latency_IFETCH_NULL: [binsize: 8 max: 1286 count: 55 average: 671.836 | standard deviation: 242.921 | 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0 1 1 2 2 0 0 1 0 0 1 0 0 1 0 2 3 1 4 1 0 0 1 0 0 0 0 1 0 1 2 2 1 0 0 1 0 0 1 0 0 1 0 1 1 1 1 0 1 0 0 0 1 0 1 1 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
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miss_latency_LD_NULL: [binsize: 256 max: 28569 count: 45 average: 4874.44 | standard deviation: 7882.18 | 6 2 5 9 2 2 3 2 0 0 1 1 0 0 0 1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_ST_NULL: [binsize: 256 max: 31997 count: 919 average: 6006.46 | standard deviation: 8225.99 | 86 24 69 94 73 58 57 37 35 29 17 15 23 15 9 13 7 5 5 4 4 5 1 1 1 3 6 1 3 1 0 1 0 2 0 0 1 0 1 1 2 3 0 2 3 1 4 3 0 1 1 1 4 4 1 2 0 2 3 1 1 0 1 0 1 1 2 4 6 5 2 1 3 7 2 7 1 2 8 10 6 6 6 7 4 5 7 5 8 5 3 2 5 7 2 1 2 3 2 2 0 2 3 2 2 0 0 1 0 0 3 1 0 0 1 0 2 1 2 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
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miss_latency_IFETCH_NULL: [binsize: 8 max: 1286 count: 55 average: 671.836 | standard deviation: 242.921 | 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0 1 1 2 2 0 0 1 0 0 1 0 0 1 0 2 3 1 4 1 0 0 1 0 0 0 0 1 0 1 2 2 1 0 0 1 0 0 1 0 0 1 0 1 1 1 1 0 1 0 0 0 1 0 1 1 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
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All Non-Zero Cycle SW Prefetch Requests
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------------------------------------
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@@ -119,11 +119,11 @@ Resource Usage
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||||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 9846
|
||||
page_reclaims: 9448
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 0
|
||||
block_outputs: 48
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Network Stats
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||||
-------------
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||||
@@ -411,6 +411,7 @@ Writeback_Ack [873 ] 873
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Writeback_Nack [0 ] 0
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||||
Unblock [0 ] 0
|
||||
Exclusive_Unblock [926 ] 926
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DmaAck [0 ] 0
|
||||
L2_Replacement [874 ] 874
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||||
|
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- Transitions -
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@@ -1160,6 +1161,76 @@ ILSI All_Acks [0 ] 0
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ILSI Writeback_Ack [0 ] 0
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ILSI L2_Replacement [0 ] 0
|
||||
|
||||
ILOSD L1_GETS [0 ] 0
|
||||
ILOSD L1_GETX [0 ] 0
|
||||
ILOSD L1_PUTO [0 ] 0
|
||||
ILOSD L1_PUTX [0 ] 0
|
||||
ILOSD L1_PUTS_only [0 ] 0
|
||||
ILOSD L1_PUTS [0 ] 0
|
||||
ILOSD Fwd_GETX [0 ] 0
|
||||
ILOSD Fwd_GETS [0 ] 0
|
||||
ILOSD Fwd_DMA [0 ] 0
|
||||
ILOSD Own_GETX [0 ] 0
|
||||
ILOSD Inv [0 ] 0
|
||||
ILOSD DmaAck [0 ] 0
|
||||
ILOSD L2_Replacement [0 ] 0
|
||||
|
||||
ILOSXD L1_GETS [0 ] 0
|
||||
ILOSXD L1_GETX [0 ] 0
|
||||
ILOSXD L1_PUTO [0 ] 0
|
||||
ILOSXD L1_PUTX [0 ] 0
|
||||
ILOSXD L1_PUTS_only [0 ] 0
|
||||
ILOSXD L1_PUTS [0 ] 0
|
||||
ILOSXD Fwd_GETX [0 ] 0
|
||||
ILOSXD Fwd_GETS [0 ] 0
|
||||
ILOSXD Fwd_DMA [0 ] 0
|
||||
ILOSXD Own_GETX [0 ] 0
|
||||
ILOSXD Inv [0 ] 0
|
||||
ILOSXD DmaAck [0 ] 0
|
||||
ILOSXD L2_Replacement [0 ] 0
|
||||
|
||||
ILOD L1_GETS [0 ] 0
|
||||
ILOD L1_GETX [0 ] 0
|
||||
ILOD L1_PUTO [0 ] 0
|
||||
ILOD L1_PUTX [0 ] 0
|
||||
ILOD L1_PUTS_only [0 ] 0
|
||||
ILOD L1_PUTS [0 ] 0
|
||||
ILOD Fwd_GETX [0 ] 0
|
||||
ILOD Fwd_GETS [0 ] 0
|
||||
ILOD Fwd_DMA [0 ] 0
|
||||
ILOD Own_GETX [0 ] 0
|
||||
ILOD Inv [0 ] 0
|
||||
ILOD DmaAck [0 ] 0
|
||||
ILOD L2_Replacement [0 ] 0
|
||||
|
||||
ILXD L1_GETS [0 ] 0
|
||||
ILXD L1_GETX [0 ] 0
|
||||
ILXD L1_PUTO [0 ] 0
|
||||
ILXD L1_PUTX [0 ] 0
|
||||
ILXD L1_PUTS_only [0 ] 0
|
||||
ILXD L1_PUTS [0 ] 0
|
||||
ILXD Fwd_GETX [0 ] 0
|
||||
ILXD Fwd_GETS [0 ] 0
|
||||
ILXD Fwd_DMA [0 ] 0
|
||||
ILXD Own_GETX [0 ] 0
|
||||
ILXD Inv [0 ] 0
|
||||
ILXD DmaAck [0 ] 0
|
||||
ILXD L2_Replacement [0 ] 0
|
||||
|
||||
ILOXD L1_GETS [0 ] 0
|
||||
ILOXD L1_GETX [0 ] 0
|
||||
ILOXD L1_PUTO [0 ] 0
|
||||
ILOXD L1_PUTX [0 ] 0
|
||||
ILOXD L1_PUTS_only [0 ] 0
|
||||
ILOXD L1_PUTS [0 ] 0
|
||||
ILOXD Fwd_GETX [0 ] 0
|
||||
ILOXD Fwd_GETS [0 ] 0
|
||||
ILOXD Fwd_DMA [0 ] 0
|
||||
ILOXD Own_GETX [0 ] 0
|
||||
ILOXD Inv [0 ] 0
|
||||
ILOXD DmaAck [0 ] 0
|
||||
ILOXD L2_Replacement [0 ] 0
|
||||
|
||||
Memory controller: system.dir_cntrl0.memBuffer:
|
||||
memory_total_requests: 1676
|
||||
memory_reads: 882
|
||||
@@ -1196,6 +1267,7 @@ Memory_Data [882 ] 882
|
||||
Memory_Ack [793 ] 793
|
||||
DMA_READ [0 ] 0
|
||||
DMA_WRITE [0 ] 0
|
||||
DMA_ACK [0 ] 0
|
||||
Data [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
@@ -1376,4 +1448,22 @@ OI_D PUTO [0 ] 0
|
||||
OI_D PUTO_SHARERS [0 ] 0
|
||||
OI_D DMA_READ [0 ] 0
|
||||
OI_D DMA_WRITE [0 ] 0
|
||||
OI_D Data
|
||||
OI_D Data [0 ] 0
|
||||
|
||||
OD GETX [0 ] 0
|
||||
OD GETS [0 ] 0
|
||||
OD PUTX [0 ] 0
|
||||
OD PUTO [0 ] 0
|
||||
OD PUTO_SHARERS [0 ] 0
|
||||
OD DMA_READ [0 ] 0
|
||||
OD DMA_WRITE [0 ] 0
|
||||
OD DMA_ACK [0 ] 0
|
||||
|
||||
MD GETX [0 ] 0
|
||||
MD GETS [0 ] 0
|
||||
MD PUTX [0 ] 0
|
||||
MD PUTO [0 ] 0
|
||||
MD PUTO_SHARERS [0 ] 0
|
||||
MD DMA_READ [0 ] 0
|
||||
MD DMA_WRITE [0 ] 0
|
||||
MD DMA_ACK
|
||||
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Feb 8 2011 17:41:34
|
||||
M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip
|
||||
M5 started Feb 8 2011 17:41:42
|
||||
M5 executing on SC2B0617
|
||||
M5 compiled Apr 19 2011 12:14:48
|
||||
M5 started Apr 19 2011 12:14:52
|
||||
M5 executing on maize
|
||||
command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
@@ -1,8 +1,8 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_mem_usage 213148 # Number of bytes of host memory used
|
||||
host_seconds 0.50 # Real time elapsed on the host
|
||||
host_tick_rate 746373 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 211096 # Number of bytes of host memory used
|
||||
host_seconds 0.28 # Real time elapsed on the host
|
||||
host_tick_rate 1336063 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_seconds 0.000372 # Number of seconds simulated
|
||||
sim_ticks 372291 # Number of ticks simulated
|
||||
|
||||
@@ -238,6 +238,7 @@ warmup_length=100000
|
||||
|
||||
[system.tester]
|
||||
type=RubyTester
|
||||
check_flush=false
|
||||
checks_to_complete=100
|
||||
deadlock_threshold=50000
|
||||
wakeup_frequency=10
|
||||
|
||||
@@ -34,27 +34,27 @@ periodic_stats_period: 1000000
|
||||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Mar/26/2011 22:00:44
|
||||
Real time: Apr/19/2011 12:17:16
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 1
|
||||
Elapsed_time_in_minutes: 0.0166667
|
||||
Elapsed_time_in_hours: 0.000277778
|
||||
Elapsed_time_in_days: 1.15741e-05
|
||||
Elapsed_time_in_seconds: 0
|
||||
Elapsed_time_in_minutes: 0
|
||||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.23
|
||||
Virtual_time_in_minutes: 0.00383333
|
||||
Virtual_time_in_hours: 6.38889e-05
|
||||
Virtual_time_in_days: 2.66204e-06
|
||||
Virtual_time_in_seconds: 0.19
|
||||
Virtual_time_in_minutes: 0.00316667
|
||||
Virtual_time_in_hours: 5.27778e-05
|
||||
Virtual_time_in_days: 2.19907e-06
|
||||
|
||||
Ruby_current_time: 268001
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 268001
|
||||
|
||||
mbytes_resident: 34.8828
|
||||
mbytes_total: 197.086
|
||||
resident_ratio: 0.177013
|
||||
mbytes_resident: 35.6602
|
||||
mbytes_total: 205.984
|
||||
resident_ratio: 0.17314
|
||||
|
||||
ruby_cycles_executed: [ 268002 ]
|
||||
|
||||
@@ -127,7 +127,7 @@ Resource Usage
|
||||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 9226
|
||||
page_reclaims: 9422
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
|
||||
@@ -5,9 +5,9 @@ The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Mar 26 2011 14:06:20
|
||||
M5 started Mar 26 2011 22:00:43
|
||||
M5 executing on phenom
|
||||
M5 compiled Apr 19 2011 12:17:10
|
||||
M5 started Apr 19 2011 12:17:16
|
||||
M5 executing on maize
|
||||
command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
@@ -1,8 +1,8 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_mem_usage 201820 # Number of bytes of host memory used
|
||||
host_seconds 0.29 # Real time elapsed on the host
|
||||
host_tick_rate 910825 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 210932 # Number of bytes of host memory used
|
||||
host_seconds 0.09 # Real time elapsed on the host
|
||||
host_tick_rate 3091502 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_seconds 0.000268 # Number of seconds simulated
|
||||
sim_ticks 268001 # Number of ticks simulated
|
||||
|
||||
@@ -128,6 +128,7 @@ deadlock_threshold=500000
|
||||
icache=system.ruby.cpu_ruby_ports.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_network_tester=false
|
||||
using_ruby_tester=true
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
@@ -213,6 +214,7 @@ warmup_length=100000
|
||||
|
||||
[system.tester]
|
||||
type=RubyTester
|
||||
check_flush=false
|
||||
checks_to_complete=100
|
||||
deadlock_threshold=50000
|
||||
wakeup_frequency=10
|
||||
|
||||
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
|
||||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Feb/08/2011 17:57:03
|
||||
Real time: Apr/19/2011 12:09:50
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
|
||||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.4
|
||||
Virtual_time_in_minutes: 0.00666667
|
||||
Virtual_time_in_hours: 0.000111111
|
||||
Virtual_time_in_days: 4.62963e-06
|
||||
Virtual_time_in_seconds: 0.17
|
||||
Virtual_time_in_minutes: 0.00283333
|
||||
Virtual_time_in_hours: 4.72222e-05
|
||||
Virtual_time_in_days: 1.96759e-06
|
||||
|
||||
Ruby_current_time: 210961
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 210961
|
||||
|
||||
mbytes_resident: 33.4023
|
||||
mbytes_total: 207.566
|
||||
resident_ratio: 0.160961
|
||||
mbytes_resident: 35.4336
|
||||
mbytes_total: 205.836
|
||||
resident_ratio: 0.172164
|
||||
|
||||
ruby_cycles_executed: [ 210962 ]
|
||||
|
||||
@@ -70,9 +70,9 @@ sequencer_requests_outstanding: [binsize: 1 max: 16 count: 978 average: 15.8016
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 64 max: 8993 count: 963 average: 3469.42 | standard deviation: 1599.67 | 72 11 5 3 10 7 13 12 7 12 1 8 4 1 1 2 0 1 0 0 1 1 0 0 1 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 2 3 2 0 5 2 2 5 6 10 12 7 16 18 17 32 34 24 31 26 29 36 35 35 28 41 44 32 34 21 30 17 25 22 20 20 10 10 6 8 9 7 5 2 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 8 max: 1126 count: 52 average: 473.327 | standard deviation: 221.338 | 0 2 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 2 1 1 0 0 0 1 0 1 0 1 0 0 2 5 1 1 0 0 0 0 0 0 0 0 0 1 0 3 2 2 1 0 1 0 0 0 0 1 2 0 0 2 0 1 0 1 0 0 0 0 0 0 0 2 2 2 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD: [binsize: 32 max: 5235 count: 48 average: 3979.79 | standard deviation: 1306.56 | 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 1 0 1 0 0 1 0 1 0 1 0 2 3 2 2 1 4 0 1 0 1 1 2 0 0 1 0 2 1 1 0 0 0 0 0 0 1 0 1 0 3 0 2 0 0 0 3 0 1 ]
|
||||
miss_latency_ST: [binsize: 64 max: 8993 count: 863 average: 3621.56 | standard deviation: 1476.69 | 66 9 4 1 5 2 6 6 3 6 0 0 2 1 1 2 0 0 0 0 1 1 0 0 1 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 2 3 2 0 5 2 2 5 5 10 11 7 16 18 17 32 31 23 31 25 28 35 30 31 23 40 43 29 34 20 27 16 25 22 19 19 7 8 6 5 8 7 5 2 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 8 max: 1126 count: 52 average: 473.327 | standard deviation: 221.338 | 0 2 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 2 1 1 0 0 0 1 0 1 0 1 0 0 2 5 1 1 0 0 0 0 0 0 0 0 0 1 0 3 2 2 1 0 1 0 0 0 0 1 2 0 0 2 0 1 0 1 0 0 0 0 0 0 0 2 2 2 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_L1Cache: [binsize: 1 max: 117 count: 71 average: 13.3803 | standard deviation: 32.5601 | 0 10 15 23 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 2 1 0 0 0 1 1 ]
|
||||
miss_latency_L2Cache: [binsize: 64 max: 8993 count: 33 average: 2589.88 | standard deviation: 2554.56 | 8 4 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 4 2 2 1 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 ]
|
||||
miss_latency_Directory: [binsize: 32 max: 6151 count: 859 average: 3788.87 | standard deviation: 1226.92 | 0 0 0 0 0 5 1 1 8 2 2 5 13 0 0 12 6 0 4 8 1 0 7 1 1 3 1 0 1 0 1 1 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 2 1 2 0 0 0 5 0 1 1 2 0 2 3 3 3 6 3 4 7 4 3 6 10 11 6 4 12 14 14 15 17 13 9 17 13 7 19 18 10 17 19 20 15 17 17 8 20 25 16 22 22 14 18 15 19 10 10 19 11 9 8 14 11 15 7 12 8 9 11 5 5 4 6 3 3 3 5 4 5 2 5 2 3 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 ]
|
||||
@@ -86,13 +86,13 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: N
|
||||
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
imcomplete_dir_Times: 859
|
||||
miss_latency_IFETCH_L2Cache: [binsize: 1 max: 117 count: 4 average: 62.25 | standard deviation: 62.0725 | 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 8 max: 1126 count: 48 average: 507.583 | standard deviation: 193.22 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 2 1 1 0 0 0 1 0 1 0 1 0 0 2 5 1 1 0 0 0 0 0 0 0 0 0 1 0 3 2 2 1 0 1 0 0 0 0 1 2 0 0 2 0 1 0 1 0 0 0 0 0 0 0 2 2 2 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 4 average: 2 | standard deviation: 0.816497 | 0 1 2 1 ]
|
||||
miss_latency_LD_Directory: [binsize: 32 max: 5235 count: 44 average: 4341.41 | standard deviation: 510.099 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 1 0 1 0 0 1 0 1 0 1 0 2 3 2 2 1 4 0 1 0 1 1 2 0 0 1 0 2 1 1 0 0 0 0 0 0 1 0 1 0 3 0 2 0 0 0 3 0 1 ]
|
||||
miss_latency_ST_L1Cache: [binsize: 1 max: 117 count: 67 average: 14.0597 | standard deviation: 33.4075 | 0 9 13 22 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 2 1 0 0 0 1 1 ]
|
||||
miss_latency_ST_L2Cache: [binsize: 64 max: 8993 count: 29 average: 2938.52 | standard deviation: 2533.58 | 6 2 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 4 2 2 1 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 ]
|
||||
miss_latency_ST_Directory: [binsize: 32 max: 6151 count: 767 average: 3962.52 | standard deviation: 973.04 | 0 0 0 0 0 4 0 0 4 1 0 2 6 0 0 6 2 0 1 5 0 0 0 0 0 2 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 2 1 2 0 0 0 5 0 1 1 2 0 2 3 3 2 6 3 4 6 4 3 6 10 11 6 4 12 14 14 13 16 13 8 17 13 6 19 17 10 16 19 18 12 15 15 7 16 25 15 22 21 13 16 15 19 9 10 17 10 8 8 14 11 15 7 12 7 9 10 5 2 4 4 3 3 3 2 4 4 2 5 2 3 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 ]
|
||||
miss_latency_IFETCH_L2Cache: [binsize: 1 max: 117 count: 4 average: 62.25 | standard deviation: 62.0725 | 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 8 max: 1126 count: 48 average: 507.583 | standard deviation: 193.22 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 2 1 1 0 0 0 1 0 1 0 1 0 0 2 5 1 1 0 0 0 0 0 0 0 0 0 1 0 3 2 2 1 0 1 0 0 0 0 1 2 0 0 2 0 1 0 1 0 0 0 0 0 0 0 2 2 2 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
@@ -124,11 +124,11 @@ Resource Usage
|
||||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 9722
|
||||
page_reclaims: 9364
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 0
|
||||
block_outputs: 56
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
@@ -188,7 +188,7 @@ Cache Stats: system.ruby.cpu_ruby_ports.icache
|
||||
|
||||
system.ruby.cpu_ruby_ports.icache_request_type_IFETCH: 100%
|
||||
|
||||
system.ruby.cpu_ruby_ports.icache_access_mode_type_SupervisorMode: 52 100%
|
||||
system.ruby.cpu_ruby_ports.icache_access_mode_type_Supervisor: 52 100%
|
||||
|
||||
Cache Stats: system.ruby.cpu_ruby_ports.dcache
|
||||
system.ruby.cpu_ruby_ports.dcache_total_misses: 852
|
||||
@@ -200,7 +200,7 @@ Cache Stats: system.ruby.cpu_ruby_ports.dcache
|
||||
system.ruby.cpu_ruby_ports.dcache_request_type_LD: 5.28169%
|
||||
system.ruby.cpu_ruby_ports.dcache_request_type_ST: 94.7183%
|
||||
|
||||
system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode: 852 100%
|
||||
system.ruby.cpu_ruby_ports.dcache_access_mode_type_Supervisor: 852 100%
|
||||
|
||||
Cache Stats: system.l1_cntrl0.L2cacheMemory
|
||||
system.l1_cntrl0.L2cacheMemory_total_misses: 904
|
||||
@@ -213,7 +213,7 @@ Cache Stats: system.l1_cntrl0.L2cacheMemory
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_ST: 89.2699%
|
||||
system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 5.75221%
|
||||
|
||||
system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 904 100%
|
||||
system.l1_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 904 100%
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
@@ -240,6 +240,8 @@ Writeback_Ack [852 ] 852
|
||||
Writeback_Nack [0 ] 0
|
||||
All_acks [0 ] 0
|
||||
All_acks_no_sharers [859 ] 859
|
||||
Flush_line [0 ] 0
|
||||
Block_Ack [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
I Load [44 ] 44
|
||||
@@ -254,6 +256,7 @@ I Other_GETS [0 ] 0
|
||||
I Other_GETS_No_Mig [0 ] 0
|
||||
I NC_DMA_GETS [0 ] 0
|
||||
I Invalidate [0 ] 0
|
||||
I Flush_line [0 ] 0
|
||||
|
||||
S Load [0 ] 0
|
||||
S Ifetch [0 ] 0
|
||||
@@ -267,6 +270,7 @@ S Other_GETS [0 ] 0
|
||||
S Other_GETS_No_Mig [0 ] 0
|
||||
S NC_DMA_GETS [0 ] 0
|
||||
S Invalidate [0 ] 0
|
||||
S Flush_line [0 ] 0
|
||||
|
||||
O Load [0 ] 0
|
||||
O Ifetch [0 ] 0
|
||||
@@ -281,6 +285,7 @@ O Merged_GETS [0 ] 0
|
||||
O Other_GETS_No_Mig [0 ] 0
|
||||
O NC_DMA_GETS [0 ] 0
|
||||
O Invalidate [0 ] 0
|
||||
O Flush_line [0 ] 0
|
||||
|
||||
M Load [0 ] 0
|
||||
M Ifetch [0 ] 0
|
||||
@@ -295,6 +300,7 @@ M Merged_GETS [0 ] 0
|
||||
M Other_GETS_No_Mig [0 ] 0
|
||||
M NC_DMA_GETS [0 ] 0
|
||||
M Invalidate [0 ] 0
|
||||
M Flush_line [0 ] 0
|
||||
|
||||
MM Load [4 ] 4
|
||||
MM Ifetch [4 ] 4
|
||||
@@ -309,6 +315,7 @@ MM Merged_GETS [0 ] 0
|
||||
MM Other_GETS_No_Mig [0 ] 0
|
||||
MM NC_DMA_GETS [0 ] 0
|
||||
MM Invalidate [0 ] 0
|
||||
MM Flush_line [0 ] 0
|
||||
|
||||
IM Load [0 ] 0
|
||||
IM Ifetch [0 ] 0
|
||||
@@ -323,6 +330,7 @@ IM Invalidate [0 ] 0
|
||||
IM Ack [0 ] 0
|
||||
IM Data [0 ] 0
|
||||
IM Exclusive_Data [767 ] 767
|
||||
IM Flush_line [0 ] 0
|
||||
|
||||
SM Load [0 ] 0
|
||||
SM Ifetch [0 ] 0
|
||||
@@ -337,6 +345,7 @@ SM Invalidate [0 ] 0
|
||||
SM Ack [0 ] 0
|
||||
SM Data [0 ] 0
|
||||
SM Exclusive_Data [0 ] 0
|
||||
SM Flush_line [0 ] 0
|
||||
|
||||
OM Load [0 ] 0
|
||||
OM Ifetch [0 ] 0
|
||||
@@ -352,6 +361,7 @@ OM Invalidate [0 ] 0
|
||||
OM Ack [0 ] 0
|
||||
OM All_acks [0 ] 0
|
||||
OM All_acks_no_sharers [0 ] 0
|
||||
OM Flush_line [0 ] 0
|
||||
|
||||
ISM Load [0 ] 0
|
||||
ISM Ifetch [0 ] 0
|
||||
@@ -360,6 +370,7 @@ ISM L2_Replacement [0 ] 0
|
||||
ISM L1_to_L2 [0 ] 0
|
||||
ISM Ack [0 ] 0
|
||||
ISM All_acks_no_sharers [0 ] 0
|
||||
ISM Flush_line [0 ] 0
|
||||
|
||||
M_W Load [0 ] 0
|
||||
M_W Ifetch [0 ] 0
|
||||
@@ -368,6 +379,7 @@ M_W L2_Replacement [0 ] 0
|
||||
M_W L1_to_L2 [310 ] 310
|
||||
M_W Ack [0 ] 0
|
||||
M_W All_acks_no_sharers [91 ] 91
|
||||
M_W Flush_line [0 ] 0
|
||||
|
||||
MM_W Load [0 ] 0
|
||||
MM_W Ifetch [0 ] 0
|
||||
@@ -376,6 +388,7 @@ MM_W L2_Replacement [0 ] 0
|
||||
MM_W L1_to_L2 [4284 ] 4284
|
||||
MM_W Ack [0 ] 0
|
||||
MM_W All_acks_no_sharers [768 ] 768
|
||||
MM_W Flush_line [0 ] 0
|
||||
|
||||
IS Load [0 ] 0
|
||||
IS Ifetch [0 ] 0
|
||||
@@ -392,6 +405,7 @@ IS Shared_Ack [0 ] 0
|
||||
IS Data [0 ] 0
|
||||
IS Shared_Data [0 ] 0
|
||||
IS Exclusive_Data [92 ] 92
|
||||
IS Flush_line [0 ] 0
|
||||
|
||||
SS Load [0 ] 0
|
||||
SS Ifetch [0 ] 0
|
||||
@@ -402,6 +416,7 @@ SS Ack [0 ] 0
|
||||
SS Shared_Ack [0 ] 0
|
||||
SS All_acks [0 ] 0
|
||||
SS All_acks_no_sharers [0 ] 0
|
||||
SS Flush_line [0 ] 0
|
||||
|
||||
OI Load [0 ] 0
|
||||
OI Ifetch [0 ] 0
|
||||
@@ -415,6 +430,7 @@ OI Other_GETS_No_Mig [0 ] 0
|
||||
OI NC_DMA_GETS [0 ] 0
|
||||
OI Invalidate [0 ] 0
|
||||
OI Writeback_Ack [0 ] 0
|
||||
OI Flush_line [0 ] 0
|
||||
|
||||
MI Load [0 ] 0
|
||||
MI Ifetch [1 ] 1
|
||||
@@ -428,6 +444,7 @@ MI Other_GETS_No_Mig [0 ] 0
|
||||
MI NC_DMA_GETS [0 ] 0
|
||||
MI Invalidate [0 ] 0
|
||||
MI Writeback_Ack [852 ] 852
|
||||
MI Flush_line [0 ] 0
|
||||
|
||||
II Load [0 ] 0
|
||||
II Ifetch [0 ] 0
|
||||
@@ -441,6 +458,7 @@ II NC_DMA_GETS [0 ] 0
|
||||
II Invalidate [0 ] 0
|
||||
II Writeback_Ack [0 ] 0
|
||||
II Writeback_Nack [0 ] 0
|
||||
II Flush_line [0 ] 0
|
||||
|
||||
IT Load [0 ] 0
|
||||
IT Ifetch [0 ] 0
|
||||
@@ -454,6 +472,7 @@ IT Merged_GETS [0 ] 0
|
||||
IT Other_GETS_No_Mig [0 ] 0
|
||||
IT NC_DMA_GETS [0 ] 0
|
||||
IT Invalidate [0 ] 0
|
||||
IT Flush_line [0 ] 0
|
||||
|
||||
ST Load [0 ] 0
|
||||
ST Ifetch [0 ] 0
|
||||
@@ -467,6 +486,7 @@ ST Merged_GETS [0 ] 0
|
||||
ST Other_GETS_No_Mig [0 ] 0
|
||||
ST NC_DMA_GETS [0 ] 0
|
||||
ST Invalidate [0 ] 0
|
||||
ST Flush_line [0 ] 0
|
||||
|
||||
OT Load [0 ] 0
|
||||
OT Ifetch [0 ] 0
|
||||
@@ -480,6 +500,7 @@ OT Merged_GETS [0 ] 0
|
||||
OT Other_GETS_No_Mig [0 ] 0
|
||||
OT NC_DMA_GETS [0 ] 0
|
||||
OT Invalidate [0 ] 0
|
||||
OT Flush_line [0 ] 0
|
||||
|
||||
MT Load [0 ] 0
|
||||
MT Ifetch [0 ] 0
|
||||
@@ -493,6 +514,7 @@ MT Merged_GETS [0 ] 0
|
||||
MT Other_GETS_No_Mig [0 ] 0
|
||||
MT NC_DMA_GETS [0 ] 0
|
||||
MT Invalidate [0 ] 0
|
||||
MT Flush_line [0 ] 0
|
||||
|
||||
MMT Load [0 ] 0
|
||||
MMT Ifetch [0 ] 0
|
||||
@@ -506,6 +528,94 @@ MMT Merged_GETS [0 ] 0
|
||||
MMT Other_GETS_No_Mig [0 ] 0
|
||||
MMT NC_DMA_GETS [0 ] 0
|
||||
MMT Invalidate [0 ] 0
|
||||
MMT Flush_line [0 ] 0
|
||||
|
||||
MI_F Load [0 ] 0
|
||||
MI_F Ifetch [0 ] 0
|
||||
MI_F Store [0 ] 0
|
||||
MI_F L1_to_L2 [0 ] 0
|
||||
MI_F Writeback_Ack [0 ] 0
|
||||
MI_F Flush_line [0 ] 0
|
||||
|
||||
MM_F Load [0 ] 0
|
||||
MM_F Ifetch [0 ] 0
|
||||
MM_F Store [0 ] 0
|
||||
MM_F L1_to_L2 [0 ] 0
|
||||
MM_F Other_GETX [0 ] 0
|
||||
MM_F Other_GETS [0 ] 0
|
||||
MM_F Merged_GETS [0 ] 0
|
||||
MM_F Other_GETS_No_Mig [0 ] 0
|
||||
MM_F NC_DMA_GETS [0 ] 0
|
||||
MM_F Invalidate [0 ] 0
|
||||
MM_F Ack [0 ] 0
|
||||
MM_F All_acks [0 ] 0
|
||||
MM_F All_acks_no_sharers [0 ] 0
|
||||
MM_F Flush_line [0 ] 0
|
||||
MM_F Block_Ack [0 ] 0
|
||||
|
||||
IM_F Load [0 ] 0
|
||||
IM_F Ifetch [0 ] 0
|
||||
IM_F Store [0 ] 0
|
||||
IM_F L2_Replacement [0 ] 0
|
||||
IM_F L1_to_L2 [0 ] 0
|
||||
IM_F Other_GETX [0 ] 0
|
||||
IM_F Other_GETS [0 ] 0
|
||||
IM_F Other_GETS_No_Mig [0 ] 0
|
||||
IM_F NC_DMA_GETS [0 ] 0
|
||||
IM_F Invalidate [0 ] 0
|
||||
IM_F Ack [0 ] 0
|
||||
IM_F Data [0 ] 0
|
||||
IM_F Exclusive_Data [0 ] 0
|
||||
IM_F Flush_line [0 ] 0
|
||||
|
||||
ISM_F Load [0 ] 0
|
||||
ISM_F Ifetch [0 ] 0
|
||||
ISM_F Store [0 ] 0
|
||||
ISM_F L2_Replacement [0 ] 0
|
||||
ISM_F L1_to_L2 [0 ] 0
|
||||
ISM_F Ack [0 ] 0
|
||||
ISM_F All_acks_no_sharers [0 ] 0
|
||||
ISM_F Flush_line [0 ] 0
|
||||
|
||||
SM_F Load [0 ] 0
|
||||
SM_F Ifetch [0 ] 0
|
||||
SM_F Store [0 ] 0
|
||||
SM_F L2_Replacement [0 ] 0
|
||||
SM_F L1_to_L2 [0 ] 0
|
||||
SM_F Other_GETX [0 ] 0
|
||||
SM_F Other_GETS [0 ] 0
|
||||
SM_F Other_GETS_No_Mig [0 ] 0
|
||||
SM_F NC_DMA_GETS [0 ] 0
|
||||
SM_F Invalidate [0 ] 0
|
||||
SM_F Ack [0 ] 0
|
||||
SM_F Data [0 ] 0
|
||||
SM_F Exclusive_Data [0 ] 0
|
||||
SM_F Flush_line [0 ] 0
|
||||
|
||||
OM_F Load [0 ] 0
|
||||
OM_F Ifetch [0 ] 0
|
||||
OM_F Store [0 ] 0
|
||||
OM_F L2_Replacement [0 ] 0
|
||||
OM_F L1_to_L2 [0 ] 0
|
||||
OM_F Other_GETX [0 ] 0
|
||||
OM_F Other_GETS [0 ] 0
|
||||
OM_F Merged_GETS [0 ] 0
|
||||
OM_F Other_GETS_No_Mig [0 ] 0
|
||||
OM_F NC_DMA_GETS [0 ] 0
|
||||
OM_F Invalidate [0 ] 0
|
||||
OM_F Ack [0 ] 0
|
||||
OM_F All_acks [0 ] 0
|
||||
OM_F All_acks_no_sharers [0 ] 0
|
||||
OM_F Flush_line [0 ] 0
|
||||
|
||||
MM_WF Load [0 ] 0
|
||||
MM_WF Ifetch [0 ] 0
|
||||
MM_WF Store [0 ] 0
|
||||
MM_WF L2_Replacement [0 ] 0
|
||||
MM_WF L1_to_L2 [0 ] 0
|
||||
MM_WF Ack [0 ] 0
|
||||
MM_WF All_acks_no_sharers [0 ] 0
|
||||
MM_WF Flush_line [0 ] 0
|
||||
|
||||
Cache Stats: system.dir_cntrl0.probeFilter
|
||||
system.dir_cntrl0.probeFilter_total_misses: 0
|
||||
@@ -561,6 +671,8 @@ All_acks_and_shared_data [0 ] 0
|
||||
All_acks_and_owner_data [0 ] 0
|
||||
All_acks_and_data_no_sharers [0 ] 0
|
||||
All_Unblocks [0 ] 0
|
||||
GETF [0 ] 0
|
||||
PUTF [0 ] 0
|
||||
|
||||
- Transitions -
|
||||
NX GETX [0 ] 0
|
||||
@@ -569,6 +681,7 @@ NX PUT [0 ] 0
|
||||
NX Pf_Replacement [0 ] 0
|
||||
NX DMA_READ [0 ] 0
|
||||
NX DMA_WRITE [0 ] 0
|
||||
NX GETF [0 ] 0
|
||||
|
||||
NO GETX [0 ] 0
|
||||
NO GETS [0 ] 0
|
||||
@@ -576,6 +689,7 @@ NO PUT [852 ] 852
|
||||
NO Pf_Replacement [0 ] 0
|
||||
NO DMA_READ [0 ] 0
|
||||
NO DMA_WRITE [0 ] 0
|
||||
NO GETF [0 ] 0
|
||||
|
||||
S GETX [0 ] 0
|
||||
S GETS [0 ] 0
|
||||
@@ -583,6 +697,7 @@ S PUT [0 ] 0
|
||||
S Pf_Replacement [0 ] 0
|
||||
S DMA_READ [0 ] 0
|
||||
S DMA_WRITE [0 ] 0
|
||||
S GETF [0 ] 0
|
||||
|
||||
O GETX [0 ] 0
|
||||
O GETS [0 ] 0
|
||||
@@ -590,12 +705,14 @@ O PUT [0 ] 0
|
||||
O Pf_Replacement [0 ] 0
|
||||
O DMA_READ [0 ] 0
|
||||
O DMA_WRITE [0 ] 0
|
||||
O GETF [0 ] 0
|
||||
|
||||
E GETX [767 ] 767
|
||||
E GETS [92 ] 92
|
||||
E PUT [0 ] 0
|
||||
E DMA_READ [0 ] 0
|
||||
E DMA_WRITE [0 ] 0
|
||||
E GETF [0 ] 0
|
||||
|
||||
O_R GETX [0 ] 0
|
||||
O_R GETS [0 ] 0
|
||||
@@ -605,6 +722,7 @@ O_R DMA_READ [0 ] 0
|
||||
O_R DMA_WRITE [0 ] 0
|
||||
O_R Ack [0 ] 0
|
||||
O_R All_acks_and_data_no_sharers [0 ] 0
|
||||
O_R GETF [0 ] 0
|
||||
|
||||
S_R GETX [0 ] 0
|
||||
S_R GETS [0 ] 0
|
||||
@@ -615,6 +733,7 @@ S_R DMA_WRITE [0 ] 0
|
||||
S_R Ack [0 ] 0
|
||||
S_R Data [0 ] 0
|
||||
S_R All_acks_and_data_no_sharers [0 ] 0
|
||||
S_R GETF [0 ] 0
|
||||
|
||||
NO_R GETX [0 ] 0
|
||||
NO_R GETS [0 ] 0
|
||||
@@ -626,6 +745,7 @@ NO_R Ack [0 ] 0
|
||||
NO_R Data [0 ] 0
|
||||
NO_R Exclusive_Data [0 ] 0
|
||||
NO_R All_acks_and_data_no_sharers [0 ] 0
|
||||
NO_R GETF [0 ] 0
|
||||
|
||||
NO_B GETX [0 ] 0
|
||||
NO_B GETS [0 ] 0
|
||||
@@ -635,6 +755,7 @@ NO_B UnblockM [856 ] 856
|
||||
NO_B Pf_Replacement [0 ] 0
|
||||
NO_B DMA_READ [0 ] 0
|
||||
NO_B DMA_WRITE [0 ] 0
|
||||
NO_B GETF [0 ] 0
|
||||
|
||||
NO_B_X GETX [0 ] 0
|
||||
NO_B_X GETS [0 ] 0
|
||||
@@ -644,6 +765,7 @@ NO_B_X UnblockM [0 ] 0
|
||||
NO_B_X Pf_Replacement [0 ] 0
|
||||
NO_B_X DMA_READ [0 ] 0
|
||||
NO_B_X DMA_WRITE [0 ] 0
|
||||
NO_B_X GETF [0 ] 0
|
||||
|
||||
NO_B_S GETX [0 ] 0
|
||||
NO_B_S GETS [0 ] 0
|
||||
@@ -653,6 +775,7 @@ NO_B_S UnblockM [0 ] 0
|
||||
NO_B_S Pf_Replacement [0 ] 0
|
||||
NO_B_S DMA_READ [0 ] 0
|
||||
NO_B_S DMA_WRITE [0 ] 0
|
||||
NO_B_S GETF [0 ] 0
|
||||
|
||||
NO_B_S_W GETX [0 ] 0
|
||||
NO_B_S_W GETS [0 ] 0
|
||||
@@ -662,6 +785,7 @@ NO_B_S_W Pf_Replacement [0 ] 0
|
||||
NO_B_S_W DMA_READ [0 ] 0
|
||||
NO_B_S_W DMA_WRITE [0 ] 0
|
||||
NO_B_S_W All_Unblocks [0 ] 0
|
||||
NO_B_S_W GETF [0 ] 0
|
||||
|
||||
O_B GETX [0 ] 0
|
||||
O_B GETS [0 ] 0
|
||||
@@ -671,6 +795,7 @@ O_B UnblockM [0 ] 0
|
||||
O_B Pf_Replacement [0 ] 0
|
||||
O_B DMA_READ [0 ] 0
|
||||
O_B DMA_WRITE [0 ] 0
|
||||
O_B GETF [0 ] 0
|
||||
|
||||
NO_B_W GETX [0 ] 0
|
||||
NO_B_W GETS [0 ] 0
|
||||
@@ -681,6 +806,7 @@ NO_B_W Pf_Replacement [0 ] 0
|
||||
NO_B_W DMA_READ [0 ] 0
|
||||
NO_B_W DMA_WRITE [0 ] 0
|
||||
NO_B_W Memory_Data [859 ] 859
|
||||
NO_B_W GETF [0 ] 0
|
||||
|
||||
O_B_W GETX [0 ] 0
|
||||
O_B_W GETS [0 ] 0
|
||||
@@ -690,6 +816,7 @@ O_B_W Pf_Replacement [0 ] 0
|
||||
O_B_W DMA_READ [0 ] 0
|
||||
O_B_W DMA_WRITE [0 ] 0
|
||||
O_B_W Memory_Data [0 ] 0
|
||||
O_B_W GETF [0 ] 0
|
||||
|
||||
NO_W GETX [0 ] 0
|
||||
NO_W GETS [0 ] 0
|
||||
@@ -698,6 +825,7 @@ NO_W Pf_Replacement [0 ] 0
|
||||
NO_W DMA_READ [0 ] 0
|
||||
NO_W DMA_WRITE [0 ] 0
|
||||
NO_W Memory_Data [0 ] 0
|
||||
NO_W GETF [0 ] 0
|
||||
|
||||
O_W GETX [0 ] 0
|
||||
O_W GETS [0 ] 0
|
||||
@@ -706,6 +834,7 @@ O_W Pf_Replacement [0 ] 0
|
||||
O_W DMA_READ [0 ] 0
|
||||
O_W DMA_WRITE [0 ] 0
|
||||
O_W Memory_Data [0 ] 0
|
||||
O_W GETF [0 ] 0
|
||||
|
||||
NO_DW_B_W GETX [0 ] 0
|
||||
NO_DW_B_W GETS [0 ] 0
|
||||
@@ -717,6 +846,7 @@ NO_DW_B_W Ack [0 ] 0
|
||||
NO_DW_B_W Data [0 ] 0
|
||||
NO_DW_B_W Exclusive_Data [0 ] 0
|
||||
NO_DW_B_W All_acks_and_data_no_sharers [0 ] 0
|
||||
NO_DW_B_W GETF [0 ] 0
|
||||
|
||||
NO_DR_B_W GETX [0 ] 0
|
||||
NO_DR_B_W GETS [0 ] 0
|
||||
@@ -730,6 +860,7 @@ NO_DR_B_W Shared_Ack [0 ] 0
|
||||
NO_DR_B_W Shared_Data [0 ] 0
|
||||
NO_DR_B_W Data [0 ] 0
|
||||
NO_DR_B_W Exclusive_Data [0 ] 0
|
||||
NO_DR_B_W GETF [0 ] 0
|
||||
|
||||
NO_DR_B_D GETX [0 ] 0
|
||||
NO_DR_B_D GETS [0 ] 0
|
||||
@@ -745,6 +876,7 @@ NO_DR_B_D Exclusive_Data [0 ] 0
|
||||
NO_DR_B_D All_acks_and_shared_data [0 ] 0
|
||||
NO_DR_B_D All_acks_and_owner_data [0 ] 0
|
||||
NO_DR_B_D All_acks_and_data_no_sharers [0 ] 0
|
||||
NO_DR_B_D GETF [0 ] 0
|
||||
|
||||
NO_DR_B GETX [0 ] 0
|
||||
NO_DR_B GETS [0 ] 0
|
||||
@@ -760,6 +892,7 @@ NO_DR_B Exclusive_Data [0 ] 0
|
||||
NO_DR_B All_acks_and_shared_data [0 ] 0
|
||||
NO_DR_B All_acks_and_owner_data [0 ] 0
|
||||
NO_DR_B All_acks_and_data_no_sharers [0 ] 0
|
||||
NO_DR_B GETF [0 ] 0
|
||||
|
||||
NO_DW_W GETX [0 ] 0
|
||||
NO_DW_W GETS [0 ] 0
|
||||
@@ -768,6 +901,7 @@ NO_DW_W Pf_Replacement [0 ] 0
|
||||
NO_DW_W DMA_READ [0 ] 0
|
||||
NO_DW_W DMA_WRITE [0 ] 0
|
||||
NO_DW_W Memory_Ack [0 ] 0
|
||||
NO_DW_W GETF [0 ] 0
|
||||
|
||||
O_DR_B_W GETX [0 ] 0
|
||||
O_DR_B_W GETS [0 ] 0
|
||||
@@ -778,6 +912,7 @@ O_DR_B_W DMA_WRITE [0 ] 0
|
||||
O_DR_B_W Memory_Data [0 ] 0
|
||||
O_DR_B_W Ack [0 ] 0
|
||||
O_DR_B_W Shared_Ack [0 ] 0
|
||||
O_DR_B_W GETF [0 ] 0
|
||||
|
||||
O_DR_B GETX [0 ] 0
|
||||
O_DR_B GETS [0 ] 0
|
||||
@@ -789,6 +924,7 @@ O_DR_B Ack [0 ] 0
|
||||
O_DR_B Shared_Ack [0 ] 0
|
||||
O_DR_B All_acks_and_owner_data [0 ] 0
|
||||
O_DR_B All_acks_and_data_no_sharers [0 ] 0
|
||||
O_DR_B GETF [0 ] 0
|
||||
|
||||
WB GETX [0 ] 0
|
||||
WB GETS [0 ] 0
|
||||
@@ -801,6 +937,7 @@ WB Writeback_Exclusive_Dirty [767 ] 767
|
||||
WB Pf_Replacement [0 ] 0
|
||||
WB DMA_READ [0 ] 0
|
||||
WB DMA_WRITE [0 ] 0
|
||||
WB GETF [0 ] 0
|
||||
|
||||
WB_O_W GETX [0 ] 0
|
||||
WB_O_W GETS [0 ] 0
|
||||
@@ -809,6 +946,7 @@ WB_O_W Pf_Replacement [0 ] 0
|
||||
WB_O_W DMA_READ [0 ] 0
|
||||
WB_O_W DMA_WRITE [0 ] 0
|
||||
WB_O_W Memory_Ack [0 ] 0
|
||||
WB_O_W GETF [0 ] 0
|
||||
|
||||
WB_E_W GETX [0 ] 0
|
||||
WB_E_W GETS [1 ] 1
|
||||
@@ -816,4 +954,22 @@ WB_E_W PUT [0 ] 0
|
||||
WB_E_W Pf_Replacement [0 ] 0
|
||||
WB_E_W DMA_READ [0 ] 0
|
||||
WB_E_W DMA_WRITE [0 ] 0
|
||||
WB_E_W Memory_Ack
|
||||
WB_E_W Memory_Ack [767 ] 767
|
||||
WB_E_W GETF [0 ] 0
|
||||
|
||||
NO_F GETX [0 ] 0
|
||||
NO_F GETS [0 ] 0
|
||||
NO_F PUT [0 ] 0
|
||||
NO_F UnblockM [0 ] 0
|
||||
NO_F Pf_Replacement [0 ] 0
|
||||
NO_F GETF [0 ] 0
|
||||
NO_F PUTF [0 ] 0
|
||||
|
||||
NO_F_W GETX [0 ] 0
|
||||
NO_F_W GETS [0 ] 0
|
||||
NO_F_W PUT [0 ] 0
|
||||
NO_F_W Pf_Replacement [0 ] 0
|
||||
NO_F_W DMA_READ [0 ] 0
|
||||
NO_F_W DMA_WRITE [0 ] 0
|
||||
NO_F_W Memory_Data [0 ] 0
|
||||
NO_F_W GETF
|
||||
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Feb 8 2011 17:56:59
|
||||
M5 revision 685719afafe6+ 7938+ default tip brad/increase_ruby_mem_test_threshold qtip
|
||||
M5 started Feb 8 2011 17:57:03
|
||||
M5 executing on SC2B0617
|
||||
M5 compiled Apr 19 2011 12:09:47
|
||||
M5 started Apr 19 2011 12:09:50
|
||||
M5 executing on maize
|
||||
command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
@@ -1,8 +1,8 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_mem_usage 212552 # Number of bytes of host memory used
|
||||
host_seconds 0.12 # Real time elapsed on the host
|
||||
host_tick_rate 1803209 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 210780 # Number of bytes of host memory used
|
||||
host_seconds 0.07 # Real time elapsed on the host
|
||||
host_tick_rate 3205678 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_seconds 0.000211 # Number of seconds simulated
|
||||
sim_ticks 210961 # Number of ticks simulated
|
||||
|
||||
@@ -104,6 +104,7 @@ deadlock_threshold=500000
|
||||
icache=system.ruby.cpu_ruby_ports.dcache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_network_tester=false
|
||||
using_ruby_tester=true
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
@@ -181,6 +182,7 @@ warmup_length=100000
|
||||
|
||||
[system.tester]
|
||||
type=RubyTester
|
||||
check_flush=false
|
||||
checks_to_complete=100
|
||||
deadlock_threshold=50000
|
||||
wakeup_frequency=10
|
||||
|
||||
@@ -34,7 +34,7 @@ periodic_stats_period: 1000000
|
||||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Feb/07/2011 01:47:37
|
||||
Real time: Apr/19/2011 11:58:24
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
@@ -43,18 +43,18 @@ Elapsed_time_in_minutes: 0
|
||||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.3
|
||||
Virtual_time_in_minutes: 0.005
|
||||
Virtual_time_in_hours: 8.33333e-05
|
||||
Virtual_time_in_days: 3.47222e-06
|
||||
Virtual_time_in_seconds: 0.16
|
||||
Virtual_time_in_minutes: 0.00266667
|
||||
Virtual_time_in_hours: 4.44444e-05
|
||||
Virtual_time_in_days: 1.85185e-06
|
||||
|
||||
Ruby_current_time: 281031
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 281031
|
||||
|
||||
mbytes_resident: 34.3867
|
||||
mbytes_total: 225.355
|
||||
resident_ratio: 0.152606
|
||||
mbytes_resident: 35.2539
|
||||
mbytes_total: 205.707
|
||||
resident_ratio: 0.171398
|
||||
|
||||
ruby_cycles_executed: [ 281032 ]
|
||||
|
||||
@@ -70,9 +70,9 @@ sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1014 average: 15.7801
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 32 max: 6068 count: 999 average: 4453.7 | standard deviation: 529.325 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 1 0 0 0 0 1 1 1 0 1 0 1 1 2 5 0 4 1 2 6 3 6 5 6 4 7 8 11 10 20 9 19 17 13 22 23 30 23 21 22 25 31 27 31 39 35 22 20 39 25 30 27 25 23 23 19 22 10 24 20 22 19 19 12 21 14 12 11 5 8 6 0 3 2 0 2 0 2 0 1 0 0 0 0 2 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 32 max: 5702 count: 52 average: 4674.27 | standard deviation: 454.241 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 0 2 0 0 1 3 4 0 0 0 0 1 0 1 1 1 0 0 1 0 1 0 2 2 0 3 2 0 3 0 3 1 3 3 1 1 3 2 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_LD: [binsize: 32 max: 5245 count: 48 average: 4523.02 | standard deviation: 319.516 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 2 1 1 2 3 1 2 1 1 0 4 1 0 2 1 2 4 2 0 1 1 0 1 1 2 4 1 1 0 0 0 0 0 1 0 1 ]
|
||||
miss_latency_ST: [binsize: 32 max: 6068 count: 899 average: 4437.24 | standard deviation: 539.424 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 1 0 0 0 0 1 1 1 0 1 0 1 1 2 5 0 4 1 2 6 3 6 4 6 4 7 7 11 9 18 9 16 16 12 19 19 25 21 18 21 23 29 26 30 34 33 22 18 37 23 25 25 23 20 22 16 19 9 19 16 18 17 16 9 20 13 9 8 4 7 6 0 3 2 0 1 0 2 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 ]
|
||||
miss_latency_IFETCH: [binsize: 32 max: 5702 count: 52 average: 4674.27 | standard deviation: 454.241 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 0 2 0 0 1 3 4 0 0 0 0 1 0 1 1 1 0 0 1 0 1 0 2 2 0 3 2 0 3 0 3 1 3 3 1 1 3 2 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_L1Cache: [binsize: 32 max: 4572 count: 43 average: 3768.3 | standard deviation: 359.401 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 0 1 0 2 2 0 3 1 0 2 2 1 1 3 1 2 1 1 0 4 1 3 0 2 0 0 1 0 0 0 0 0 0 0 2 0 0 0 2 ]
|
||||
miss_latency_Directory: [binsize: 32 max: 6068 count: 956 average: 4484.53 | standard deviation: 514.797 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 0 1 0 2 4 1 5 4 3 3 5 7 10 10 16 8 16 17 11 22 23 29 23 21 22 25 31 27 31 37 35 22 20 37 25 30 27 25 23 23 19 22 10 24 20 22 19 19 12 21 14 12 11 5 8 6 0 3 2 0 2 0 2 0 1 0 0 0 0 2 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 ]
|
||||
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
@@ -85,12 +85,12 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: N
|
||||
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
imcomplete_dir_Times: 956
|
||||
miss_latency_IFETCH_L1Cache: [binsize: 32 max: 4022 count: 1 average: 4022 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 32 max: 5702 count: 51 average: 4687.06 | standard deviation: 449.206 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 0 1 0 0 1 3 4 0 0 0 0 1 0 1 1 1 0 0 1 0 1 0 2 2 0 3 2 0 3 0 3 1 3 3 1 1 3 2 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_LD_L1Cache: [binsize: 32 max: 3964 count: 1 average: 3964 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_LD_Directory: [binsize: 32 max: 5245 count: 47 average: 4534.91 | standard deviation: 312.044 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 2 1 1 2 3 1 2 1 1 0 4 1 0 2 1 2 4 2 0 1 1 0 1 1 2 4 1 1 0 0 0 0 0 1 0 1 ]
|
||||
miss_latency_ST_L1Cache: [binsize: 32 max: 4572 count: 41 average: 3757.34 | standard deviation: 364.607 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 0 1 0 2 2 0 3 1 0 2 2 1 1 3 1 2 1 1 0 3 1 2 0 2 0 0 1 0 0 0 0 0 0 0 2 0 0 0 2 ]
|
||||
miss_latency_ST_Directory: [binsize: 32 max: 6068 count: 858 average: 4469.73 | standard deviation: 524.902 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 0 1 0 2 4 1 5 3 3 3 5 6 10 9 15 8 14 16 10 19 19 24 21 18 21 23 29 26 30 32 33 22 18 35 23 25 25 23 20 22 16 19 9 19 16 18 17 16 9 20 13 9 8 4 7 6 0 3 2 0 1 0 2 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 ]
|
||||
miss_latency_IFETCH_L1Cache: [binsize: 32 max: 4022 count: 1 average: 4022 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_IFETCH_Directory: [binsize: 32 max: 5702 count: 51 average: 4687.06 | standard deviation: 449.206 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 0 1 0 0 1 3 4 0 0 0 0 1 0 1 1 1 0 0 1 0 1 0 2 2 0 3 2 0 3 0 3 1 3 3 1 1 3 2 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
@@ -122,7 +122,7 @@ Resource Usage
|
||||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 9878
|
||||
page_reclaims: 9324
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
@@ -181,7 +181,7 @@ Cache Stats: system.ruby.cpu_ruby_ports.dcache
|
||||
system.ruby.cpu_ruby_ports.dcache_request_type_ST: 89.7597%
|
||||
system.ruby.cpu_ruby_ports.dcache_request_type_IFETCH: 5.32915%
|
||||
|
||||
system.ruby.cpu_ruby_ports.dcache_access_mode_type_SupervisorMode: 957 100%
|
||||
system.ruby.cpu_ruby_ports.dcache_access_mode_type_Supervisor: 957 100%
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
|
||||
@@ -5,10 +5,9 @@ The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Feb 7 2011 01:47:18
|
||||
M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
|
||||
M5 started Feb 7 2011 01:47:37
|
||||
M5 executing on burrito
|
||||
M5 compiled Apr 19 2011 11:52:53
|
||||
M5 started Apr 19 2011 11:58:24
|
||||
M5 executing on maize
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
|
||||
@@ -1,8 +1,8 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_mem_usage 230768 # Number of bytes of host memory used
|
||||
host_seconds 0.30 # Real time elapsed on the host
|
||||
host_tick_rate 934733 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 210648 # Number of bytes of host memory used
|
||||
host_seconds 0.05 # Real time elapsed on the host
|
||||
host_tick_rate 5633491 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_seconds 0.000281 # Number of seconds simulated
|
||||
sim_ticks 281031 # Number of ticks simulated
|
||||
|
||||
Reference in New Issue
Block a user