Small fixes to O3 model.

cpu/o3/alpha_dyn_inst.hh:
    Set the instResult using a function on the base dyn inst.
cpu/o3/bpred_unit_impl.hh:
    Don't need to reset the state.
cpu/o3/commit_impl.hh:
    Mark instructions as completed.

    Wait until all stores are written back to handle a fault.
cpu/o3/cpu.cc:
    Clear instruction lists when switching out.
cpu/o3/lsq_unit.hh:
    Allow wbEvent to be set externally.
cpu/o3/lsq_unit_impl.hh:
    Mark instructions as completed properly.  Also use events for writing back stores even if there is a hit in the dcache.

--HG--
extra : convert_revision : 172ad088b75ac31e848a5040633152b5c051444c

cpu/o3/commit_impl.hh

@@ -1117,6 +1117,10 @@ head_inst->isWriteBarrier())*/
         panic("Barrier instructions are not handled yet.\n");
     }
 
+    if (!head_inst->isStore()) {
+        head_inst->setCompleted();
+    }
+
     // Check if the instruction caused a fault.  If so, trap.
     Fault inst_fault = head_inst->getFault();
 
@@ -1126,6 +1130,11 @@ head_inst->isWriteBarrier())*/
             DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
                     head_inst->seqNum, head_inst->readPC());
 
+            if (iewStage->hasStoresToWB()) {
+                DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
+                return false;
+            }
+
             assert(!thread[tid]->inSyscall);
 
             thread[tid]->inSyscall = true;