Fixes to get prefetching working again.
Apparently we broke it with the cache rewrite and never noticed. Thanks to Bao Yungang <baoyungang@gmail.com> for a significant part of these changes (and for inspiring me to work on the rest). Some other overdue cleanup on the prefetch code too.
This commit is contained in:
12
src/mem/cache/BaseCache.py
vendored
12
src/mem/cache/BaseCache.py
vendored
@@ -52,12 +52,10 @@ class BaseCache(MemObject):
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two_queue = Param.Bool(False,
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"whether the lifo should have two queue replacement")
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write_buffers = Param.Int(8, "number of write buffers")
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prefetch_miss = Param.Bool(False,
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"wheter you are using the hardware prefetcher from Miss stream")
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prefetch_access = Param.Bool(False,
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"wheter you are using the hardware prefetcher from Access stream")
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prefetch_on_access = Param.Bool(False,
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"notify the hardware prefetcher on every access (not just misses)")
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prefetcher_size = Param.Int(100,
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"Number of entries in the harware prefetch queue")
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"Number of entries in the hardware prefetch queue")
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prefetch_past_page = Param.Bool(False,
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"Allow prefetches to cross virtual page boundaries")
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prefetch_serial_squash = Param.Bool(False,
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@@ -69,9 +67,9 @@ class BaseCache(MemObject):
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prefetch_policy = Param.Prefetch('none',
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"Type of prefetcher to use")
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prefetch_cache_check_push = Param.Bool(True,
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"Check if in cash on push or pop of prefetch queue")
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"Check if in cache on push or pop of prefetch queue")
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prefetch_use_cpu_id = Param.Bool(True,
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"Use the CPU ID to seperate calculations of prefetches")
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"Use the CPU ID to separate calculations of prefetches")
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prefetch_data_accesses_only = Param.Bool(False,
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"Only prefetch on data not on instruction accesses")
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cpu_side = Port("Port on side closer to CPU")
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