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arch, cpu: Remove float type accessors.

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Use the binary accessors instead.

Change-Id: Iff1877e92c79df02b3d13635391a8c2f025776a2
Reviewed-on: https://gem5-review.googlesource.com/c/14457
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
This commit is contained in:
Gabe Black
2018-11-19 17:20:31 -08:00
parent 67d58e8182
commit 88bbabe93f
21 changed files with 17 additions and 247 deletions
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2
src/cpu/simple/base.cc
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@@ -493,7 +493,7 @@ BaseSimpleCPU::preExecute()
// maintain $r0 semantics
thread->setIntReg(ZeroReg, 0);
#if THE_ISA == ALPHA_ISA
thread->setFloatReg(ZeroReg, 0.0);
thread->setFloatRegBits(ZeroReg, 0);
#endif // ALPHA_ISA
// check for instruction-count-based events

19
src/cpu/simple/exec_context.hh
View File

@@ -191,15 +191,6 @@ class SimpleExecContext : public ExecContext {
thread->setIntReg(reg.index(), val);
}
/** Reads a floating point register of single register width. */
FloatReg readFloatRegOperand(const StaticInst *si, int idx) override
{
numFpRegReads++;
const RegId& reg = si->srcRegIdx(idx);
assert(reg.isFloatReg());
return thread->readFloatReg(reg.index());
}
/** Reads a floating point register in its binary format, instead
* of by value. */
FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) override
@@ -210,16 +201,6 @@ class SimpleExecContext : public ExecContext {
return thread->readFloatRegBits(reg.index());
}
/** Sets a floating point register of single width to a value. */
void setFloatRegOperand(const StaticInst *si, int idx,
FloatReg val) override
{
numFpRegWrites++;
const RegId& reg = si->destRegIdx(idx);
assert(reg.isFloatReg());
thread->setFloatReg(reg.index(), val);
}
/** Sets the bits of a floating point register of single width
* to a binary value. */
void setFloatRegOperandBits(const StaticInst *si, int idx,