I missed a couple of WithEffects, this should do it

--HG--
extra : convert_revision : 19fce78a19b27b7ccb5e3653a64b46e6d5292915
This commit is contained in:
Ali Saidi
2007-03-07 21:51:44 -05:00
parent 2f7a4e1d1b
commit 87fb0eb8de
7 changed files with 20 additions and 22 deletions

View File

@@ -125,7 +125,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
}
/** Reads a miscellaneous register. */
TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
TheISA::MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx)
{
return this->cpu->readMiscRegNoEffect(
si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
@@ -135,7 +135,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
/** Reads a misc. register, including any side-effects the read
* might have as defined by the architecture.
*/
TheISA::MiscReg readMiscRegOperandWithEffect(const StaticInst *si, int idx)
TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
{
return this->cpu->readMiscReg(
si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
@@ -143,7 +143,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
}
/** Sets a misc. register. */
void setMiscRegOperand(const StaticInst * si, int idx, const MiscReg &val)
void setMiscRegOperandNoEffect(const StaticInst * si, int idx, const MiscReg &val)
{
this->instResult.integer = val;
return this->cpu->setMiscRegNoEffect(
@@ -154,7 +154,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
/** Sets a misc. register, including any side-effects the write
* might have as defined by the architecture.
*/
void setMiscRegOperandWithEffect(const StaticInst *si, int idx,
void setMiscRegOperand(const StaticInst *si, int idx,
const MiscReg &val)
{
return this->cpu->setMiscReg(

View File

@@ -107,7 +107,7 @@ class SparcDynInst : public BaseDynInst<Impl>
}
/** Reads a miscellaneous register. */
TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
TheISA::MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx)
{
return this->cpu->readMiscRegNoEffect(
si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
@@ -117,7 +117,7 @@ class SparcDynInst : public BaseDynInst<Impl>
/** Reads a misc. register, including any side-effects the read
* might have as defined by the architecture.
*/
TheISA::MiscReg readMiscRegOperandWithEffect(const StaticInst *si, int idx)
TheISA::MiscReg readMiscRegOperand(const StaticInst *si, int idx)
{
return this->cpu->readMiscReg(
si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
@@ -125,7 +125,7 @@ class SparcDynInst : public BaseDynInst<Impl>
}
/** Sets a misc. register. */
void setMiscRegOperand(const StaticInst * si,
void setMiscRegOperandNoEffect(const StaticInst * si,
int idx, const TheISA::MiscReg &val)
{
this->instResult.integer = val;
@@ -137,7 +137,7 @@ class SparcDynInst : public BaseDynInst<Impl>
/** Sets a misc. register, including any side-effects the write
* might have as defined by the architecture.
*/
void setMiscRegOperandWithEffect(
void setMiscRegOperand(
const StaticInst *si, int idx, const TheISA::MiscReg &val)
{
return this->cpu->setMiscReg(

View File

@@ -304,25 +304,25 @@ class BaseSimpleCPU : public BaseCPU
return thread->setMiscReg(misc_reg, val);
}
MiscReg readMiscRegOperand(const StaticInst *si, int idx)
MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
return thread->readMiscRegNoEffect(reg_idx);
}
MiscReg readMiscRegOperandWithEffect(const StaticInst *si, int idx)
MiscReg readMiscRegOperand(const StaticInst *si, int idx)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
return thread->readMiscReg(reg_idx);
}
void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val)
void setMiscRegOperandNoEffect(const StaticInst *si, int idx, const MiscReg &val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
return thread->setMiscRegNoEffect(reg_idx, val);
}
void setMiscRegOperandWithEffect(
void setMiscRegOperand(
const StaticInst *si, int idx, const MiscReg &val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;