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Hand merge. Stuff probably doesn't compile.

Browse Source 
--HG--
rename : arch/alpha/isa_desc => arch/alpha/isa/main.isa
rename : arch/alpha/alpha_linux_process.cc => arch/alpha/linux/process.cc
rename : arch/alpha/alpha_linux_process.hh => arch/alpha/linux/process.hh
rename : arch/alpha/alpha_tru64_process.cc => arch/alpha/tru64/process.cc
rename : arch/alpha/alpha_tru64_process.hh => arch/alpha/tru64/process.hh
rename : cpu/exec_context.cc => cpu/cpu_exec_context.cc
rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh
extra : convert_revision : 7d1efcedd708815d985a951f6f010fbd83dc27e8
This commit is contained in:
Gabe Black
2006-03-09 18:35:28 -05:00
parent 3adb45144a 7b283dbc09
commit 872bbdfc33
243 changed files with 19901 additions and 8800 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
dev/alpha_access.h
View File

@@ -33,7 +33,7 @@
* System Console Memory Mapped Register Definition
*/
#define ALPHA_ACCESS_VERSION (1303)
#define ALPHA_ACCESS_VERSION (1305)
#ifdef CONSOLE
typedef unsigned uint32_t;
@@ -67,9 +67,7 @@ struct AlphaAccess
uint64_t inputChar; // 68: Placeholder for input
// MP boot
uint64_t bootStrapImpure; // 70:
uint32_t bootStrapCPU; // 78:
uint32_t align2; // 7C: Dummy placeholder for alignment
uint64_t cpuStack[64]; // 70:
};
#endif // __ALPHA_ACCESS_H__

61
dev/alpha_console.cc
View File

@@ -34,6 +34,7 @@
#include <cstdio>
#include <string>
#include "arch/alpha/system.hh"
#include "base/inifile.hh"
#include "base/str.hh"
#include "base/trace.hh"
@@ -50,12 +51,12 @@
#include "mem/functional/physical.hh"
#include "sim/builder.hh"
#include "sim/sim_object.hh"
#include "sim/system.hh"
using namespace std;
using namespace AlphaISA;
AlphaConsole::AlphaConsole(const string &name, SimConsole *cons, SimpleDisk *d,
System *s, BaseCPU *c, Platform *p,
AlphaSystem *s, BaseCPU *c, Platform *p,
MemoryController *mmu, Addr a,
HierParams *hier, Bus *pio_bus)
: PioDevice(name, p), disk(d), console(cons), system(s), cpu(c), addr(a)
@@ -80,9 +81,7 @@ AlphaConsole::AlphaConsole(const string &name, SimConsole *cons, SimpleDisk *d,
alphaAccess->diskOperation = 0;
alphaAccess->outputChar = 0;
alphaAccess->inputChar = 0;
alphaAccess->bootStrapImpure = 0;
alphaAccess->bootStrapCPU = 0;
alphaAccess->align2 = 0;
bzero(alphaAccess->cpuStack, sizeof(alphaAccess->cpuStack));
system->setAlphaAccess(addr);
}
@@ -122,9 +121,6 @@ AlphaConsole::read(MemReqPtr &req, uint8_t *data)
case offsetof(AlphaAccess, numCPUs):
*(uint32_t*)data = alphaAccess->numCPUs;
break;
case offsetof(AlphaAccess, bootStrapCPU):
*(uint32_t*)data = alphaAccess->bootStrapCPU;
break;
case offsetof(AlphaAccess, intrClockFrequency):
*(uint32_t*)data = alphaAccess->intrClockFrequency;
break;
@@ -175,18 +171,21 @@ AlphaConsole::read(MemReqPtr &req, uint8_t *data)
case offsetof(AlphaAccess, outputChar):
*(uint64_t*)data = alphaAccess->outputChar;
break;
case offsetof(AlphaAccess, bootStrapImpure):
*(uint64_t*)data = alphaAccess->bootStrapImpure;
break;
default:
panic("Unknown 64bit access, %#x\n", daddr);
int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) /
sizeof(alphaAccess->cpuStack[0]);
if (cpunum >= 0 && cpunum < 64)
*(uint64_t*)data = alphaAccess->cpuStack[cpunum];
else
panic("Unknown 64bit access, %#x\n", daddr);
}
break;
default:
return Machine_Check_Fault;
return genMachineCheckFault();
}
return No_Fault;
return NoFault;
}
Fault
@@ -203,7 +202,7 @@ AlphaConsole::write(MemReqPtr &req, const uint8_t *data)
val = *(uint64_t *)data;
break;
default:
return Machine_Check_Fault;
return genMachineCheckFault();
}
Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
@@ -239,27 +238,21 @@ AlphaConsole::write(MemReqPtr &req, const uint8_t *data)
console->out((char)(val & 0xff));
break;
case offsetof(AlphaAccess, bootStrapImpure):
alphaAccess->bootStrapImpure = val;
break;
case offsetof(AlphaAccess, bootStrapCPU):
warn("%d: Trying to launch another CPU!", curTick);
assert(val > 0 && "Must not access primary cpu");
other_xc = req->xc->system->execContexts[val];
other_xc->regs.intRegFile[16] = val;
other_xc->regs.ipr[TheISA::IPR_PALtemp16] = val;
other_xc->regs.intRegFile[0] = val;
other_xc->regs.intRegFile[30] = alphaAccess->bootStrapImpure;
other_xc->activate(); //Start the cpu
break;
default:
return Machine_Check_Fault;
int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) /
sizeof(alphaAccess->cpuStack[0]);
warn("%d: Trying to launch CPU number %d!", curTick, cpunum);
assert(val > 0 && "Must not access primary cpu");
if (cpunum >= 0 && cpunum < 64)
alphaAccess->cpuStack[cpunum] = val;
else
panic("Unknown 64bit access, %#x\n", daddr);
}
return No_Fault;
return NoFault;
}
Tick
@@ -287,8 +280,7 @@ AlphaConsole::Access::serialize(ostream &os)
SERIALIZE_SCALAR(diskOperation);
SERIALIZE_SCALAR(outputChar);
SERIALIZE_SCALAR(inputChar);
SERIALIZE_SCALAR(bootStrapImpure);
SERIALIZE_SCALAR(bootStrapCPU);
SERIALIZE_ARRAY(cpuStack,64);
}
void
@@ -310,8 +302,7 @@ AlphaConsole::Access::unserialize(Checkpoint *cp, const std::string &section)
UNSERIALIZE_SCALAR(diskOperation);
UNSERIALIZE_SCALAR(outputChar);
UNSERIALIZE_SCALAR(inputChar);
UNSERIALIZE_SCALAR(bootStrapImpure);
UNSERIALIZE_SCALAR(bootStrapCPU);
UNSERIALIZE_ARRAY(cpuStack, 64);
}
void
@@ -332,7 +323,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole)
SimObjectParam<SimpleDisk *> disk;
SimObjectParam<MemoryController *> mmu;
Param<Addr> addr;
SimObjectParam<System *> system;
SimObjectParam<AlphaSystem *> system;
SimObjectParam<BaseCPU *> cpu;
SimObjectParam<Platform *> platform;
SimObjectParam<Bus*> pio_bus;

9
dev/alpha_console.hh
View File

@@ -41,8 +41,9 @@
class BaseCPU;
class SimConsole;
class System;
class AlphaSystem;
class SimpleDisk;
class MemoryController;
/**
* Memory mapped interface to the system console. This device
@@ -90,18 +91,18 @@ class AlphaConsole : public PioDevice
SimConsole *console;
/** a pointer to the system we are running in */
System *system;
AlphaSystem *system;
/** a pointer to the CPU boot cpu */
BaseCPU *cpu;
Addr addr;
static const Addr size = 0x80; // equal to sizeof(alpha_access);
static const Addr size = sizeof(struct AlphaAccess);
public:
/** Standard Constructor */
AlphaConsole(const std::string &name, SimConsole *cons, SimpleDisk *d,
System *s, BaseCPU *c, Platform *platform,
AlphaSystem *s, BaseCPU *c, Platform *platform,
MemoryController *mmu, Addr addr,
HierParams *hier, Bus *pio_bus);

5
dev/baddev.cc
View File

@@ -46,6 +46,7 @@
#include "sim/system.hh"
using namespace std;
using namespace TheISA;
BadDevice::BadDevice(const string &name, Addr a, MemoryController *mmu,
HierParams *hier, Bus *pio_bus, const string &devicename)
@@ -66,14 +67,14 @@ BadDevice::read(MemReqPtr &req, uint8_t *data)
{
panic("Device %s not imlpmented\n", devname);
return No_Fault;
return NoFault;
}
Fault
BadDevice::write(MemReqPtr &req, const uint8_t *data)
{
panic("Device %s not imlpmented\n", devname);
return No_Fault;
return NoFault;
}
Tick

2
dev/baddev.hh
View File

@@ -37,6 +37,8 @@
#include "base/range.hh"
#include "dev/io_device.hh"
class MemoryController;
/**
* BadDevice
* This device just panics when accessed. It is supposed to warn

2
dev/disk_image.cc
View File

@@ -46,7 +46,7 @@
#include "dev/disk_image.hh"
#include "sim/builder.hh"
#include "sim/sim_exit.hh"
#include "targetarch/byte_swap.hh"
#include "sim/byteswap.hh"
using namespace std;

11
dev/ide_ctrl.cc
View File

@@ -48,6 +48,7 @@
#include "sim/sim_object.hh"
using namespace std;
using namespace TheISA;
////
// Initialization and destruction
@@ -401,7 +402,7 @@ IdeController::read(MemReqPtr &req, uint8_t *data)
parseAddr(req->paddr, offset, channel, reg_type);
if (!io_enabled)
return No_Fault;
return NoFault;
switch (reg_type) {
case BMI_BLOCK:
@@ -457,7 +458,7 @@ IdeController::read(MemReqPtr &req, uint8_t *data)
DPRINTF(IdeCtrl, "read from offset: %#x size: %#x data: %#x\n",
offset, req->size, *(uint32_t*)data);
return No_Fault;
return NoFault;
}
Fault
@@ -472,12 +473,12 @@ IdeController::write(MemReqPtr &req, const uint8_t *data)
parseAddr(req->paddr, offset, channel, reg_type);
if (!io_enabled)
return No_Fault;
return NoFault;
switch (reg_type) {
case BMI_BLOCK:
if (!bm_enabled)
return No_Fault;
return NoFault;
switch (offset) {
// Bus master IDE command register
@@ -627,7 +628,7 @@ IdeController::write(MemReqPtr &req, const uint8_t *data)
DPRINTF(IdeCtrl, "write to offset: %#x size: %#x data: %#x\n",
offset, req->size, *(uint32_t*)data);
return No_Fault;
return NoFault;
}
////

3
dev/ide_disk.cc
View File

@@ -50,9 +50,10 @@
#include "sim/builder.hh"
#include "sim/sim_object.hh"
#include "sim/root.hh"
#include "targetarch/isa_traits.hh"
#include "arch/isa_traits.hh"
using namespace std;
using namespace TheISA;
IdeDisk::IdeDisk(const string &name, DiskImage *img, PhysicalMemory *phys,
int id, Tick delay)

13
dev/isa_fake.cc
View File

@@ -45,6 +45,7 @@
#include "sim/system.hh"
using namespace std;
using namespace TheISA;
IsaFake::IsaFake(const string &name, Addr a, MemoryController *mmu,
HierParams *hier, Bus *pio_bus, Addr size)
@@ -73,23 +74,23 @@ IsaFake::read(MemReqPtr &req, uint8_t *data)
case sizeof(uint64_t):
*(uint64_t*)data = 0xFFFFFFFFFFFFFFFFULL;
return No_Fault;
return NoFault;
case sizeof(uint32_t):
*(uint32_t*)data = 0xFFFFFFFF;
return No_Fault;
return NoFault;
case sizeof(uint16_t):
*(uint16_t*)data = 0xFFFF;
return No_Fault;
return NoFault;
case sizeof(uint8_t):
*(uint8_t*)data = 0xFF;
return No_Fault;
return NoFault;
default:
panic("invalid access size(?) for PCI configspace!\n");
}
DPRINTFN("Isa FakeSMC ERROR: read daddr=%#x size=%d\n", daddr, req->size);
return No_Fault;
return NoFault;
}
Fault
@@ -100,7 +101,7 @@ IsaFake::write(MemReqPtr &req, const uint8_t *data)
//:Addr daddr = (req->paddr & addr_mask) >> 6;
return No_Fault;
return NoFault;
}
Tick

2
dev/isa_fake.hh
View File

@@ -37,6 +37,8 @@
#include "base/range.hh"
#include "dev/io_device.hh"
class MemoryController;
/**
* IsaFake is a device that returns -1 on all reads and
* accepts all writes. It is meant to be placed at an address range

81
dev/ns_gige.cc
View File

@@ -49,7 +49,7 @@
#include "sim/debug.hh"
#include "sim/host.hh"
#include "sim/stats.hh"
#include "targetarch/vtophys.hh"
#include "arch/vtophys.hh"
const char *NsRxStateStrings[] =
{
@@ -84,6 +84,7 @@ const char *NsDmaState[] =
using namespace std;
using namespace Net;
using namespace TheISA;
///////////////////////////////////////////////////////////////////////
//
@@ -130,8 +131,6 @@ NSGigE::NSGigE(Params *p)
} else if (p->payload_bus)
panic("Must define a header bus if defining a payload bus");
pioDelayWrite = p->pio_delay_write && pioInterface;
intrDelay = p->intr_delay;
dmaReadDelay = p->dma_read_delay;
dmaWriteDelay = p->dma_write_delay;
@@ -575,14 +574,14 @@ NSGigE::read(MemReqPtr &req, uint8_t *data)
panic("Accessing reserved register");
} else if (daddr > RESERVED && daddr <= 0x3FC) {
readConfig(daddr & 0xff, req->size, data);
return No_Fault;
return NoFault;
} else if (daddr >= MIB_START && daddr <= MIB_END) {
// don't implement all the MIB's. hopefully the kernel
// doesn't actually DEPEND upon their values
// MIB are just hardware stats keepers
uint32_t &reg = *(uint32_t *) data;
reg = 0;
return No_Fault;
return NoFault;
} else if (daddr > 0x3FC)
panic("Something is messed up!\n");
@@ -768,6 +767,8 @@ NSGigE::read(MemReqPtr &req, uint8_t *data)
reg |= M5REG_RX_THREAD;
if (params()->tx_thread)
reg |= M5REG_TX_THREAD;
if (params()->rss)
reg |= M5REG_RSS;
break;
default:
@@ -784,7 +785,7 @@ NSGigE::read(MemReqPtr &req, uint8_t *data)
daddr, req->size);
}
return No_Fault;
return NoFault;
}
Fault
@@ -800,17 +801,10 @@ NSGigE::write(MemReqPtr &req, const uint8_t *data)
panic("Accessing reserved register");
} else if (daddr > RESERVED && daddr <= 0x3FC) {
writeConfig(daddr & 0xff, req->size, data);
return No_Fault;
return NoFault;
} else if (daddr > 0x3FC)
panic("Something is messed up!\n");
if (pioDelayWrite) {
int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff;
if (cpu >= writeQueue.size())
writeQueue.resize(cpu + 1);
writeQueue[cpu].push_back(RegWriteData(daddr, *(uint32_t *)data));
}
if (req->size == sizeof(uint32_t)) {
uint32_t reg = *(uint32_t *)data;
uint16_t rfaddr;
@@ -823,24 +817,20 @@ NSGigE::write(MemReqPtr &req, const uint8_t *data)
if (reg & CR_TXD) {
txEnable = false;
} else if (reg & CR_TXE) {
if (!pioDelayWrite) {
txEnable = true;
txEnable = true;
// the kernel is enabling the transmit machine
if (txState == txIdle)
txKick();
}
// the kernel is enabling the transmit machine
if (txState == txIdle)
txKick();
}
if (reg & CR_RXD) {
rxEnable = false;
} else if (reg & CR_RXE) {
if (!pioDelayWrite) {
rxEnable = true;
rxEnable = true;
if (rxState == rxIdle)
rxKick();
}
if (rxState == rxIdle)
rxKick();
}
if (reg & CR_TXR)
@@ -1203,7 +1193,7 @@ NSGigE::write(MemReqPtr &req, const uint8_t *data)
panic("Invalid Request Size");
}
return No_Fault;
return NoFault;
}
void
@@ -2948,38 +2938,9 @@ NSGigE::unserialize(Checkpoint *cp, const std::string &section)
Tick
NSGigE::cacheAccess(MemReqPtr &req)
{
Addr daddr = req->paddr & 0xfff;
DPRINTF(EthernetPIO, "timing access to paddr=%#x (daddr=%#x)\n",
req->paddr, daddr);
req->paddr, req->paddr & 0xfff);
if (!pioDelayWrite || !req->cmd.isWrite())
return curTick + pioLatency;
int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff;
std::list<RegWriteData> &wq = writeQueue[cpu];
if (wq.empty())
panic("WriteQueue for cpu %d empty timing daddr=%#x", cpu, daddr);
const RegWriteData &data = wq.front();
if (data.daddr != daddr)
panic("read mismatch on cpu %d, daddr functional=%#x timing=%#x",
cpu, data.daddr, daddr);
if (daddr == CR) {
if ((data.value & (CR_TXD | CR_TXE)) == CR_TXE) {
txEnable = true;
if (txState == txIdle)
txKick();
}
if ((data.value & (CR_RXD | CR_RXE)) == CR_RXE) {
rxEnable = true;
if (rxState == rxIdle)
rxKick();
}
}
wq.pop_front();
return curTick + pioLatency;
}
@@ -3039,7 +3000,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
Param<Tick> dma_write_factor;
Param<bool> dma_no_allocate;
Param<Tick> pio_latency;
Param<bool> pio_delay_write;
Param<Tick> intr_delay;
Param<Tick> rx_delay;
@@ -3051,6 +3011,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
Param<string> hardware_address;
Param<bool> rx_thread;
Param<bool> tx_thread;
Param<bool> rss;
END_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
@@ -3080,7 +3041,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigE)
INIT_PARAM(dma_write_factor, "multiplier for dma writes"),
INIT_PARAM(dma_no_allocate, "Should DMA reads allocate cache lines"),
INIT_PARAM(pio_latency, "Programmed IO latency in bus cycles"),
INIT_PARAM(pio_delay_write, ""),
INIT_PARAM(intr_delay, "Interrupt Delay in microseconds"),
INIT_PARAM(rx_delay, "Receive Delay"),
@@ -3091,7 +3051,8 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigE)
INIT_PARAM(rx_filter, "Enable Receive Filter"),
INIT_PARAM(hardware_address, "Ethernet Hardware Address"),
INIT_PARAM(rx_thread, ""),
INIT_PARAM(tx_thread, "")
INIT_PARAM(tx_thread, ""),
INIT_PARAM(rss, "")
END_INIT_SIM_OBJECT_PARAMS(NSGigE)
@@ -3125,7 +3086,6 @@ CREATE_SIM_OBJECT(NSGigE)
params->dma_write_factor = dma_write_factor;
params->dma_no_allocate = dma_no_allocate;
params->pio_latency = pio_latency;
params->pio_delay_write = pio_delay_write;
params->intr_delay = intr_delay;
params->rx_delay = rx_delay;
@@ -3137,6 +3097,7 @@ CREATE_SIM_OBJECT(NSGigE)
params->eaddr = hardware_address;
params->rx_thread = rx_thread;
params->tx_thread = tx_thread;
params->rss = rss;
return new NSGigE(params);
}

14
dev/ns_gige.hh
View File

@@ -170,9 +170,6 @@ class NSGigE : public PciDev
static const Addr size = sizeof(dp_regs);
protected:
typedef std::deque<PacketPtr> pktbuf_t;
typedef pktbuf_t::iterator pktiter_t;
/** device register file */
dp_regs regs;
dp_rom rom;
@@ -239,15 +236,6 @@ class NSGigE : public PciDev
uint32_t rxDescCnt;
DmaState rxDmaState;
struct RegWriteData {
Addr daddr;
uint32_t value;
RegWriteData(Addr da, uint32_t val) : daddr(da), value(val) {}
};
std::vector<std::list<RegWriteData> > writeQueue;
bool pioDelayWrite;
bool extstsEnable;
/** EEPROM State Machine */
@@ -385,7 +373,6 @@ class NSGigE : public PciDev
Tick tx_delay;
Tick rx_delay;
Tick pio_latency;
bool pio_delay_write;
bool dma_desc_free;
bool dma_data_free;
Tick dma_read_delay;
@@ -398,6 +385,7 @@ class NSGigE : public PciDev
uint32_t rx_fifo_size;
bool rx_thread;
bool tx_thread;
bool rss;
bool dma_no_allocate;
};

1
dev/ns_gige_reg.h
View File

@@ -306,6 +306,7 @@
/* M5 control register */
#define M5REG_RESERVED 0xfffffffc
#define M5REG_RSS 0x00000004
#define M5REG_RX_THREAD 0x00000002
#define M5REG_TX_THREAD 0x00000001

15
dev/pciconfigall.cc
View File

@@ -47,6 +47,7 @@
#include "sim/system.hh"
using namespace std;
using namespace TheISA;
PciConfigAll::PciConfigAll(const string &name,
Addr a, MemoryController *mmu,
@@ -112,16 +113,16 @@ PciConfigAll::read(MemReqPtr &req, uint8_t *data)
switch (req->size) {
// case sizeof(uint64_t):
// *(uint64_t*)data = 0xFFFFFFFFFFFFFFFF;
// return No_Fault;
// return NoFault;
case sizeof(uint32_t):
*(uint32_t*)data = 0xFFFFFFFF;
return No_Fault;
return NoFault;
case sizeof(uint16_t):
*(uint16_t*)data = 0xFFFF;
return No_Fault;
return NoFault;
case sizeof(uint8_t):
*(uint8_t*)data = 0xFF;
return No_Fault;
return NoFault;
default:
panic("invalid access size(?) for PCI configspace!\n");
}
@@ -131,7 +132,7 @@ PciConfigAll::read(MemReqPtr &req, uint8_t *data)
case sizeof(uint16_t):
case sizeof(uint8_t):
devices[device][func]->readConfig(reg, req->size, data);
return No_Fault;
return NoFault;
default:
panic("invalid access size(?) for PCI configspace!\n");
}
@@ -140,7 +141,7 @@ PciConfigAll::read(MemReqPtr &req, uint8_t *data)
DPRINTFN("PCI Configspace ERROR: read daddr=%#x size=%d\n",
daddr, req->size);
return No_Fault;
return NoFault;
}
Fault
@@ -164,7 +165,7 @@ PciConfigAll::write(MemReqPtr &req, const uint8_t *data)
devices[device][func]->writeConfig(reg, req->size, data);
return No_Fault;
return NoFault;
}
void

4
dev/pcidev.cc
View File

@@ -72,11 +72,11 @@ PciDev::PciDev(Params *p)
Fault
PciDev::read(MemReqPtr &req, uint8_t *data)
{ return No_Fault; }
{ return NoFault; }
Fault
PciDev::write(MemReqPtr &req, const uint8_t *data)
{ return No_Fault; }
{ return NoFault; }
Fault
PciDev::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data)

6
dev/pcidev.hh
View File

@@ -260,6 +260,7 @@ class PciDev : public DmaDevice
inline Fault
PciDev::readBar(MemReqPtr &req, uint8_t *data)
{
using namespace TheISA;
if (isBAR(req->paddr, 0))
return readBar0(req, req->paddr - BARAddrs[0], data);
if (isBAR(req->paddr, 1))
@@ -272,12 +273,13 @@ PciDev::readBar(MemReqPtr &req, uint8_t *data)
return readBar4(req, req->paddr - BARAddrs[4], data);
if (isBAR(req->paddr, 5))
return readBar5(req, req->paddr - BARAddrs[5], data);
return Machine_Check_Fault;
return genMachineCheckFault();
}
inline Fault
PciDev::writeBar(MemReqPtr &req, const uint8_t *data)
{
using namespace TheISA;
if (isBAR(req->paddr, 0))
return writeBar0(req, req->paddr - BARAddrs[0], data);
if (isBAR(req->paddr, 1))
@@ -290,7 +292,7 @@ PciDev::writeBar(MemReqPtr &req, const uint8_t *data)
return writeBar4(req, req->paddr - BARAddrs[4], data);
if (isBAR(req->paddr, 5))
return writeBar5(req, req->paddr - BARAddrs[5], data);
return Machine_Check_Fault;
return genMachineCheckFault();
}
#endif // __DEV_PCIDEV_HH__

34
dev/pktfifo.cc
View File

@@ -31,6 +31,36 @@
using namespace std;
bool
PacketFifo::copyout(void *dest, int offset, int len)
{
char *data = (char *)dest;
if (offset + len >= size())
return false;
list<PacketPtr>::iterator p = fifo.begin();
list<PacketPtr>::iterator end = fifo.end();
while (len > 0) {
while (offset >= (*p)->length) {
offset -= (*p)->length;
++p;
}
if (p == end)
panic("invalid fifo");
int size = min((*p)->length - offset, len);
memcpy(data, (*p)->data, size);
offset = 0;
len -= size;
data += size;
++p;
}
return true;
}
void
PacketFifo::serialize(const string &base, ostream &os)
{
@@ -40,8 +70,8 @@ PacketFifo::serialize(const string &base, ostream &os)
paramOut(os, base + ".packets", fifo.size());
int i = 0;
std::list<PacketPtr>::iterator p = fifo.begin();
std::list<PacketPtr>::iterator end = fifo.end();
list<PacketPtr>::iterator p = fifo.begin();
list<PacketPtr>::iterator end = fifo.end();
while (p != end) {
(*p)->serialize(csprintf("%s.packet%d", base, i), os);
++p;

29
dev/pktfifo.hh
View File

@@ -127,6 +127,35 @@ class PacketFifo
fifo.erase(i);
}
bool copyout(void *dest, int offset, int len);
int countPacketsBefore(iterator end)
{
iterator i = fifo.begin();
int count = 0;
while (i != end) {
++count;
++i;
}
return count;
}
int countPacketsAfter(iterator i)
{
iterator end = fifo.end();
int count = 0;
while (i != end) {
++count;
++i;
}
return count;
}
/**
* Serialization stuff
*/

1
dev/platform.cc
View File

@@ -31,6 +31,7 @@
#include "sim/sim_exit.hh"
using namespace std;
using namespace TheISA;
Platform::Platform(const string &name, IntrControl *intctrl, PciConfigAll *pci)
: SimObject(name), intrctrl(intctrl), pciconfig(pci)

2
dev/platform.hh
View File

@@ -35,7 +35,7 @@
#define __DEV_PLATFORM_HH__
#include "sim/sim_object.hh"
#include "targetarch/isa_traits.hh"
#include "arch/isa_traits.hh"
class PciConfigAll;
class IntrControl;

22
dev/simple_disk.hh
View File

@@ -34,7 +34,7 @@
#define __DEV_SIMPLE_DISK_HH__
#include "sim/sim_object.hh"
#include "targetarch/isa_traits.hh"
#include "arch/isa_traits.hh"
class DiskImage;
class PhysicalMemory;
@@ -44,19 +44,19 @@ class PhysicalMemory;
*/
class SimpleDisk : public SimObject
{
public:
typedef uint64_t baddr_t;
public:
typedef uint64_t baddr_t;
protected:
PhysicalMemory *physmem;
DiskImage *image;
protected:
PhysicalMemory *physmem;
DiskImage *image;
public:
SimpleDisk(const std::string &name, PhysicalMemory *pmem, DiskImage *img);
~SimpleDisk();
public:
SimpleDisk(const std::string &name, PhysicalMemory *pmem, DiskImage *img);
~SimpleDisk();
void read(Addr addr, baddr_t block, int count) const;
void write(Addr addr, baddr_t block, int count);
void read(Addr addr, baddr_t block, int count) const;
void write(Addr addr, baddr_t block, int count);
};
#endif // __DEV_SIMPLE_DISK_HH__

82
dev/sinic.cc
View File

@@ -47,9 +47,10 @@
#include "sim/eventq.hh"
#include "sim/host.hh"
#include "sim/stats.hh"
#include "targetarch/vtophys.hh"
#include "arch/vtophys.hh"
using namespace Net;
using namespace TheISA;
namespace Sinic {
@@ -112,8 +113,6 @@ Device::Device(Params *p)
p->dma_no_allocate);
} else if (p->payload_bus)
panic("must define a header bus if defining a payload bus");
pioDelayWrite = p->pio_delay_write && pioInterface;
}
Device::~Device()
@@ -352,9 +351,6 @@ Device::prepareRead(int cpu, int index)
void
Device::prepareWrite(int cpu, int index)
{
if (cpu >= writeQueue.size())
writeQueue.resize(cpu + 1);
prepareIO(cpu, index);
}
@@ -367,11 +363,11 @@ Device::read(MemReqPtr &req, uint8_t *data)
assert(config.command & PCI_CMD_MSE);
Fault fault = readBar(req, data);
if (fault == Machine_Check_Fault) {
if (fault->isMachineCheckFault()) {
panic("address does not map to a BAR pa=%#x va=%#x size=%d",
req->paddr, req->vaddr, req->size);
return Machine_Check_Fault;
return genMachineCheckFault();
}
return fault;
@@ -380,7 +376,7 @@ Device::read(MemReqPtr &req, uint8_t *data)
Fault
Device::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data)
{
int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff;
int cpu = (req->xc->readMiscReg(TheISA::IPR_PALtemp16) >> 8) & 0xff;
Addr index = daddr >> Regs::VirtualShift;
Addr raddr = daddr & Regs::VirtualMask;
@@ -421,7 +417,7 @@ Device::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data)
if (raddr == Regs::IntrStatus)
devIntrClear();
return No_Fault;
return NoFault;
}
/**
@@ -451,7 +447,7 @@ Device::iprRead(Addr daddr, int cpu, uint64_t &result)
DPRINTF(EthernetPIO, "IPR read %s: cpu=%s da=%#x val=%#x\n",
info.name, cpu, result);
return No_Fault;
return NoFault;
}
/**
@@ -463,11 +459,11 @@ Device::write(MemReqPtr &req, const uint8_t *data)
assert(config.command & PCI_CMD_MSE);
Fault fault = writeBar(req, data);
if (fault == Machine_Check_Fault) {
if (fault->isMachineCheckFault()) {
panic("address does not map to a BAR pa=%#x va=%#x size=%d",
req->paddr, req->vaddr, req->size);
return Machine_Check_Fault;
return genMachineCheckFault();
}
return fault;
@@ -476,7 +472,7 @@ Device::write(MemReqPtr &req, const uint8_t *data)
Fault
Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data)
{
int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff;
int cpu = (req->xc->readMiscReg(TheISA::IPR_PALtemp16) >> 8) & 0xff;
Addr index = daddr >> Regs::VirtualShift;
Addr raddr = daddr & Regs::VirtualMask;
@@ -495,32 +491,15 @@ Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data)
uint32_t reg32 = *(uint32_t *)data;
uint64_t reg64 = *(uint64_t *)data;
VirtualReg &vnic = virtualRegs[index];
DPRINTF(EthernetPIO,
"write %s: cpu=%d val=%#x da=%#x pa=%#x va=%#x size=%d\n",
info.name, cpu, info.size == 4 ? reg32 : reg64, daddr,
req->paddr, req->vaddr, req->size);
info.name, cpu, info.size == 4 ? reg32 : reg64,
daddr, req->paddr, req->vaddr, req->size);
prepareWrite(cpu, index);
if (pioDelayWrite)
writeQueue[cpu].push_back(RegWriteData(daddr, reg64));
if (!pioDelayWrite || !info.delay_write)
regWrite(daddr, cpu, data);
return No_Fault;
}
void
Device::regWrite(Addr daddr, int cpu, const uint8_t *data)
{
Addr index = daddr >> Regs::VirtualShift;
Addr raddr = daddr & Regs::VirtualMask;
uint32_t reg32 = *(uint32_t *)data;
uint64_t reg64 = *(uint64_t *)data;
VirtualReg &vnic = virtualRegs[index];
switch (raddr) {
case Regs::Config:
changeConfig(reg32);
@@ -567,6 +546,8 @@ Device::regWrite(Addr daddr, int cpu, const uint8_t *data)
}
break;
}
return NoFault;
}
void
@@ -780,6 +761,8 @@ Device::reset()
regs.Config |= Config_RxThread;
if (params()->tx_thread)
regs.Config |= Config_TxThread;
if (params()->rss)
regs.Config |= Config_RSS;
regs.IntrMask = Intr_Soft | Intr_RxHigh | Intr_RxPacket | Intr_TxLow;
regs.RxMaxCopy = params()->rx_max_copy;
regs.TxMaxCopy = params()->tx_max_copy;
@@ -1570,27 +1553,6 @@ Device::cacheAccess(MemReqPtr &req)
DPRINTF(EthernetPIO, "timing %s to paddr=%#x bar=%d daddr=%#x\n",
req->cmd.toString(), req->paddr, bar, daddr);
if (!pioDelayWrite || !req->cmd.isWrite())
return curTick + pioLatency;
if (bar == 0) {
int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff;
std::list<RegWriteData> &wq = writeQueue[cpu];
if (wq.empty())
panic("WriteQueue for cpu %d empty timing daddr=%#x", cpu, daddr);
const RegWriteData &data = wq.front();
if (data.daddr != daddr)
panic("read mismatch on cpu %d, daddr functional=%#x timing=%#x",
cpu, data.daddr, daddr);
const Regs::Info &info = regInfo(data.daddr);
if (info.delay_write)
regWrite(daddr, cpu, (uint8_t *)&data.value);
wq.pop_front();
}
return curTick + pioLatency;
}
@@ -1648,7 +1610,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(Device)
Param<Tick> dma_write_factor;
Param<bool> dma_no_allocate;
Param<Tick> pio_latency;
Param<bool> pio_delay_write;
Param<Tick> intr_delay;
Param<Tick> rx_delay;
@@ -1665,6 +1626,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(Device)
Param<string> hardware_address;
Param<bool> rx_thread;
Param<bool> tx_thread;
Param<bool> rss;
END_DECLARE_SIM_OBJECT_PARAMS(Device)
@@ -1692,7 +1654,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(Device)
INIT_PARAM(dma_write_factor, "multiplier for dma writes"),
INIT_PARAM(dma_no_allocate, "Should we allocat on read in cache"),
INIT_PARAM(pio_latency, "Programmed IO latency in bus cycles"),
INIT_PARAM(pio_delay_write, ""),
INIT_PARAM(intr_delay, "Interrupt Delay"),
INIT_PARAM(rx_delay, "Receive Delay"),
@@ -1708,7 +1669,8 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(Device)
INIT_PARAM(rx_filter, "Enable Receive Filter"),
INIT_PARAM(hardware_address, "Ethernet Hardware Address"),
INIT_PARAM(rx_thread, ""),
INIT_PARAM(tx_thread, "")
INIT_PARAM(tx_thread, ""),
INIT_PARAM(rss, "")
END_INIT_SIM_OBJECT_PARAMS(Device)
@@ -1740,7 +1702,6 @@ CREATE_SIM_OBJECT(Device)
params->dma_write_factor = dma_write_factor;
params->dma_no_allocate = dma_no_allocate;
params->pio_latency = pio_latency;
params->pio_delay_write = pio_delay_write;
params->intr_delay = intr_delay;
params->tx_delay = tx_delay;
@@ -1757,6 +1718,7 @@ CREATE_SIM_OBJECT(Device)
params->eaddr = hardware_address;
params->rx_thread = rx_thread;
params->tx_thread = tx_thread;
params->rss = rss;
return new Device(params);
}

14
dev/sinic.hh
View File

@@ -280,20 +280,8 @@ class Device : public Base
Fault iprRead(Addr daddr, int cpu, uint64_t &result);
Fault readBar0(MemReqPtr &req, Addr daddr, uint8_t *data);
Fault writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data);
void regWrite(Addr daddr, int cpu, const uint8_t *data);
Tick cacheAccess(MemReqPtr &req);
protected:
struct RegWriteData {
Addr daddr;
uint64_t value;
RegWriteData(Addr da, uint64_t val) : daddr(da), value(val) {}
};
std::vector<std::list<RegWriteData> > writeQueue;
bool pioDelayWrite;
/**
* Statistics
*/
@@ -349,7 +337,6 @@ class Device : public Base
Bus *header_bus;
Bus *payload_bus;
Tick pio_latency;
bool pio_delay_write;
PhysicalMemory *physmem;
IntrControl *intctrl;
bool rx_filter;
@@ -368,6 +355,7 @@ class Device : public Base
bool dma_no_allocate;
bool rx_thread;
bool tx_thread;
bool rss;
};
protected:

41
dev/sinicreg.hh
View File

@@ -81,6 +81,7 @@ __SINIC_REG32(HwAddr, 0x60); // 64: mac address
__SINIC_REG32(Size, 0x68); // register addres space size
// Config register bits
__SINIC_VAL32(Config_RSS, 10, 1); // enable receive side scaling
__SINIC_VAL32(Config_RxThread, 9, 1); // enable receive threads
__SINIC_VAL32(Config_TxThread, 8, 1); // enable transmit thread
__SINIC_VAL32(Config_Filter, 7, 1); // enable receive filter
@@ -157,8 +158,6 @@ struct Info
uint8_t size;
bool read;
bool write;
bool delay_read;
bool delay_write;
const char *name;
};
@@ -167,33 +166,33 @@ struct Info
inline const Regs::Info&
regInfo(Addr daddr)
{
static Regs::Info invalid = { 0, false, false, false, false, "invalid" };
static Regs::Info invalid = { 0, false, false, "invalid" };
static Regs::Info info [] = {
{ 4, true, true, false, false, "Config" },
{ 4, false, true, false, false, "Command" },
{ 4, true, true, false, false, "IntrStatus" },
{ 4, true, true, false, false, "IntrMask" },
{ 4, true, false, false, false, "RxMaxCopy" },
{ 4, true, false, false, false, "TxMaxCopy" },
{ 4, true, false, false, false, "RxMaxIntr" },
{ 4, true, true, "Config" },
{ 4, false, true, "Command" },
{ 4, true, true, "IntrStatus" },
{ 4, true, true, "IntrMask" },
{ 4, true, false, "RxMaxCopy" },
{ 4, true, false, "TxMaxCopy" },
{ 4, true, false, "RxMaxIntr" },
invalid,
{ 4, true, false, false, false, "RxFifoSize" },
{ 4, true, false, false, false, "TxFifoSize" },
{ 4, true, false, false, false, "RxFifoMark" },
{ 4, true, false, false, false, "TxFifoMark" },
{ 8, true, true, false, true, "RxData" },
{ 4, true, false, "RxFifoSize" },
{ 4, true, false, "TxFifoSize" },
{ 4, true, false, "RxFifoMark" },
{ 4, true, false, "TxFifoMark" },
{ 8, true, true, "RxData" },
invalid,
{ 8, true, false, false, false, "RxDone" },
{ 8, true, false, "RxDone" },
invalid,
{ 8, true, false, false, false, "RxWait" },
{ 8, true, false, "RxWait" },
invalid,
{ 8, true, true, false, true, "TxData" },
{ 8, true, true, "TxData" },
invalid,
{ 8, true, false, false, false, "TxDone" },
{ 8, true, false, "TxDone" },
invalid,
{ 8, true, false, false, false, "TxWait" },
{ 8, true, false, "TxWait" },
invalid,
{ 8, true, false, false, false, "HwAddr" },
{ 8, true, false, "HwAddr" },
invalid,
};

2
dev/tsunami.cc
View File

@@ -46,6 +46,8 @@
#include "sim/system.hh"
using namespace std;
//Should this be AlphaISA?
using namespace TheISA;
Tsunami::Tsunami(const string &name, System *s, IntrControl *ic,
PciConfigAll *pci)

69
dev/tsunami_cchip.cc
View File

@@ -42,11 +42,14 @@
#include "mem/bus/pio_interface.hh"
#include "mem/bus/pio_interface_impl.hh"
#include "mem/functional/memory_control.hh"
#include "cpu/exec_context.hh"
#include "cpu/intr_control.hh"
#include "sim/builder.hh"
#include "sim/system.hh"
using namespace std;
//Should this be AlphaISA?
using namespace TheISA;
TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a,
MemoryController *mmu, HierParams *hier,
@@ -92,81 +95,81 @@ TsunamiCChip::read(MemReqPtr &req, uint8_t *data)
if (daddr & TSDEV_CC_BDIMS)
{
*(uint64_t*)data = dim[(daddr >> 4) & 0x3F];
return No_Fault;
return NoFault;
}
if (daddr & TSDEV_CC_BDIRS)
{
*(uint64_t*)data = dir[(daddr >> 4) & 0x3F];
return No_Fault;
return NoFault;
}
switch(regnum) {
case TSDEV_CC_CSR:
*(uint64_t*)data = 0x0;
return No_Fault;
return NoFault;
case TSDEV_CC_MTR:
panic("TSDEV_CC_MTR not implemeted\n");
return No_Fault;
return NoFault;
case TSDEV_CC_MISC:
*(uint64_t*)data = (ipint << 8) & 0xF |
(itint << 4) & 0xF |
(xc->cpu_id & 0x3);
return No_Fault;
(xc->readCpuId() & 0x3);
return NoFault;
case TSDEV_CC_AAR0:
case TSDEV_CC_AAR1:
case TSDEV_CC_AAR2:
case TSDEV_CC_AAR3:
*(uint64_t*)data = 0;
return No_Fault;
return NoFault;
case TSDEV_CC_DIM0:
*(uint64_t*)data = dim[0];
return No_Fault;
return NoFault;
case TSDEV_CC_DIM1:
*(uint64_t*)data = dim[1];
return No_Fault;
return NoFault;
case TSDEV_CC_DIM2:
*(uint64_t*)data = dim[2];
return No_Fault;
return NoFault;
case TSDEV_CC_DIM3:
*(uint64_t*)data = dim[3];
return No_Fault;
return NoFault;
case TSDEV_CC_DIR0:
*(uint64_t*)data = dir[0];
return No_Fault;
return NoFault;
case TSDEV_CC_DIR1:
*(uint64_t*)data = dir[1];
return No_Fault;
return NoFault;
case TSDEV_CC_DIR2:
*(uint64_t*)data = dir[2];
return No_Fault;
return NoFault;
case TSDEV_CC_DIR3:
*(uint64_t*)data = dir[3];
return No_Fault;
return NoFault;
case TSDEV_CC_DRIR:
*(uint64_t*)data = drir;
return No_Fault;
return NoFault;
case TSDEV_CC_PRBEN:
panic("TSDEV_CC_PRBEN not implemented\n");
return No_Fault;
return NoFault;
case TSDEV_CC_IIC0:
case TSDEV_CC_IIC1:
case TSDEV_CC_IIC2:
case TSDEV_CC_IIC3:
panic("TSDEV_CC_IICx not implemented\n");
return No_Fault;
return NoFault;
case TSDEV_CC_MPR0:
case TSDEV_CC_MPR1:
case TSDEV_CC_MPR2:
case TSDEV_CC_MPR3:
panic("TSDEV_CC_MPRx not implemented\n");
return No_Fault;
return NoFault;
case TSDEV_CC_IPIR:
*(uint64_t*)data = ipint;
return No_Fault;
return NoFault;
case TSDEV_CC_ITIR:
*(uint64_t*)data = itint;
return No_Fault;
return NoFault;
default:
panic("default in cchip read reached, accessing 0x%x\n");
} // uint64_t
@@ -179,7 +182,7 @@ TsunamiCChip::read(MemReqPtr &req, uint8_t *data)
*(uint32_t*)data = drir;
} else
panic("invalid access size(?) for tsunami register!\n");
return No_Fault;
return NoFault;
case sizeof(uint16_t):
case sizeof(uint8_t):
default:
@@ -187,7 +190,7 @@ TsunamiCChip::read(MemReqPtr &req, uint8_t *data)
}
DPRINTFN("Tsunami CChip ERROR: read regnum=%#x size=%d\n", regnum, req->size);
return No_Fault;
return NoFault;
}
Fault
@@ -243,16 +246,16 @@ TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
}
}
return No_Fault;
return NoFault;
}
switch(regnum) {
case TSDEV_CC_CSR:
panic("TSDEV_CC_CSR write\n");
return No_Fault;
return NoFault;
case TSDEV_CC_MTR:
panic("TSDEV_CC_MTR write not implemented\n");
return No_Fault;
return NoFault;
case TSDEV_CC_MISC:
uint64_t ipreq;
ipreq = (*(uint64_t*)data >> 12) & 0xF;
@@ -285,13 +288,13 @@ TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
if(!supportedWrite)
panic("TSDEV_CC_MISC write not implemented\n");
return No_Fault;
return NoFault;
case TSDEV_CC_AAR0:
case TSDEV_CC_AAR1:
case TSDEV_CC_AAR2:
case TSDEV_CC_AAR3:
panic("TSDEV_CC_AARx write not implemeted\n");
return No_Fault;
return NoFault;
case TSDEV_CC_DIM0:
case TSDEV_CC_DIM1:
case TSDEV_CC_DIM2:
@@ -341,7 +344,7 @@ TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
}
}
return No_Fault;
return NoFault;
case TSDEV_CC_DIR0:
case TSDEV_CC_DIR1:
case TSDEV_CC_DIR2:
@@ -363,13 +366,13 @@ TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
panic("TSDEV_CC_MPRx write not implemented\n");
case TSDEV_CC_IPIR:
clearIPI(*(uint64_t*)data);
return No_Fault;
return NoFault;
case TSDEV_CC_ITIR:
clearITI(*(uint64_t*)data);
return No_Fault;
return NoFault;
case TSDEV_CC_IPIQ:
reqIPI(*(uint64_t*)data);
return No_Fault;
return NoFault;
default:
panic("default in cchip read reached, accessing 0x%x\n");
}
@@ -384,7 +387,7 @@ TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size);
return No_Fault;
return NoFault;
}
void

68
dev/tsunami_io.cc
View File

@@ -50,6 +50,8 @@
#include "mem/functional/memory_control.hh"
using namespace std;
//Should this be AlphaISA?
using namespace TheISA;
TsunamiIO::RTC::RTC(const string &name, Tsunami* t, Tick i)
: _name(name), event(t, i), addr(0)
@@ -459,38 +461,38 @@ TsunamiIO::read(MemReqPtr &req, uint8_t *data)
// PIC1 mask read
case TSDEV_PIC1_MASK:
*(uint8_t*)data = ~mask1;
return No_Fault;
return NoFault;
case TSDEV_PIC2_MASK:
*(uint8_t*)data = ~mask2;
return No_Fault;
return NoFault;
case TSDEV_PIC1_ISR:
// !!! If this is modified 64bit case needs to be too
// Pal code has to do a 64 bit physical read because there is
// no load physical byte instruction
*(uint8_t*)data = picr;
return No_Fault;
return NoFault;
case TSDEV_PIC2_ISR:
// PIC2 not implemnted... just return 0
*(uint8_t*)data = 0x00;
return No_Fault;
return NoFault;
case TSDEV_TMR0_DATA:
pitimer.counter0.read(data);
return No_Fault;
return NoFault;
case TSDEV_TMR1_DATA:
pitimer.counter1.read(data);
return No_Fault;
return NoFault;
case TSDEV_TMR2_DATA:
pitimer.counter2.read(data);
return No_Fault;
return NoFault;
case TSDEV_RTC_DATA:
rtc.readData(data);
return No_Fault;
return NoFault;
case TSDEV_CTRL_PORTB:
if (pitimer.counter2.outputHigh())
*data = PORTB_SPKR_HIGH;
else
*data = 0x00;
return No_Fault;
return NoFault;
default:
panic("I/O Read - va%#x size %d\n", req->vaddr, req->size);
}
@@ -506,7 +508,7 @@ TsunamiIO::read(MemReqPtr &req, uint8_t *data)
// Pal code has to do a 64 bit physical read because there is
// no load physical byte instruction
*(uint64_t*)data = (uint64_t)picr;
return No_Fault;
return NoFault;
default:
panic("I/O Read - invalid size - va %#x size %d\n",
req->vaddr, req->size);
@@ -518,7 +520,7 @@ TsunamiIO::read(MemReqPtr &req, uint8_t *data)
}
panic("I/O Read - va%#x size %d\n", req->vaddr, req->size);
return No_Fault;
return NoFault;
}
Fault
@@ -550,63 +552,63 @@ TsunamiIO::write(MemReqPtr &req, const uint8_t *data)
tsunami->cchip->clearDRIR(55);
DPRINTF(Tsunami, "clearing pic interrupt\n");
}
return No_Fault;
return NoFault;
case TSDEV_PIC2_MASK:
mask2 = *(uint8_t*)data;
//PIC2 Not implemented to interrupt
return No_Fault;
return NoFault;
case TSDEV_PIC1_ACK:
// clear the interrupt on the PIC
picr &= ~(1 << (*(uint8_t*)data & 0xF));
if (!(picr & mask1))
tsunami->cchip->clearDRIR(55);
return No_Fault;
return NoFault;
case TSDEV_DMA1_CMND:
return No_Fault;
return NoFault;
case TSDEV_DMA2_CMND:
return No_Fault;
return NoFault;
case TSDEV_DMA1_MMASK:
return No_Fault;
return NoFault;
case TSDEV_DMA2_MMASK:
return No_Fault;
return NoFault;
case TSDEV_PIC2_ACK:
return No_Fault;
return NoFault;
case TSDEV_DMA1_RESET:
return No_Fault;
return NoFault;
case TSDEV_DMA2_RESET:
return No_Fault;
return NoFault;
case TSDEV_DMA1_MODE:
mode1 = *(uint8_t*)data;
return No_Fault;
return NoFault;
case TSDEV_DMA2_MODE:
mode2 = *(uint8_t*)data;
return No_Fault;
return NoFault;
case TSDEV_DMA1_MASK:
case TSDEV_DMA2_MASK:
return No_Fault;
return NoFault;
case TSDEV_TMR0_DATA:
pitimer.counter0.write(data);
return No_Fault;
return NoFault;
case TSDEV_TMR1_DATA:
pitimer.counter1.write(data);
return No_Fault;
return NoFault;
case TSDEV_TMR2_DATA:
pitimer.counter2.write(data);
return No_Fault;
return NoFault;
case TSDEV_TMR_CTRL:
pitimer.writeControl(data);
return No_Fault;
return NoFault;
case TSDEV_RTC_ADDR:
rtc.writeAddr(data);
return No_Fault;
return NoFault;
case TSDEV_KBD:
return No_Fault;
return NoFault;
case TSDEV_RTC_DATA:
rtc.writeData(data);
return No_Fault;
return NoFault;
case TSDEV_CTRL_PORTB:
// System Control Port B not implemented
return No_Fault;
return NoFault;
default:
panic("I/O Write - va%#x size %d data %#x\n", req->vaddr, req->size, (int)*data);
}
@@ -619,7 +621,7 @@ TsunamiIO::write(MemReqPtr &req, const uint8_t *data)
}
return No_Fault;
return NoFault;
}
void

68
dev/tsunami_pchip.cc
View File

@@ -47,6 +47,8 @@
#include "sim/system.hh"
using namespace std;
//Should this be AlphaISA?
using namespace TheISA;
TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a,
MemoryController *mmu, HierParams *hier,
@@ -90,60 +92,60 @@ TsunamiPChip::read(MemReqPtr &req, uint8_t *data)
switch(daddr) {
case TSDEV_PC_WSBA0:
*(uint64_t*)data = wsba[0];
return No_Fault;
return NoFault;
case TSDEV_PC_WSBA1:
*(uint64_t*)data = wsba[1];
return No_Fault;
return NoFault;
case TSDEV_PC_WSBA2:
*(uint64_t*)data = wsba[2];
return No_Fault;
return NoFault;
case TSDEV_PC_WSBA3:
*(uint64_t*)data = wsba[3];
return No_Fault;
return NoFault;
case TSDEV_PC_WSM0:
*(uint64_t*)data = wsm[0];
return No_Fault;
return NoFault;
case TSDEV_PC_WSM1:
*(uint64_t*)data = wsm[1];
return No_Fault;
return NoFault;
case TSDEV_PC_WSM2:
*(uint64_t*)data = wsm[2];
return No_Fault;
return NoFault;
case TSDEV_PC_WSM3:
*(uint64_t*)data = wsm[3];
return No_Fault;
return NoFault;
case TSDEV_PC_TBA0:
*(uint64_t*)data = tba[0];
return No_Fault;
return NoFault;
case TSDEV_PC_TBA1:
*(uint64_t*)data = tba[1];
return No_Fault;
return NoFault;
case TSDEV_PC_TBA2:
*(uint64_t*)data = tba[2];
return No_Fault;
return NoFault;
case TSDEV_PC_TBA3:
*(uint64_t*)data = tba[3];
return No_Fault;
return NoFault;
case TSDEV_PC_PCTL:
*(uint64_t*)data = pctl;
return No_Fault;
return NoFault;
case TSDEV_PC_PLAT:
panic("PC_PLAT not implemented\n");
case TSDEV_PC_RES:
panic("PC_RES not implemented\n");
case TSDEV_PC_PERROR:
*(uint64_t*)data = 0x00;
return No_Fault;
return NoFault;
case TSDEV_PC_PERRMASK:
*(uint64_t*)data = 0x00;
return No_Fault;
return NoFault;
case TSDEV_PC_PERRSET:
panic("PC_PERRSET not implemented\n");
case TSDEV_PC_TLBIV:
panic("PC_TLBIV not implemented\n");
case TSDEV_PC_TLBIA:
*(uint64_t*)data = 0x00; // shouldn't be readable, but linux
return No_Fault;
return NoFault;
case TSDEV_PC_PMONCTL:
panic("PC_PMONCTL not implemented\n");
case TSDEV_PC_PMONCNT:
@@ -162,7 +164,7 @@ TsunamiPChip::read(MemReqPtr &req, uint8_t *data)
}
DPRINTFN("Tsunami PChip ERROR: read daddr=%#x size=%d\n", daddr, req->size);
return No_Fault;
return NoFault;
}
Fault
@@ -179,49 +181,49 @@ TsunamiPChip::write(MemReqPtr &req, const uint8_t *data)
switch(daddr) {
case TSDEV_PC_WSBA0:
wsba[0] = *(uint64_t*)data;
return No_Fault;
return NoFault;
case TSDEV_PC_WSBA1:
wsba[1] = *(uint64_t*)data;
return No_Fault;
return NoFault;
case TSDEV_PC_WSBA2:
wsba[2] = *(uint64_t*)data;
return No_Fault;
return NoFault;
case TSDEV_PC_WSBA3:
wsba[3] = *(uint64_t*)data;
return No_Fault;
return NoFault;
case TSDEV_PC_WSM0:
wsm[0] = *(uint64_t*)data;
return No_Fault;
return NoFault;
case TSDEV_PC_WSM1:
wsm[1] = *(uint64_t*)data;
return No_Fault;
return NoFault;
case TSDEV_PC_WSM2:
wsm[2] = *(uint64_t*)data;
return No_Fault;
return NoFault;
case TSDEV_PC_WSM3:
wsm[3] = *(uint64_t*)data;
return No_Fault;
return NoFault;
case TSDEV_PC_TBA0:
tba[0] = *(uint64_t*)data;
return No_Fault;
return NoFault;
case TSDEV_PC_TBA1:
tba[1] = *(uint64_t*)data;
return No_Fault;
return NoFault;
case TSDEV_PC_TBA2:
tba[2] = *(uint64_t*)data;
return No_Fault;
return NoFault;
case TSDEV_PC_TBA3:
tba[3] = *(uint64_t*)data;
return No_Fault;
return NoFault;
case TSDEV_PC_PCTL:
pctl = *(uint64_t*)data;
return No_Fault;
return NoFault;
case TSDEV_PC_PLAT:
panic("PC_PLAT not implemented\n");
case TSDEV_PC_RES:
panic("PC_RES not implemented\n");
case TSDEV_PC_PERROR:
return No_Fault;
return NoFault;
case TSDEV_PC_PERRMASK:
panic("PC_PERRMASK not implemented\n");
case TSDEV_PC_PERRSET:
@@ -229,7 +231,7 @@ TsunamiPChip::write(MemReqPtr &req, const uint8_t *data)
case TSDEV_PC_TLBIV:
panic("PC_TLBIV not implemented\n");
case TSDEV_PC_TLBIA:
return No_Fault; // value ignored, supposted to invalidate SG TLB
return NoFault; // value ignored, supposted to invalidate SG TLB
case TSDEV_PC_PMONCTL:
panic("PC_PMONCTL not implemented\n");
case TSDEV_PC_PMONCNT:
@@ -249,7 +251,7 @@ TsunamiPChip::write(MemReqPtr &req, const uint8_t *data)
DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size);
return No_Fault;
return NoFault;
}
#define DMA_ADDR_MASK ULL(0x3ffffffff)

1
dev/uart.hh
View File

@@ -37,6 +37,7 @@
#include "dev/io_device.hh"
class SimConsole;
class MemoryController;
class Platform;
const int RX_INT = 0x1;

5
dev/uart8250.cc
View File

@@ -46,6 +46,7 @@
#include "sim/builder.hh"
using namespace std;
using namespace TheISA;
Uart8250::IntrEvent::IntrEvent(Uart8250 *u, int bit)
: Event(&mainEventQueue), uart(u)
@@ -183,7 +184,7 @@ Uart8250::read(MemReqPtr &req, uint8_t *data)
break;
}
return No_Fault;
return NoFault;
}
@@ -255,7 +256,7 @@ Uart8250::write(MemReqPtr &req, const uint8_t *data)
panic("Tried to access a UART port that doesn't exist\n");
break;
}
return No_Fault;
return NoFault;
}
void

1
dev/uart8250.hh
View File

@@ -53,6 +53,7 @@
#define IIR_LINE 0x06 /* Rx Line Status (highest priority)*/
class SimConsole;
class MemoryController;
class Platform;
class Uart8250 : public Uart