From 86131d4323f4ec70e4f60074d4e6b13c6d1f3bf1 Mon Sep 17 00:00:00 2001 From: Matt Sinclair Date: Wed, 8 Nov 2023 12:13:15 -0600 Subject: [PATCH] mem-ruby, gpu-compute: update GPU L1I$ MRU info (#530) Previously the GPU L1 I$ (SQC) was not updating the MRU information on hits in the SQC. This commit resolves that by adding support to the appropriate Ruby transition. --- src/mem/ruby/protocol/GPU_VIPER-SQC.sm | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/mem/ruby/protocol/GPU_VIPER-SQC.sm b/src/mem/ruby/protocol/GPU_VIPER-SQC.sm index 28bddf5ba4..6290908e1b 100644 --- a/src/mem/ruby/protocol/GPU_VIPER-SQC.sm +++ b/src/mem/ruby/protocol/GPU_VIPER-SQC.sm @@ -1,5 +1,6 @@ /* * Copyright (c) 2012-2015 Advanced Micro Devices, Inc. + * Copyright (c) 2023 Matthew D. Sinclair * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -297,6 +298,10 @@ machine(MachineType:SQC, "GPU SQC (L1 I Cache)") } } + action(mru_updateMRU, "mru", desc="Touch block for replacement policy") { + L1cache.setMRU(address); + } + // added for profiling action(uu_profileDataMiss, "\udm", desc="Profile SQC demand miss"){ L1cache.profileDemandMiss(); @@ -332,6 +337,7 @@ machine(MachineType:SQC, "GPU SQC (L1 I Cache)") // simple hit transitions transition(V, Fetch) {TagArrayRead, DataArrayRead} { l_loadDoneHit; + mru_updateMRU; uu_profileDataHit; // line was in SQC, so we hit p_popMandatoryQueue; }