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cpu,arm: Add a method to RegClass-es to print register values.

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This further abstracts the properties of registers so they can be
removed from the CPUs.

Change-Id: I2aa1bffe8b095a0301579e60270965c611d6db4e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49694
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-08-11 03:03:10 -07:00
parent ff4a8b15a0
commit 85b769a68e
3 changed files with 87 additions and 27 deletions
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2
src/arch/arm/isa.cc
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@@ -80,7 +80,7 @@ class MiscRegClassOps : public RegClassOps
}
} miscRegClassOps;
VecElemRegClassOps vecRegElemClassOps(NumVecElemPerVecReg);
VecElemRegClassOps<ArmISA::VecElem> vecRegElemClassOps(NumVecElemPerVecReg);
ISA::ISA(const Params &p) : BaseISA(p), system(NULL),
_decoderFlavor(p.decoderFlavor), pmu(p.pmu), impdefAsNop(p.impdef_nop),