cpu: Revert CPU stats changes
This reverts this relationchain: https://gem5-review.googlesource.com/c/public/gem5/+/67396/6 This was pre-maturely submitted before all testing and checking was done. To be safe this has been reverted. When all testing and checks are completed, this revert will be undone. Change-Id: I2a88cadfee03c1fc81932e6548938db108786dd2 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68717 Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Bobby Bruce <bbruce@ucdavis.edu> Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Bobby R. Bruce
committed by
Bobby Bruce
Bobby Bruce
parent
18ba4e1278
commit
85342dbb0e
@@ -86,12 +86,60 @@ class SimpleExecContext : public ExecContext
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: statistics::Group(cpu,
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csprintf("exec_context.thread_%i",
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thread->threadId()).c_str()),
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ADD_STAT(numInsts, statistics::units::Count::get(),
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"Number of instructions committed"),
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ADD_STAT(numOps, statistics::units::Count::get(),
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"Number of ops (including micro ops) committed"),
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ADD_STAT(numIntAluAccesses, statistics::units::Count::get(),
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"Number of integer alu accesses"),
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ADD_STAT(numFpAluAccesses, statistics::units::Count::get(),
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"Number of float alu accesses"),
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ADD_STAT(numVecAluAccesses, statistics::units::Count::get(),
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"Number of vector alu accesses"),
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ADD_STAT(numMatAluAccesses, statistics::units::Count::get(),
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"Number of matrix alu accesses"),
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ADD_STAT(numCallsReturns, statistics::units::Count::get(),
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"Number of times a function call or return occured"),
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ADD_STAT(numCondCtrlInsts, statistics::units::Count::get(),
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"Number of instructions that are conditional controls"),
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ADD_STAT(numIntInsts, statistics::units::Count::get(),
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"Number of integer instructions"),
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ADD_STAT(numFpInsts, statistics::units::Count::get(),
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"Number of float instructions"),
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ADD_STAT(numVecInsts, statistics::units::Count::get(),
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"Number of vector instructions"),
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ADD_STAT(numMatInsts, statistics::units::Count::get(),
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"Number of matrix instructions"),
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ADD_STAT(numIntRegReads, statistics::units::Count::get(),
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"Number of times the integer registers were read"),
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ADD_STAT(numIntRegWrites, statistics::units::Count::get(),
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"Number of times the integer registers were written"),
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ADD_STAT(numFpRegReads, statistics::units::Count::get(),
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"Number of times the floating registers were read"),
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ADD_STAT(numFpRegWrites, statistics::units::Count::get(),
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"Number of times the floating registers were written"),
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ADD_STAT(numVecRegReads, statistics::units::Count::get(),
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"Number of times the vector registers were read"),
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ADD_STAT(numVecRegWrites, statistics::units::Count::get(),
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"Number of times the vector registers were written"),
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ADD_STAT(numVecPredRegReads, statistics::units::Count::get(),
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"Number of times the predicate registers were read"),
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ADD_STAT(numVecPredRegWrites, statistics::units::Count::get(),
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"Number of times the predicate registers were written"),
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ADD_STAT(numCCRegReads, statistics::units::Count::get(),
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"Number of times the CC registers were read"),
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ADD_STAT(numCCRegWrites, statistics::units::Count::get(),
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"Number of times the CC registers were written"),
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ADD_STAT(numMiscRegReads, statistics::units::Count::get(),
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"Number of times the Misc registers were read"),
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ADD_STAT(numMiscRegWrites, statistics::units::Count::get(),
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"Number of times the Misc registers were written"),
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ADD_STAT(numMemRefs, statistics::units::Count::get(),
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"Number of memory refs"),
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ADD_STAT(numLoadInsts, statistics::units::Count::get(),
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"Number of load instructions"),
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ADD_STAT(numStoreInsts, statistics::units::Count::get(),
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"Number of store instructions"),
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ADD_STAT(numIdleCycles, statistics::units::Cycle::get(),
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"Number of idle cycles"),
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ADD_STAT(numBusyCycles, statistics::units::Cycle::get(),
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@@ -100,35 +148,64 @@ class SimpleExecContext : public ExecContext
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"Percentage of non-idle cycles"),
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ADD_STAT(idleFraction, statistics::units::Ratio::get(),
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"Percentage of idle cycles"),
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ADD_STAT(icacheStallCycles, statistics::units::Cycle::get(),
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"ICache total stall cycles"),
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ADD_STAT(dcacheStallCycles, statistics::units::Cycle::get(),
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"DCache total stall cycles"),
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ADD_STAT(numBranches, statistics::units::Count::get(),
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"Number of branches fetched"),
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ADD_STAT(numPredictedBranches, statistics::units::Count::get(),
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"Number of branches predicted as taken"),
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ADD_STAT(numBranchMispred, statistics::units::Count::get(),
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"Number of branch mispredictions"),
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ADD_STAT(statExecutedInstType, statistics::units::Count::get(),
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"Class of executed instruction."),
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numRegReads{
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&(cpu->executeStats[thread->threadId()]->numIntRegReads),
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&(cpu->executeStats[thread->threadId()]->numFpRegReads),
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&(cpu->executeStats[thread->threadId()]->numVecRegReads),
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&(cpu->executeStats[thread->threadId()]->numVecRegReads),
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&(cpu->executeStats[thread->threadId()]->numVecPredRegReads),
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&(cpu->executeStats[thread->threadId()]->numCCRegReads),
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&numMatRegReads
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&numIntRegReads,
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&numFpRegReads,
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&numVecRegReads,
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&numVecRegReads,
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&numVecPredRegReads,
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&numMatRegReads,
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&numCCRegReads
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},
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numRegWrites{
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&(cpu->executeStats[thread->threadId()]->numIntRegWrites),
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&(cpu->executeStats[thread->threadId()]->numFpRegWrites),
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&(cpu->executeStats[thread->threadId()]->numVecRegWrites),
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&(cpu->executeStats[thread->threadId()]->numVecRegWrites),
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&(cpu->executeStats[thread->threadId()]
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->numVecPredRegWrites),
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&(cpu->executeStats[thread->threadId()]->numCCRegWrites),
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&numMatRegWrites
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&numIntRegWrites,
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&numFpRegWrites,
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&numVecRegWrites,
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&numVecRegWrites,
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&numVecPredRegWrites,
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&numMatRegWrites,
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&numCCRegWrites
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}
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{
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numCCRegReads
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.flags(statistics::nozero);
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numCCRegWrites
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.flags(statistics::nozero);
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icacheStallCycles
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.prereq(icacheStallCycles);
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dcacheStallCycles
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.prereq(dcacheStallCycles);
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statExecutedInstType
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.init(enums::Num_OpClass)
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.flags(statistics::total | statistics::pdf | statistics::dist);
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for (unsigned i = 0; i < Num_OpClasses; ++i) {
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statExecutedInstType.subname(i, enums::OpClassStrings[i]);
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}
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idleFraction = statistics::constant(1.0) - notIdleFraction;
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numIdleCycles = idleFraction * cpu->baseStats.numCycles;
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numBusyCycles = notIdleFraction * cpu->baseStats.numCycles;
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numBranches
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.prereq(numBranches);
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numPredictedBranches
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.prereq(numPredictedBranches);
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@@ -136,19 +213,73 @@ class SimpleExecContext : public ExecContext
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.prereq(numBranchMispred);
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}
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// Number of simulated instructions
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statistics::Scalar numInsts;
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statistics::Scalar numOps;
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// Number of integer alu accesses
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statistics::Scalar numIntAluAccesses;
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// Number of float alu accesses
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statistics::Scalar numFpAluAccesses;
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// Number of vector alu accesses
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statistics::Scalar numVecAluAccesses;
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// Number of matrix alu accesses
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statistics::Scalar numMatAluAccesses;
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// Number of function calls/returns
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statistics::Scalar numCallsReturns;
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// Conditional control instructions;
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statistics::Scalar numCondCtrlInsts;
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// Number of int instructions
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statistics::Scalar numIntInsts;
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// Number of float instructions
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statistics::Scalar numFpInsts;
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// Number of vector instructions
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statistics::Scalar numVecInsts;
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// Number of matrix instructions
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statistics::Scalar numMatInsts;
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// Number of integer register file accesses
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statistics::Scalar numIntRegReads;
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statistics::Scalar numIntRegWrites;
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// Number of float register file accesses
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statistics::Scalar numFpRegReads;
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statistics::Scalar numFpRegWrites;
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// Number of vector register file accesses
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mutable statistics::Scalar numVecRegReads;
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statistics::Scalar numVecRegWrites;
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// Number of predicate register file accesses
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mutable statistics::Scalar numVecPredRegReads;
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statistics::Scalar numVecPredRegWrites;
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// Number of matrix register file accesses
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mutable statistics::Scalar numMatRegReads;
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statistics::Scalar numMatRegWrites;
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// Number of condition code register file accesses
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statistics::Scalar numCCRegReads;
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statistics::Scalar numCCRegWrites;
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// Number of misc register file accesses
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statistics::Scalar numMiscRegReads;
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statistics::Scalar numMiscRegWrites;
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// Number of simulated memory references
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statistics::Scalar numMemRefs;
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statistics::Scalar numLoadInsts;
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statistics::Scalar numStoreInsts;
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// Number of idle cycles
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statistics::Formula numIdleCycles;
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@@ -159,13 +290,24 @@ class SimpleExecContext : public ExecContext
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statistics::Average notIdleFraction;
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statistics::Formula idleFraction;
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// Number of cycles stalled for I-cache responses
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statistics::Scalar icacheStallCycles;
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// Number of cycles stalled for D-cache responses
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statistics::Scalar dcacheStallCycles;
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/// @{
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/// Total number of branches fetched
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statistics::Scalar numBranches;
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/// Number of branches predicted as taken
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statistics::Scalar numPredictedBranches;
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/// Number of misprediced branches
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statistics::Scalar numBranchMispred;
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/// @}
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// Instruction mix histogram by OpClass
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statistics::Vector statExecutedInstType;
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std::array<statistics::Scalar *, CCRegClass + 1> numRegReads;
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std::array<statistics::Scalar *, CCRegClass + 1> numRegWrites;
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@@ -226,7 +368,7 @@ class SimpleExecContext : public ExecContext
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RegVal
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readMiscRegOperand(const StaticInst *si, int idx) override
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{
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cpu->executeStats[thread->threadId()]->numMiscRegReads++;
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execContextStats.numMiscRegReads++;
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const RegId& reg = si->srcRegIdx(idx);
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assert(reg.is(MiscRegClass));
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return thread->readMiscReg(reg.index());
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@@ -235,7 +377,7 @@ class SimpleExecContext : public ExecContext
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void
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setMiscRegOperand(const StaticInst *si, int idx, RegVal val) override
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{
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cpu->executeStats[thread->threadId()]->numMiscRegWrites++;
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execContextStats.numMiscRegWrites++;
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const RegId& reg = si->destRegIdx(idx);
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assert(reg.is(MiscRegClass));
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thread->setMiscReg(reg.index(), val);
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@@ -248,7 +390,7 @@ class SimpleExecContext : public ExecContext
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RegVal
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readMiscReg(int misc_reg) override
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{
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cpu->executeStats[thread->threadId()]->numMiscRegReads++;
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execContextStats.numMiscRegReads++;
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return thread->readMiscReg(misc_reg);
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}
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@@ -259,7 +401,7 @@ class SimpleExecContext : public ExecContext
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void
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setMiscReg(int misc_reg, RegVal val) override
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{
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cpu->executeStats[thread->threadId()]->numMiscRegWrites++;
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execContextStats.numMiscRegWrites++;
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thread->setMiscReg(misc_reg, val);
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}
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