cpu: Revert CPU stats changes
This reverts this relationchain: https://gem5-review.googlesource.com/c/public/gem5/+/67396/6 This was pre-maturely submitted before all testing and checking was done. To be safe this has been reverted. When all testing and checks are completed, this revert will be undone. Change-Id: I2a88cadfee03c1fc81932e6548938db108786dd2 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68717 Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Bobby Bruce <bbruce@ucdavis.edu> Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Bobby R. Bruce
committed by
Bobby Bruce
Bobby Bruce
parent
18ba4e1278
commit
85342dbb0e
250
src/cpu/base.cc
250
src/cpu/base.cc
@@ -191,30 +191,6 @@ BaseCPU::BaseCPU(const Params &p, bool is_checker)
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modelResetPort.onChange([this](const bool &new_val) {
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setReset(new_val);
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});
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// create a stat group object for each thread on this core
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fetchStats.reserve(numThreads);
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executeStats.reserve(numThreads);
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commitStats.reserve(numThreads);
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for (int i = 0; i < numThreads; i++) {
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// create fetchStat object for thread i and set rate formulas
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FetchCPUStats* fetchStatptr = new FetchCPUStats(this, i);
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fetchStatptr->fetchRate = fetchStatptr->numInsts / baseStats.numCycles;
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fetchStatptr->branchRate = fetchStatptr->numBranches /
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baseStats.numCycles;
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fetchStats.emplace_back(fetchStatptr);
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// create executeStat object for thread i and set rate formulas
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ExecuteCPUStats* executeStatptr = new ExecuteCPUStats(this, i);
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executeStatptr->instRate = executeStatptr->numInsts /
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baseStats.numCycles;
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executeStats.emplace_back(executeStatptr);
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// create commitStat object for thread i and set ipc, cpi formulas
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CommitCPUStats* commitStatptr = new CommitCPUStats(this, i);
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commitStatptr->ipc = commitStatptr->numInsts / baseStats.numCycles;
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commitStatptr->cpi = baseStats.numCycles / commitStatptr->numInsts;
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commitStats.emplace_back(commitStatptr);
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}
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}
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void
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@@ -407,28 +383,13 @@ BaseCPU::probeInstCommit(const StaticInstPtr &inst, Addr pc)
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BaseCPU::
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BaseCPUStats::BaseCPUStats(statistics::Group *parent)
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: statistics::Group(parent),
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ADD_STAT(numInsts, statistics::units::Count::get(),
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"Number of instructions committed (core level)"),
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ADD_STAT(numOps, statistics::units::Count::get(),
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"Number of ops (including micro ops) committed (core level)"),
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ADD_STAT(numCycles, statistics::units::Cycle::get(),
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"Number of cpu cycles simulated"),
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ADD_STAT(cpi, statistics::units::Rate<
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statistics::units::Cycle, statistics::units::Count>::get(),
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"CPI: cycles per instruction (core level)"),
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ADD_STAT(ipc, statistics::units::Rate<
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statistics::units::Count, statistics::units::Cycle>::get(),
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"IPC: instructions per cycle (core level)"),
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ADD_STAT(numWorkItemsStarted, statistics::units::Count::get(),
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"Number of work items this cpu started"),
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ADD_STAT(numWorkItemsCompleted, statistics::units::Count::get(),
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"Number of work items this cpu completed")
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{
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cpi.precision(6);
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cpi = numCycles / numInsts;
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ipc.precision(6);
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ipc = numInsts / numCycles;
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}
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void
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@@ -866,215 +827,4 @@ BaseCPU::GlobalStats::GlobalStats(statistics::Group *parent)
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hostOpRate = simOps / hostSeconds;
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}
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BaseCPU::
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FetchCPUStats::FetchCPUStats(statistics::Group *parent, int thread_id)
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: statistics::Group(parent, csprintf("fetchStats%i", thread_id).c_str()),
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ADD_STAT(numInsts, statistics::units::Count::get(),
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"Number of instructions fetched (thread level)"),
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ADD_STAT(numOps, statistics::units::Count::get(),
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"Number of ops (including micro ops) fetched (thread level)"),
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ADD_STAT(fetchRate, statistics::units::Rate<
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statistics::units::Count, statistics::units::Cycle>::get(),
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"Number of inst fetches per cycle"),
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ADD_STAT(numBranches, statistics::units::Count::get(),
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"Number of branches fetched"),
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ADD_STAT(branchRate, statistics::units::Ratio::get(),
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"Number of branch fetches per cycle"),
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ADD_STAT(icacheStallCycles, statistics::units::Cycle::get(),
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"ICache total stall cycles"),
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ADD_STAT(numFetchSuspends, statistics::units::Count::get(),
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"Number of times Execute suspended instruction fetching")
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{
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fetchRate
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.flags(statistics::total);
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numBranches
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.prereq(numBranches);
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branchRate
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.flags(statistics::total);
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icacheStallCycles
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.prereq(icacheStallCycles);
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}
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// means it is incremented in a vector indexing and not directly
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BaseCPU::
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ExecuteCPUStats::ExecuteCPUStats(statistics::Group *parent, int thread_id)
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: statistics::Group(parent, csprintf("executeStats%i", thread_id).c_str()),
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ADD_STAT(numInsts, statistics::units::Count::get(),
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"Number of executed instructions"),
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ADD_STAT(numNop, statistics::units::Count::get(),
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"Number of nop insts executed"),
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ADD_STAT(numBranches, statistics::units::Count::get(),
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"Number of branches executed"),
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ADD_STAT(numLoadInsts, statistics::units::Count::get(),
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"Number of load instructions executed"),
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ADD_STAT(numStoreInsts, statistics::units::Count::get(),
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"Number of stores executed"),
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ADD_STAT(instRate, statistics::units::Rate<
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statistics::units::Count, statistics::units::Cycle>::get(),
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"Inst execution rate"),
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ADD_STAT(dcacheStallCycles, statistics::units::Cycle::get(),
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"DCache total stall cycles"),
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ADD_STAT(numCCRegReads, statistics::units::Count::get(),
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"Number of times the CC registers were read"),
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ADD_STAT(numCCRegWrites, statistics::units::Count::get(),
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"Number of times the CC registers were written"),
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ADD_STAT(numFpAluAccesses, statistics::units::Count::get(),
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"Number of float alu accesses"),
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ADD_STAT(numFpRegReads, statistics::units::Count::get(),
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"Number of times the floating registers were read"),
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ADD_STAT(numFpRegWrites, statistics::units::Count::get(),
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"Number of times the floating registers were written"),
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ADD_STAT(numIntAluAccesses, statistics::units::Count::get(),
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"Number of integer alu accesses"),
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ADD_STAT(numIntRegReads, statistics::units::Count::get(),
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"Number of times the integer registers were read"),
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ADD_STAT(numIntRegWrites, statistics::units::Count::get(),
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"Number of times the integer registers were written"),
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ADD_STAT(numMemRefs, statistics::units::Count::get(),
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"Number of memory refs"),
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ADD_STAT(numMiscRegReads, statistics::units::Count::get(),
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"Number of times the Misc registers were read"),
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ADD_STAT(numMiscRegWrites, statistics::units::Count::get(),
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"Number of times the Misc registers were written"),
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ADD_STAT(numVecAluAccesses, statistics::units::Count::get(),
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"Number of vector alu accesses"),
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ADD_STAT(numVecPredRegReads, statistics::units::Count::get(),
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"Number of times the predicate registers were read"),
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ADD_STAT(numVecPredRegWrites, statistics::units::Count::get(),
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"Number of times the predicate registers were written"),
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ADD_STAT(numVecRegReads, statistics::units::Count::get(),
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"Number of times the vector registers were read"),
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ADD_STAT(numVecRegWrites, statistics::units::Count::get(),
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"Number of times the vector registers were written"),
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ADD_STAT(numDiscardedOps, statistics::units::Count::get(),
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"Number of ops (including micro ops) which were discarded before "
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"commit")
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{
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numStoreInsts = numMemRefs - numLoadInsts;
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dcacheStallCycles
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.prereq(dcacheStallCycles);
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numCCRegReads
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.prereq(numCCRegReads)
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.flags(statistics::nozero);
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numCCRegWrites
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.prereq(numCCRegWrites)
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.flags(statistics::nozero);
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numFpAluAccesses
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.prereq(numFpAluAccesses);
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numFpRegReads
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.prereq(numFpRegReads);
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numIntAluAccesses
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.prereq(numIntAluAccesses);
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numIntRegReads
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.prereq(numIntRegReads);
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numIntRegWrites
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.prereq(numIntRegWrites);
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numMiscRegReads
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.prereq(numMiscRegReads);
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numMiscRegWrites
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.prereq(numMiscRegWrites);
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numVecPredRegReads
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.prereq(numVecPredRegReads);
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numVecPredRegWrites
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.prereq(numVecPredRegWrites);
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numVecRegReads
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.prereq(numVecRegReads);
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numVecRegWrites
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.prereq(numVecRegWrites);
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}
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BaseCPU::
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CommitCPUStats::CommitCPUStats(statistics::Group *parent, int thread_id)
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: statistics::Group(parent, csprintf("commitStats%i", thread_id).c_str()),
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ADD_STAT(numInsts, statistics::units::Count::get(),
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"Number of instructions committed (thread level)"),
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ADD_STAT(numOps, statistics::units::Count::get(),
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"Number of ops (including micro ops) committed (thread level)"),
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ADD_STAT(numInstsNotNOP, statistics::units::Count::get(),
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"Number of instructions committed excluding NOPs or prefetches"),
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ADD_STAT(numOpsNotNOP, statistics::units::Count::get(),
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"Number of Ops (including micro ops) Simulated"),
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ADD_STAT(cpi, statistics::units::Rate<
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statistics::units::Cycle, statistics::units::Count>::get(),
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"CPI: cycles per instruction (thread level)"),
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ADD_STAT(ipc, statistics::units::Rate<
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statistics::units::Count, statistics::units::Cycle>::get(),
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"IPC: instructions per cycle (thread level)"),
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ADD_STAT(numMemRefs, statistics::units::Count::get(),
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"Number of memory references committed"),
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ADD_STAT(numFpInsts, statistics::units::Count::get(),
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"Number of float instructions"),
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ADD_STAT(numIntInsts, statistics::units::Count::get(),
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"Number of integer instructions"),
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ADD_STAT(numLoadInsts, statistics::units::Count::get(),
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"Number of load instructions"),
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ADD_STAT(numStoreInsts, statistics::units::Count::get(),
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"Number of store instructions"),
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ADD_STAT(numVecInsts, statistics::units::Count::get(),
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"Number of vector instructions"),
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ADD_STAT(committedInstType, statistics::units::Count::get(),
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"Class of committed instruction."),
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ADD_STAT(committedControl, statistics::units::Count::get(),
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"Class of control type instructions committed")
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{
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numInsts
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.prereq(numInsts);
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cpi.precision(6);
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ipc.precision(6);
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committedInstType
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.init(enums::Num_OpClass)
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.flags(statistics::total | statistics::pdf | statistics::dist);
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for (unsigned i = 0; i < Num_OpClasses; ++i) {
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committedInstType.subname(i, enums::OpClassStrings[i]);
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}
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committedControl
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.init(StaticInstFlags::Flags::Num_Flags)
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.flags(statistics::nozero);
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for (unsigned i = 0; i < StaticInstFlags::Flags::Num_Flags; i++) {
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committedControl.subname(i, StaticInstFlags::FlagsStrings[i]);
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}
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}
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void
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BaseCPU::
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CommitCPUStats::updateComCtrlStats(const StaticInstPtr staticInst)
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{
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/* Add a count for every control instruction type */
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if (staticInst->isControl()) {
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if (staticInst->isReturn()) {
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committedControl[gem5::StaticInstFlags::Flags::IsReturn]++;
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}
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if (staticInst->isCall()) {
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committedControl[gem5::StaticInstFlags::Flags::IsCall]++;
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}
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if (staticInst->isDirectCtrl()) {
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committedControl[gem5::StaticInstFlags::Flags::IsDirectControl]++;
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}
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if (staticInst->isIndirectCtrl()) {
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committedControl
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[gem5::StaticInstFlags::Flags::IsIndirectControl]++;
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}
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if (staticInst->isCondCtrl()) {
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committedControl[gem5::StaticInstFlags::Flags::IsCondControl]++;
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}
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if (staticInst->isUncondCtrl()) {
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committedControl[gem5::StaticInstFlags::Flags::IsUncondControl]++;
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}
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committedControl[gem5::StaticInstFlags::Flags::IsControl]++;
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}
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}
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} // namespace gem5
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