From 841b8212613344cd599c56749798cfc6108920d1 Mon Sep 17 00:00:00 2001 From: Robert Hauser <85344819+robhau@users.noreply.github.com> Date: Mon, 8 Apr 2024 17:41:11 +0200 Subject: [PATCH] arch-riscv: fix c.fswsp source register (#998) RISC-V C.FSWSP format (RISC-V Unprivileged ISA V20191213, page 102): |15-13|12-7|6-2|1-0| |-------|----|----|----| |funct3|imm|rs2|op| Source register is bit 2-6, not bit 20-24 https://github.com/gem5/gem5/blob/ee6f1377d7c54422137dfa47cd4d73407814867d/src/arch/riscv/isa/bitfields.isa#L111 https://github.com/gem5/gem5/blob/ee6f1377d7c54422137dfa47cd4d73407814867d/src/arch/riscv/isa/operands.isa#L86 https://github.com/gem5/gem5/blob/ee6f1377d7c54422137dfa47cd4d73407814867d/src/arch/riscv/isa/bitfields.isa#L87 https://github.com/gem5/gem5/blob/ee6f1377d7c54422137dfa47cd4d73407814867d/src/arch/riscv/isa/operands.isa#L80 --- src/arch/riscv/isa/decoder.isa | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa index d632f722fc..30a46a5fa7 100644 --- a/src/arch/riscv/isa/decoder.isa +++ b/src/arch/riscv/isa/decoder.isa @@ -5,6 +5,7 @@ // Copyright (c) 2020 Barkhausen Institut // Copyright (c) 2021 StreamComputing Corp // Copyright (c) 2022 Google LLC +// Copyright (c) 2024 University of Rostock // All rights reserved. // // Redistribution and use in source and binary forms, with or without @@ -508,7 +509,7 @@ decode QUADRANT default Unknown::unknown() { return std::make_shared("FPU is off", machInst); - Mem_uw = unboxF32(boxF32(Fs2_bits)); + Mem_uw = unboxF32(boxF32(Fc2_bits)); }}, {{ EA = (uint32_t)(sp_uw + offset); }});