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Merge zizzer:/bk/newmem

Browse Source 
into  zeep.pool:/z/saidi/work/m5.newmem

--HG--
extra : convert_revision : fd6464c9883783c7c2cbefba317f4a0f20dd24cb
This commit is contained in:
Ali Saidi
2007-03-03 19:03:22 -05:00
parent 61178c8de2 1694c65ba1
commit 82874eefca
34 changed files with 1207 additions and 1093 deletions
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11
src/cpu/base.cc
View File

@@ -371,12 +371,6 @@ BaseCPU::ProfileEvent::process()
schedule(curTick + interval);
}
void
BaseCPU::post_interrupt(int int_type)
{
interrupts.post(int_type);
}
void
BaseCPU::post_interrupt(int int_num, int index)
{
@@ -395,6 +389,11 @@ BaseCPU::clear_interrupts()
interrupts.clear_all();
}
uint64_t
BaseCPU::get_interrupts(int int_num)
{
return interrupts.get_vec(int_num);
}
void
BaseCPU::serialize(std::ostream &os)

2
src/cpu/base.hh
View File

@@ -102,10 +102,10 @@ class BaseCPU : public MemObject
TheISA::Interrupts interrupts;
public:
virtual void post_interrupt(int int_type);
virtual void post_interrupt(int int_num, int index);
virtual void clear_interrupt(int int_num, int index);
virtual void clear_interrupts();
virtual uint64_t get_interrupts(int int_num);
bool check_interrupts(ThreadContext * tc) const
{ return interrupts.check_interrupts(tc); }

22
src/cpu/intr_control.cc
View File

@@ -40,18 +40,14 @@
using namespace std;
IntrControl::IntrControl(const string &name, BaseCPU *c)
: SimObject(name), cpu(c)
IntrControl::IntrControl(const string &name, System *s)
: SimObject(name), sys(s)
{}
/* @todo
*Fix the cpu sim object parameter to be a system pointer
*instead, to avoid some extra dereferencing
*/
void
IntrControl::post(int int_num, int index)
{
std::vector<ThreadContext *> &tcvec = cpu->system->threadContexts;
std::vector<ThreadContext *> &tcvec = sys->threadContexts;
BaseCPU *temp = tcvec[0]->getCpuPtr();
temp->post_interrupt(int_num, index);
}
@@ -59,7 +55,7 @@ IntrControl::post(int int_num, int index)
void
IntrControl::post(int cpu_id, int int_num, int index)
{
std::vector<ThreadContext *> &tcvec = cpu->system->threadContexts;
std::vector<ThreadContext *> &tcvec = sys->threadContexts;
BaseCPU *temp = tcvec[cpu_id]->getCpuPtr();
temp->post_interrupt(int_num, index);
}
@@ -67,7 +63,7 @@ IntrControl::post(int cpu_id, int int_num, int index)
void
IntrControl::clear(int int_num, int index)
{
std::vector<ThreadContext *> &tcvec = cpu->system->threadContexts;
std::vector<ThreadContext *> &tcvec = sys->threadContexts;
BaseCPU *temp = tcvec[0]->getCpuPtr();
temp->clear_interrupt(int_num, index);
}
@@ -75,26 +71,26 @@ IntrControl::clear(int int_num, int index)
void
IntrControl::clear(int cpu_id, int int_num, int index)
{
std::vector<ThreadContext *> &tcvec = cpu->system->threadContexts;
std::vector<ThreadContext *> &tcvec = sys->threadContexts;
BaseCPU *temp = tcvec[cpu_id]->getCpuPtr();
temp->clear_interrupt(int_num, index);
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(IntrControl)
SimObjectParam<BaseCPU *> cpu;
SimObjectParam<System *> sys;
END_DECLARE_SIM_OBJECT_PARAMS(IntrControl)
BEGIN_INIT_SIM_OBJECT_PARAMS(IntrControl)
INIT_PARAM(cpu, "the cpu")
INIT_PARAM(sys, "the system we are part of")
END_INIT_SIM_OBJECT_PARAMS(IntrControl)
CREATE_SIM_OBJECT(IntrControl)
{
return new IntrControl(getInstanceName(), cpu);
return new IntrControl(getInstanceName(), sys);
}
REGISTER_SIM_OBJECT("IntrControl", IntrControl)

4
src/cpu/intr_control.hh
View File

@@ -42,8 +42,8 @@
class IntrControl : public SimObject
{
public:
BaseCPU *cpu;
IntrControl(const std::string &name, BaseCPU *c);
System *sys;
IntrControl(const std::string &name, System *s);
void clear(int int_num, int index = 0);
void post(int int_num, int index = 0);