add ISA_HAS_DELAY_SLOT directive instead of "#if THE_ISA == ALPHA_ISA" throughout CPU models

src/arch/alpha/isa_traits.hh:
src/arch/mips/isa_traits.hh:
src/arch/sparc/isa_traits.hh:
    define 'ISA_HAS_DELAY_SLOT'
src/cpu/base_dyn_inst.hh:
src/cpu/o3/bpred_unit_impl.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/simple/base.cc:
    use ISA_HAS_DELAY_SLOT instead of THE_ISA == ALPHA_ISA

--HG--
extra : convert_revision : 24c7460d9391e8d443c9fe08e17c331ae8e9c36a

src/arch/alpha/isa_traits.hh

@@ -42,7 +42,6 @@ class StaticInstPtr;
 
 namespace AlphaISA
 {
-
     using namespace LittleEndianGuest;
 
     // These enumerate all the registers for dependence tracking.
@@ -60,12 +59,14 @@ namespace AlphaISA
 
     StaticInstPtr decodeInst(ExtMachInst);
 
+    // Alpha Does NOT have a delay slot
+    #define ISA_HAS_DELAY_SLOT 0
+
     const Addr PageShift = 13;
     const Addr PageBytes = ULL(1) << PageShift;
     const Addr PageMask = ~(PageBytes - 1);
     const Addr PageOffset = PageBytes - 1;
 
-
 #if FULL_SYSTEM
 
     ////////////////////////////////////////////////////////////////////////

src/arch/mips/isa_traits.hh

@@ -47,6 +47,9 @@ namespace MipsISA
 
     StaticInstPtr decodeInst(ExtMachInst);
 
+    // MIPS DOES a delay slot
+    #define ISA_HAS_DELAY_SLOT 1
+
     const Addr PageShift = 13;
     const Addr PageBytes = ULL(1) << PageShift;
     const Addr PageMask = ~(PageBytes - 1);

src/arch/sparc/isa_traits.hh

@@ -57,6 +57,9 @@ namespace SparcISA
     //This makes sure the big endian versions of certain functions are used.
     using namespace BigEndianGuest;
 
+    // Alpha Does NOT have a delay slot
+    #define ISA_HAS_DELAY_SLOT 1
+
     //TODO this needs to be a SPARC Noop
     // Alpha UNOP (ldq_u r31,0(r0))
     const MachInst NoopMachInst = 0x2ffe0000;