From 8110a422665f8a40dc639aab8db7a0fe33fc23ca Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Wed, 18 Jan 2023 08:53:02 +0000 Subject: [PATCH] arch-arm: Replace Loader with loader namespace in SME code This is fixing our nightly tests [1]. There was a merge conflict between the removal of the Loader namespace and the SME patches which were still using the old capitalized version [1]: https://jenkins.gem5.org/job/nightly/491/ Change-Id: I9f709b2fff252ed6fcc76cc984592e713ab53766 Signed-off-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67333 Reviewed-by: Daniel Carvalho Maintainer: Daniel Carvalho Reviewed-by: Richard Cooper Tested-by: kokoro --- src/arch/arm/insts/sme.cc | 18 +++++++++--------- src/arch/arm/insts/sme.hh | 18 +++++++++--------- src/arch/arm/insts/sve.cc | 4 ++-- src/arch/arm/insts/sve.hh | 4 ++-- 4 files changed, 22 insertions(+), 22 deletions(-) diff --git a/src/arch/arm/insts/sme.cc b/src/arch/arm/insts/sme.cc index 305d332514..43f4579842 100644 --- a/src/arch/arm/insts/sme.cc +++ b/src/arch/arm/insts/sme.cc @@ -45,7 +45,7 @@ namespace ArmISA std::string SmeAddOp::generateDisassembly(Addr pc, - const Loader::SymbolTable *symtab) const + const loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -61,7 +61,7 @@ SmeAddOp::generateDisassembly(Addr pc, std::string SmeAddVlOp::generateDisassembly(Addr pc, - const Loader::SymbolTable *symtab) const + const loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -76,7 +76,7 @@ SmeAddVlOp::generateDisassembly(Addr pc, std::string SmeLd1xSt1xOp::generateDisassembly(Addr pc, - const Loader::SymbolTable *symtab) const + const loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -94,7 +94,7 @@ SmeLd1xSt1xOp::generateDisassembly(Addr pc, std::string SmeLdrStrOp::generateDisassembly(Addr pc, - const Loader::SymbolTable *symtab) const + const loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -108,7 +108,7 @@ SmeLdrStrOp::generateDisassembly(Addr pc, std::string SmeMovExtractOp::generateDisassembly(Addr pc, - const Loader::SymbolTable *symtab) const + const loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -124,7 +124,7 @@ SmeMovExtractOp::generateDisassembly(Addr pc, std::string SmeMovInsertOp::generateDisassembly(Addr pc, - const Loader::SymbolTable *symtab) const + const loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -140,7 +140,7 @@ SmeMovInsertOp::generateDisassembly(Addr pc, std::string SmeOPOp::generateDisassembly(Addr pc, - const Loader::SymbolTable *symtab) const + const loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -158,7 +158,7 @@ SmeOPOp::generateDisassembly(Addr pc, std::string SmeRdsvlOp::generateDisassembly(Addr pc, - const Loader::SymbolTable *symtab) const + const loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -171,7 +171,7 @@ SmeRdsvlOp::generateDisassembly(Addr pc, std::string SmeZeroOp::generateDisassembly(Addr pc, - const Loader::SymbolTable *symtab) const + const loader::SymbolTable *symtab) const { std::stringstream ss; ArmStaticInst::printMnemonic(ss, "", false); diff --git a/src/arch/arm/insts/sme.hh b/src/arch/arm/insts/sme.hh index d6cbdde5a7..198ce52f77 100644 --- a/src/arch/arm/insts/sme.hh +++ b/src/arch/arm/insts/sme.hh @@ -63,7 +63,7 @@ class SmeAddOp : public ArmStaticInst {} std::string generateDisassembly( - Addr pc, const Loader::SymbolTable *symtab) const override; + Addr pc, const loader::SymbolTable *symtab) const override; }; // Used for the SME ADDSPL/ADDSVL instructions @@ -82,7 +82,7 @@ class SmeAddVlOp : public ArmStaticInst {} std::string generateDisassembly( - Addr pc, const Loader::SymbolTable *symtab) const override; + Addr pc, const loader::SymbolTable *symtab) const override; }; // Used for SME LD1x/ST1x instrucions @@ -105,7 +105,7 @@ class SmeLd1xSt1xOp : public ArmStaticInst {} std::string generateDisassembly( - Addr pc, const Loader::SymbolTable *symtab) const override; + Addr pc, const loader::SymbolTable *symtab) const override; }; // Used for SME LDR/STR instructions @@ -124,7 +124,7 @@ class SmeLdrStrOp : public ArmStaticInst {} std::string generateDisassembly( - Addr pc, const Loader::SymbolTable *symtab) const override; + Addr pc, const loader::SymbolTable *symtab) const override; }; // Used for SME MOVA (Tile to Vector) @@ -145,7 +145,7 @@ class SmeMovExtractOp : public ArmStaticInst {} std::string generateDisassembly( - Addr pc, const Loader::SymbolTable *symtab) const override; + Addr pc, const loader::SymbolTable *symtab) const override; }; // Used for SME MOVA (Vector to Tile) @@ -166,7 +166,7 @@ class SmeMovInsertOp : public ArmStaticInst {} std::string generateDisassembly( - Addr pc, const Loader::SymbolTable *symtab) const override; + Addr pc, const loader::SymbolTable *symtab) const override; }; // Used for SME output product instructions @@ -187,7 +187,7 @@ class SmeOPOp : public ArmStaticInst {} std::string generateDisassembly( - Addr pc, const Loader::SymbolTable *symtab) const override; + Addr pc, const loader::SymbolTable *symtab) const override; }; // Used for the SME RDSVL instruction @@ -204,7 +204,7 @@ class SmeRdsvlOp : public ArmStaticInst {} std::string generateDisassembly( - Addr pc, const Loader::SymbolTable *symtab) const override; + Addr pc, const loader::SymbolTable *symtab) const override; }; // Used for SME ZERO @@ -220,7 +220,7 @@ class SmeZeroOp : public ArmStaticInst {} std::string generateDisassembly( - Addr pc, const Loader::SymbolTable *symtab) const override; + Addr pc, const loader::SymbolTable *symtab) const override; }; } // namespace ArmISA diff --git a/src/arch/arm/insts/sve.cc b/src/arch/arm/insts/sve.cc index 9d9c2bcb1c..546074c8fd 100644 --- a/src/arch/arm/insts/sve.cc +++ b/src/arch/arm/insts/sve.cc @@ -163,7 +163,7 @@ SveWhileOp::generateDisassembly( std::string SvePselOp::generateDisassembly(Addr pc, - const Loader::SymbolTable *symtab) const + const loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); @@ -851,7 +851,7 @@ SveComplexIdxOp::generateDisassembly( std::string SveClampOp::generateDisassembly( - Addr pc, const Loader::SymbolTable *symtab) const + Addr pc, const loader::SymbolTable *symtab) const { std::stringstream ss; printMnemonic(ss, "", false); diff --git a/src/arch/arm/insts/sve.hh b/src/arch/arm/insts/sve.hh index 63a59d493a..66d82f0a3f 100644 --- a/src/arch/arm/insts/sve.hh +++ b/src/arch/arm/insts/sve.hh @@ -199,7 +199,7 @@ class SvePselOp : public ArmStaticInst {} std::string generateDisassembly( - Addr pc, const Loader::SymbolTable *symtab) const override; + Addr pc, const loader::SymbolTable *symtab) const override; }; /// Compare and terminate loop SVE instruction. @@ -989,7 +989,7 @@ class SveClampOp : public ArmStaticInst {} std::string generateDisassembly( - Addr pc, const Loader::SymbolTable *symtab) const override; + Addr pc, const loader::SymbolTable *symtab) const override; };