diff --git a/src/arch/arm/kvm/KvmGic.py b/src/arch/arm/kvm/KvmGic.py
index d4cbd6c8b2..d594f6ad38 100644
--- a/src/arch/arm/kvm/KvmGic.py
+++ b/src/arch/arm/kvm/KvmGic.py
@@ -38,20 +38,7 @@
 from m5.params import *
 from m5.proxy import *
 
-from Gic import BaseGic, Pl390
-from KvmVM import KvmVM
-from System import System
-
-class KvmGic(BaseGic):
-    type = 'KvmGic'
-    cxx_header = "arch/arm/kvm/gic.hh"
-
-    dist_addr = Param.Addr(0x1f001000, "Address for distributor")
-    cpu_addr = Param.Addr(0x1f000100, "Address for cpu")
-    it_lines = Param.UInt32(128, "Number of interrupt lines supported")
-
-    system = Param.System(Parent.any,
-                          'System this interrupt controller belongs to')
+from Gic import Pl390
 
 class MuxingKvmGic(Pl390):
     type = 'MuxingKvmGic'
diff --git a/src/arch/arm/kvm/gic.cc b/src/arch/arm/kvm/gic.cc
index 7bc1ba59fd..64fb7c6c6f 100644
--- a/src/arch/arm/kvm/gic.cc
+++ b/src/arch/arm/kvm/gic.cc
@@ -44,7 +44,6 @@
 
 #include "arch/arm/kvm/base_cpu.hh"
 #include "debug/Interrupt.hh"
-#include "params/KvmGic.hh"
 #include "params/MuxingKvmGic.hh"
 
 KvmKernelGicV2::KvmKernelGicV2(KvmVM &_vm, Addr cpu_addr, Addr dist_addr,
@@ -106,88 +105,6 @@ KvmKernelGicV2::setIntState(unsigned type, unsigned vcpu, unsigned irq,
 }
 
 
-KvmGic::KvmGic(const KvmGicParams *p)
-    : BaseGic(p),
-      system(*p->system),
-      kernelGic(*system.getKvmVM(),
-                p->cpu_addr, p->dist_addr, p->it_lines),
-      addrRanges{kernelGic.distRange, kernelGic.cpuRange}
-{
-}
-
-KvmGic::~KvmGic()
-{
-}
-
-void
-KvmGic::serialize(CheckpointOut &cp) const
-{
-    panic("Checkpointing unsupported\n");
-}
-
-void
-KvmGic::unserialize(CheckpointIn &cp)
-{
-    panic("Checkpointing unsupported\n");
-}
-
-Tick
-KvmGic::read(PacketPtr pkt)
-{
-    panic("KvmGic: PIO from gem5 is currently unsupported\n");
-}
-
-Tick
-KvmGic::write(PacketPtr pkt)
-{
-    panic("KvmGic: PIO from gem5 is currently unsupported\n");
-}
-
-void
-KvmGic::sendInt(uint32_t num)
-{
-    DPRINTF(Interrupt, "Set SPI %d\n", num);
-    kernelGic.setSPI(num);
-}
-
-void
-KvmGic::clearInt(uint32_t num)
-{
-    DPRINTF(Interrupt, "Clear SPI %d\n", num);
-    kernelGic.clearSPI(num);
-}
-
-void
-KvmGic::sendPPInt(uint32_t num, uint32_t cpu)
-{
-    DPRINTF(Interrupt, "Set PPI %d:%d\n", cpu, num);
-    kernelGic.setPPI(cpu, num);
-}
-
-void
-KvmGic::clearPPInt(uint32_t num, uint32_t cpu)
-{
-    DPRINTF(Interrupt, "Clear PPI %d:%d\n", cpu, num);
-    kernelGic.clearPPI(cpu, num);
-}
-
-void
-KvmGic::verifyMemoryMode() const
-{
-    if (!(system.isAtomicMode() && system.bypassCaches())) {
-        fatal("The in-kernel KVM GIC can only be used with KVM CPUs, but the "
-              "current memory mode does not support KVM.\n");
-    }
-}
-
-
-KvmGic *
-KvmGicParams::create()
-{
-    return new KvmGic(this);
-}
-
-
 MuxingKvmGic::MuxingKvmGic(const MuxingKvmGicParams *p)
     : Pl390(p),
       system(*p->system),
diff --git a/src/arch/arm/kvm/gic.hh b/src/arch/arm/kvm/gic.hh
index fc09da6a01..7e2e772b87 100644
--- a/src/arch/arm/kvm/gic.hh
+++ b/src/arch/arm/kvm/gic.hh
@@ -44,7 +44,6 @@
 #include "arch/arm/system.hh"
 #include "cpu/kvm/device.hh"
 #include "cpu/kvm/vm.hh"
-#include "dev/arm/base_gic.hh"
 #include "dev/arm/gic_pl390.hh"
 #include "dev/platform.hh"
 
@@ -138,74 +137,6 @@ class KvmKernelGicV2
     KvmDevice kdev;
 };
 
-struct KvmGicParams;
-
-/**
- * In-kernel GIC model.
- *
- * When using a KVM-based CPU model, it is possible to offload GIC
- * emulation to the kernel. This reduces some overheads when the guest
- * accesses the GIC and makes it possible to use in-kernel
- * architected/generic timer emulation.
- *
- * This device uses interfaces with the kernel GicV2 model that is
- * documented in Documentation/virtual/kvm/devices/arm-vgic.txt in the
- * Linux kernel sources.
- *
- * This GIC model has the following known limitations:
- * <ul>
- *   <li>Checkpointing is not supported.
- *   <li>This model only works with kvm. Simulated CPUs are not
- *       supported since this would require the kernel to inject
- *       interrupt into the simulated CPU.
- * </ul>
- *
- * @warn This GIC model cannot be used with simulated CPUs!
- */
-class KvmGic : public BaseGic
-{
-  public: // SimObject / Serializable / Drainable
-    KvmGic(const KvmGicParams *p);
-    ~KvmGic();
-
-    void startup() override { verifyMemoryMode(); }
-    void drainResume() override { verifyMemoryMode(); }
-
-    void serialize(CheckpointOut &cp) const override;
-    void unserialize(CheckpointIn &cp) override;
-
-  public: // PioDevice
-    AddrRangeList getAddrRanges() const { return addrRanges; }
-    Tick read(PacketPtr pkt) override;
-    Tick write(PacketPtr pkt) override;
-
-  public: // BaseGic
-    void sendInt(uint32_t num) override;
-    void clearInt(uint32_t num) override;
-
-    void sendPPInt(uint32_t num, uint32_t cpu) override;
-    void clearPPInt(uint32_t num, uint32_t cpu) override;
-
-  protected:
-    /**
-     * Do memory mode sanity checks
-     *
-     * This method only really exists to warn users that try to switch
-     * to a simulate CPU. There is no fool proof method to detect
-     * simulated CPUs, but checking that we're in atomic mode and
-     * bypassing caches should be robust enough.
-     */
-    void verifyMemoryMode() const;
-
-    /** System this interrupt controller belongs to */
-    System &system;
-
-    /** Kernel GIC device */
-    KvmKernelGicV2 kernelGic;
-
-    /** Union of all memory  */
-    const AddrRangeList addrRanges;
-};
 
 struct MuxingKvmGicParams;