stdlib,configs: Add DRAMSys to the gem5 standard library

Add DRAMSys as a new AbstractMemorySystem to the gem5 stdlib.
Also, provide convenient subclasses with predefined DRAMSys
configurations.

Add two new stdlib examples:
    - dramsys-traffic.py: Demonstrates the usage of DRAMSys
      using the stdlib TrafficGenerators
    - arm-hello-dramsys.py: A variant of the arm-hello.py
      script that uses DRAMSys as it's memory.

These DRAMSys memory components are only compiled into the standard
library if DRAMSys is not compiled into gem5.

Change-Id: I9db87c41fbd9c28bc44e9d6bde13fc225dc16be9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62914
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>

src/python/SConscript

@@ -170,6 +170,10 @@ PySource('gem5.components.cachehierarchies.ruby.topologies',
 PySource('gem5.components.memory', 'gem5/components/memory/__init__.py')
 PySource('gem5.components.memory', 'gem5/components/memory/abstract_memory_system.py')
 PySource('gem5.components.memory', 'gem5/components/memory/dramsim_3.py')
+
+if env['HAVE_DRAMSYS']:
+    PySource('gem5.components.memory', 'gem5/components/memory/dramsys.py')
+
 PySource('gem5.components.memory', 'gem5/components/memory/simple.py')
 PySource('gem5.components.memory', 'gem5/components/memory/memory.py')
 PySource('gem5.components.memory', 'gem5/components/memory/single_channel.py')

src/python/gem5/components/memory/__init__.py

@@ -34,3 +34,15 @@ from .multi_channel import DualChannelDDR3_2133
 from .multi_channel import DualChannelDDR4_2400
 from .multi_channel import DualChannelLPDDR3_1600
 from .hbm import HBM2Stack
+
+try:
+    from .dramsys import DRAMSysMem
+    from .dramsys import DRAMSysDDR4_1866
+    from .dramsys import DRAMSysDDR3_1600
+    from .dramsys import DRAMSysLPDDR4_3200
+    from .dramsys import DRAMSysHBM2
+except:
+    # In the case that DRAMSys is not compiled into the gem5 binary, importing
+    # DRAMSys components will fail. This try-exception statement is needed to
+    # ignore these imports in this case.
+    pass

src/python/gem5/components/memory/dramsys.py

@@ -25,17 +25,22 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 import m5
-import os
-import configparser
 
-from m5.objects import DRAMSys, AddrRange, Port, MemCtrl, Gem5ToTlmBridge32
+from m5.objects import (
+    DRAMSys,
+    AddrRange,
+    Port,
+    MemCtrl,
+    Gem5ToTlmBridge32,
+    SystemC_Kernel,
+)
 from m5.util.convert import toMemorySize
 
 from ...utils.override import overrides
 from ..boards.abstract_board import AbstractBoard
 from .abstract_memory_system import AbstractMemorySystem
 
-from typing import Optional, Tuple, Sequence, List
+from typing import Tuple, Sequence, List
 
 
 class DRAMSysMem(AbstractMemorySystem):
@@ -60,8 +65,9 @@ class DRAMSysMem(AbstractMemorySystem):
         )
 
         self._size = toMemorySize(size)
-        self._bridge = Gem5ToTlmBridge32()
-        self.dramsys.port = self._bridge.tlm
+        self.bridge = Gem5ToTlmBridge32()
+        self.dramsys.tlm = self.bridge.tlm
+        self.kernel = SystemC_Kernel()
 
     @overrides(AbstractMemorySystem)
     def incorporate_memory(self, board: AbstractBoard) -> None:
@@ -69,7 +75,7 @@ class DRAMSysMem(AbstractMemorySystem):
 
     @overrides(AbstractMemorySystem)
     def get_mem_ports(self) -> Sequence[Tuple[AddrRange, Port]]:
-        return [(self.dramsys.range, self._bridge.gem5)]
+        return [(self.dramsys.range, self.bridge.gem5)]
 
     @overrides(AbstractMemorySystem)
     def get_memory_controllers(self) -> List[MemCtrl]:
@@ -87,3 +93,60 @@ class DRAMSysMem(AbstractMemorySystem):
                 "range which matches the memory's size."
             )
         self.dramsys.range = ranges[0]
+        self.bridge.addr_ranges = ranges[0]
+
+
+class DRAMSysDDR4_1866(DRAMSysMem):
+    def __init__(self, recordable: bool):
+        """
+        :param recordable: Whether the database recording feature of DRAMSys is enabled.
+        """
+        super().__init__(
+            configuration="ext/dramsys/DRAMSys/DRAMSys/"
+            "library/resources/simulations/ddr4-example.json",
+            size="4GB",
+            resource_directory="ext/dramsys/DRAMSys/DRAMSys/library/resources",
+            recordable=recordable,
+        )
+
+
+class DRAMSysDDR3_1600(DRAMSysMem):
+    def __init__(self, recordable: bool):
+        """
+        :param recordable: Whether the database recording feature of DRAMSys is enabled.
+        """
+        super().__init__(
+            configuration="ext/dramsys/DRAMSys/DRAMSys/"
+            "library/resources/simulations/ddr3-gem5-se.json",
+            size="4GB",
+            resource_directory="ext/dramsys/DRAMSys/DRAMSys/library/resources",
+            recordable=recordable,
+        )
+
+
+class DRAMSysLPDDR4_3200(DRAMSysMem):
+    def __init__(self, recordable: bool):
+        """
+        :param recordable: Whether the database recording feature of DRAMSys is enabled.
+        """
+        super().__init__(
+            configuration="ext/dramsys/DRAMSys/DRAMSys/"
+            "library/resources/simulations/lpddr4-example.json",
+            size="4GB",
+            resource_directory="ext/dramsys/DRAMSys/DRAMSys/library/resources",
+            recordable=recordable,
+        )
+
+
+class DRAMSysHBM2(DRAMSysMem):
+    def __init__(self, recordable: bool):
+        """
+        :param recordable: Whether the database recording feature of DRAMSys is enabled.
+        """
+        super().__init__(
+            configuration="ext/dramsys/DRAMSys/DRAMSys/"
+            "library/resources/simulations/hbm2-example.json",
+            size="4GB",
+            resource_directory="ext/dramsys/DRAMSys/DRAMSys/library/resources",
+            recordable=recordable,
+        )