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Standardize clock parameter names to 'clock'.

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Fix description for Bus clock_ratio (no longer a ratio).
Add Clock param type (generic Frequency or Latency).

cpu/base_cpu.cc:
cpu/base_cpu.hh:
cpu/beta_cpu/alpha_full_cpu_builder.cc:
cpu/simple_cpu/simple_cpu.cc:
dev/ide_ctrl.cc:
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/pciconfigall.cc:
dev/sinic.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/uart.cc:
python/m5/objects/BaseCPU.py:
python/m5/objects/BaseCache.py:
python/m5/objects/BaseSystem.py:
python/m5/objects/Bus.py:
python/m5/objects/Ethernet.py:
python/m5/objects/Root.py:
sim/universe.cc:
    Standardize clock parameter names to 'clock'.
    Fix description for Bus clock_ratio (no longer a ratio).
python/m5/config.py:
    Minor tweaks on Frequency/Latency:
    - added new Clock param type to avoid ambiguities
    - factored out init code into getLatency()
    - made RootFrequency *not* a subclass of Frequency so it
    can't be directly assigned to a Frequency paremeter

--HG--
extra : convert_revision : fc4bb8562df171b454bbf696314cda57e1ec8506
This commit is contained in:
Steve Reinhardt
2005-06-01 21:44:00 -04:00
parent 3304da9270
commit 8031cd93b5
21 changed files with 105 additions and 88 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
dev/ide_ctrl.cc
View File

@@ -99,7 +99,7 @@ IdeController::IdeController(Params *p)
params()->host_bus,
params()->host_bus, 1,
true);
pioLatency = params()->pio_latency * params()->host_bus->clockRatio;
pioLatency = params()->pio_latency * params()->host_bus->clockRate;
}
// setup the disks attached to controller

12
dev/ns_gige.cc
View File

@@ -94,7 +94,7 @@ NSGigE::NSGigE(Params *p)
: PciDev(p), ioEnable(false),
txFifo(p->tx_fifo_size), rxFifo(p->rx_fifo_size),
txPacket(0), rxPacket(0), txPacketBufPtr(NULL), rxPacketBufPtr(NULL),
txXferLen(0), rxXferLen(0), cycleTime(p->cycle_time),
txXferLen(0), rxXferLen(0), clock(p->clock),
txState(txIdle), txEnable(false), CTDD(false),
txFragPtr(0), txDescCnt(0), txDmaState(dmaIdle), rxState(rxIdle),
rxEnable(false), CRDD(false), rxPktBytes(0),
@@ -115,7 +115,7 @@ NSGigE::NSGigE(Params *p)
p->header_bus, this,
&NSGigE::cacheAccess);
pioLatency = p->pio_latency * p->header_bus->clockRatio;
pioLatency = p->pio_latency * p->header_bus->clockRate;
if (p->payload_bus)
dmaInterface = new DMAInterface<Bus>(name() + ".dma",
@@ -132,7 +132,7 @@ NSGigE::NSGigE(Params *p)
p->payload_bus, this,
&NSGigE::cacheAccess);
pioLatency = p->pio_latency * p->payload_bus->clockRatio;
pioLatency = p->pio_latency * p->payload_bus->clockRate;
dmaInterface = new DMAInterface<Bus>(name() + ".dma",
p->payload_bus,
@@ -2689,7 +2689,7 @@ REGISTER_SIM_OBJECT("NSGigEInt", NSGigEInt)
BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
Param<Addr> addr;
Param<Tick> cycle_time;
Param<Tick> clock;
Param<Tick> tx_delay;
Param<Tick> rx_delay;
Param<Tick> intr_delay;
@@ -2723,7 +2723,7 @@ END_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigE)
INIT_PARAM(addr, "Device Address"),
INIT_PARAM(cycle_time, "State machine processor frequency"),
INIT_PARAM(clock, "State machine processor frequency"),
INIT_PARAM(tx_delay, "Transmit Delay"),
INIT_PARAM(rx_delay, "Receive Delay"),
INIT_PARAM(intr_delay, "Interrupt Delay in microseconds"),
@@ -2769,7 +2769,7 @@ CREATE_SIM_OBJECT(NSGigE)
params->deviceNum = pci_dev;
params->functionNum = pci_func;
params->cycle_time = cycle_time;
params->clock = clock;
params->intr_delay = intr_delay;
params->pmem = physmem;
params->tx_delay = tx_delay;

6
dev/ns_gige.hh
View File

@@ -176,8 +176,8 @@ class NSGigE : public PciDev
ns_desc rxDescCache;
/* state machine cycle time */
Tick cycleTime;
inline Tick cycles(int numCycles) const { return numCycles * cycleTime; }
Tick clock;
inline Tick cycles(int numCycles) const { return numCycles * clock; }
/* tx State Machine */
TxState txState;
@@ -328,7 +328,7 @@ class NSGigE : public PciDev
HierParams *hier;
Bus *header_bus;
Bus *payload_bus;
Tick cycle_time;
Tick clock;
Tick intr_delay;
Tick tx_delay;
Tick rx_delay;

2
dev/pciconfigall.cc
View File

@@ -59,7 +59,7 @@ PciConfigAll::PciConfigAll(const string &name,
pioInterface = newPioInterface(name, hier, bus, this,
&PciConfigAll::cacheAccess);
pioInterface->addAddrRange(RangeSize(addr, size));
pioLatency = pio_latency * bus->clockRatio;
pioLatency = pio_latency * bus->clockRate;
}
// Make all the pointers to devices null

4
dev/sinic.cc
View File

@@ -98,7 +98,7 @@ Device::Device(Params *p)
pioInterface = newPioInterface(p->name, p->hier, p->io_bus, this,
&Device::cacheAccess);
pioLatency = p->pio_latency * p->io_bus->clockRatio;
pioLatency = p->pio_latency * p->io_bus->clockRate;
if (p->payload_bus)
dmaInterface = new DMAInterface<Bus>(p->name + ".dma", p->io_bus,
@@ -112,7 +112,7 @@ Device::Device(Params *p)
pioInterface = newPioInterface(p->name, p->hier, p->payload_bus, this,
&Device::cacheAccess);
pioLatency = p->pio_latency * p->payload_bus->clockRatio;
pioLatency = p->pio_latency * p->payload_bus->clockRate;
dmaInterface = new DMAInterface<Bus>(p->name + ".dma", p->payload_bus,
p->payload_bus, 1,

2
dev/tsunami_cchip.cc
View File

@@ -59,7 +59,7 @@ TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a,
pioInterface = newPioInterface(name, hier, bus, this,
&TsunamiCChip::cacheAccess);
pioInterface->addAddrRange(RangeSize(addr, size));
pioLatency = pio_latency * bus->clockRatio;
pioLatency = pio_latency * bus->clockRate;
}
drir = 0;

2
dev/tsunami_io.cc
View File

@@ -175,7 +175,7 @@ TsunamiIO::TsunamiIO(const string &name, Tsunami *t, time_t init_time,
pioInterface = newPioInterface(name, hier, bus, this,
&TsunamiIO::cacheAccess);
pioInterface->addAddrRange(RangeSize(addr, size));
pioLatency = pio_latency * bus->clockRatio;
pioLatency = pio_latency * bus->clockRate;
}
// set the back pointer from tsunami to myself

2
dev/tsunami_pchip.cc
View File

@@ -65,7 +65,7 @@ TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a,
pioInterface = newPioInterface(name, hier, bus, this,
&TsunamiPChip::cacheAccess);
pioInterface->addAddrRange(RangeSize(addr, size));
pioLatency = pio_latency * bus->clockRatio;
pioLatency = pio_latency * bus->clockRate;
}

2
dev/uart.cc
View File

@@ -109,7 +109,7 @@ Uart::Uart(const string &name, SimConsole *c, MemoryController *mmu, Addr a,
pioInterface = newPioInterface(name, hier, bus, this,
&Uart::cacheAccess);
pioInterface->addAddrRange(RangeSize(addr, size));
pioLatency = pio_latency * bus->clockRatio;
pioLatency = pio_latency * bus->clockRate;
}
readAddr = 0;