mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner

Change-Id: I29214278c3dd4829c89a6f7c93214b8123912e74
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67452
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

src/arch/amdgpu/common/tlb.hh

@@ -214,7 +214,7 @@ namespace X86ISA
           public:
             CpuSidePort(const std::string &_name, GpuTLB * gpu_TLB,
                         PortID _index)
-                : ResponsePort(_name, gpu_TLB), tlb(gpu_TLB), index(_index) { }
+                : ResponsePort(_name), tlb(gpu_TLB), index(_index) { }
 
           protected:
             GpuTLB *tlb;
@@ -241,7 +241,7 @@ namespace X86ISA
           public:
             MemSidePort(const std::string &_name, GpuTLB * gpu_TLB,
                         PortID _index)
-                : RequestPort(_name, gpu_TLB), tlb(gpu_TLB), index(_index) { }
+                : RequestPort(_name), tlb(gpu_TLB), index(_index) { }
 
             std::deque<PacketPtr> retries;
 

src/arch/amdgpu/common/tlb_coalescer.hh

@@ -124,7 +124,7 @@ class TLBCoalescer : public ClockedObject
       public:
         CpuSidePort(const std::string &_name, TLBCoalescer *tlb_coalescer,
                     PortID _index)
-            : ResponsePort(_name, tlb_coalescer), coalescer(tlb_coalescer),
+            : ResponsePort(_name), coalescer(tlb_coalescer),
               index(_index) { }
 
       protected:

src/arch/amdgpu/vega/pagetable_walker.hh

@@ -59,7 +59,7 @@ class Walker : public ClockedObject
     {
       public:
         WalkerPort(const std::string &_name, Walker * _walker) :
-            RequestPort(_name, _walker), walker(_walker)
+            RequestPort(_name), walker(_walker)
         {}
 
       protected:

src/arch/amdgpu/vega/tlb.hh

@@ -215,7 +215,7 @@ class GpuTLB : public ClockedObject
       public:
         CpuSidePort(const std::string &_name, GpuTLB * gpu_TLB,
                     PortID _index)
-            : ResponsePort(_name, gpu_TLB), tlb(gpu_TLB), index(_index) { }
+            : ResponsePort(_name), tlb(gpu_TLB), index(_index) { }
 
       protected:
         GpuTLB *tlb;
@@ -242,7 +242,7 @@ class GpuTLB : public ClockedObject
       public:
         MemSidePort(const std::string &_name, GpuTLB * gpu_TLB,
                     PortID _index)
-            : RequestPort(_name, gpu_TLB), tlb(gpu_TLB), index(_index) { }
+            : RequestPort(_name), tlb(gpu_TLB), index(_index) { }
 
         std::deque<PacketPtr> retries;
 

src/arch/amdgpu/vega/tlb_coalescer.hh

@@ -137,7 +137,7 @@ class VegaTLBCoalescer : public ClockedObject
       public:
         CpuSidePort(const std::string &_name, VegaTLBCoalescer *tlb_coalescer,
                     PortID _index)
-            : ResponsePort(_name, tlb_coalescer), coalescer(tlb_coalescer),
+            : ResponsePort(_name), coalescer(tlb_coalescer),
               index(_index) { }
 
       protected:
@@ -165,7 +165,7 @@ class VegaTLBCoalescer : public ClockedObject
       public:
         MemSidePort(const std::string &_name, VegaTLBCoalescer *tlb_coalescer,
                     PortID _index)
-            : RequestPort(_name, tlb_coalescer), coalescer(tlb_coalescer),
+            : RequestPort(_name), coalescer(tlb_coalescer),
               index(_index) { }
 
         std::deque<PacketPtr> retries;

src/arch/arm/table_walker.cc

@@ -62,7 +62,7 @@ using namespace ArmISA;
 TableWalker::TableWalker(const Params &p)
     : ClockedObject(p),
       requestorId(p.sys->getRequestorId(this)),
-      port(new Port(this, requestorId)),
+      port(new Port(*this, requestorId)),
       isStage2(p.is_stage2), tlb(NULL),
       currState(NULL), pending(false),
       numSquashable(p.num_squash_per_cycle),
@@ -138,10 +138,11 @@ TableWalker::WalkerState::WalkerState() :
 {
 }
 
-TableWalker::Port::Port(TableWalker *_walker, RequestorID id)
+TableWalker::Port::Port(TableWalker& _walker, RequestorID id)
-  : QueuedRequestPort(_walker->name() + ".port", _walker,
+  : QueuedRequestPort(_walker.name() + ".port", reqQueue, snoopRespQueue),
-        reqQueue, snoopRespQueue),
+    owner{_walker},
-    reqQueue(*_walker, *this), snoopRespQueue(*_walker, *this),
+    reqQueue(_walker, *this),
+    snoopRespQueue(_walker, *this),
     requestorId(id)
 {
 }

src/arch/arm/table_walker.hh

@@ -941,7 +941,7 @@ class TableWalker : public ClockedObject
     class Port : public QueuedRequestPort
     {
       public:
-        Port(TableWalker* _walker, RequestorID id);
+        Port(TableWalker& _walker, RequestorID id);
 
         void sendFunctionalReq(Addr desc_addr, int size,
             uint8_t *data, Request::Flags flag);
@@ -963,6 +963,8 @@ class TableWalker : public ClockedObject
                                Tick delay, Event *event);
 
       private:
+        TableWalker& owner;
+
         /** Packet queue used to store outgoing requests. */
         ReqPacketQueue reqQueue;
 

src/arch/riscv/pagetable_walker.hh

@@ -68,7 +68,7 @@ namespace RiscvISA
         {
           public:
             WalkerPort(const std::string &_name, Walker * _walker) :
-                  RequestPort(_name, _walker), walker(_walker)
+                  RequestPort(_name), walker(_walker)
             {}
 
           protected:

src/arch/x86/pagetable_walker.hh

@@ -65,7 +65,7 @@ namespace X86ISA
         {
           public:
             WalkerPort(const std::string &_name, Walker * _walker) :
-                  RequestPort(_name, _walker), walker(_walker)
+                  RequestPort(_name), walker(_walker)
             {}
 
           protected:

src/cpu/kvm/base.hh

@@ -601,7 +601,7 @@ class BaseKvmCPU : public BaseCPU
 
       public:
         KVMCpuPort(const std::string &_name, BaseKvmCPU *_cpu)
-            : RequestPort(_name, _cpu), cpu(_cpu), activeMMIOReqs(0)
+            : RequestPort(_name), cpu(_cpu), activeMMIOReqs(0)
         { }
         /**
          * Interface to send Atomic or Timing IO request.  Assumes that the pkt

src/cpu/minor/cpu.hh

@@ -110,7 +110,7 @@ class MinorCPU : public BaseCPU
 
       public:
         MinorCPUPort(const std::string& name_, MinorCPU &cpu_)
-            : RequestPort(name_, &cpu_), cpu(cpu_)
+            : RequestPort(name_), cpu(cpu_)
         { }
 
     };

src/cpu/o3/fetch.cc

@@ -76,7 +76,7 @@ namespace o3
 {
 
 Fetch::IcachePort::IcachePort(Fetch *_fetch, CPU *_cpu) :
-        RequestPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch)
+        RequestPort(_cpu->name() + ".icache_port"), fetch(_fetch)
 {}
 
 

src/cpu/o3/lsq.cc

@@ -65,7 +65,7 @@ namespace o3
 {
 
 LSQ::DcachePort::DcachePort(LSQ *_lsq, CPU *_cpu) :
-    RequestPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq), cpu(_cpu)
+    RequestPort(_cpu->name() + ".dcache_port"), lsq(_lsq), cpu(_cpu)
 {}
 
 LSQ::LSQ(CPU *cpu_ptr, IEW *iew_ptr, const BaseO3CPUParams &params)

src/cpu/simple/atomic.cc

@@ -78,7 +78,7 @@ AtomicSimpleCPU::AtomicSimpleCPU(const BaseAtomicSimpleCPUParams &p)
       width(p.width), locked(false),
       simulate_data_stalls(p.simulate_data_stalls),
       simulate_inst_stalls(p.simulate_inst_stalls),
-      icachePort(name() + ".icache_port", this),
+      icachePort(name() + ".icache_port"),
       dcachePort(name() + ".dcache_port", this),
       dcache_access(false), dcache_latency(0),
       ppCommit(nullptr)
@@ -281,8 +281,6 @@ AtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(PacketPtr pkt)
             __func__, pkt->getAddr(), pkt->cmdString());
 
     // X86 ISA: Snooping an invalidation for monitor/mwait
-    AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner);
-
     for (ThreadID tid = 0; tid < cpu->numThreads; tid++) {
         if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) {
             cpu->wakeup(tid);
@@ -312,7 +310,6 @@ AtomicSimpleCPU::AtomicCPUDPort::recvFunctionalSnoop(PacketPtr pkt)
             __func__, pkt->getAddr(), pkt->cmdString());
 
     // X86 ISA: Snooping an invalidation for monitor/mwait
-    AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner);
     for (ThreadID tid = 0; tid < cpu->numThreads; tid++) {
         if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) {
             cpu->wakeup(tid);

src/cpu/simple/atomic.hh

@@ -117,8 +117,8 @@ class AtomicSimpleCPU : public BaseSimpleCPU
 
       public:
 
-        AtomicCPUPort(const std::string &_name, BaseSimpleCPU* _cpu)
+        AtomicCPUPort(const std::string &_name)
-            : RequestPort(_name, _cpu)
+            : RequestPort(_name)
         { }
 
       protected:
@@ -142,7 +142,7 @@ class AtomicSimpleCPU : public BaseSimpleCPU
 
       public:
         AtomicCPUDPort(const std::string &_name, BaseSimpleCPU *_cpu)
-            : AtomicCPUPort(_name, _cpu), cpu(_cpu)
+            : AtomicCPUPort(_name), cpu(_cpu)
         {
             cacheBlockMask = ~(cpu->cacheLineSize() - 1);
         }

src/cpu/simple/timing.hh

@@ -164,7 +164,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
       public:
 
         TimingCPUPort(const std::string& _name, TimingSimpleCPU* _cpu)
-            : RequestPort(_name, _cpu), cpu(_cpu),
+            : RequestPort(_name), cpu(_cpu),
               retryRespEvent([this]{ sendRetryResp(); }, name())
         { }
 

src/cpu/testers/directedtest/RubyDirectedTester.hh

@@ -58,7 +58,7 @@ class RubyDirectedTester : public ClockedObject
       public:
         CpuPort(const std::string &_name, RubyDirectedTester *_tester,
                 PortID _id)
-            : RequestPort(_name, _tester, _id), tester(_tester)
+            : RequestPort(_name, _id), tester(_tester)
         {}
 
       protected:

src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh

@@ -84,7 +84,7 @@ class GarnetSyntheticTraffic : public ClockedObject
       public:
 
         CpuPort(const std::string &_name, GarnetSyntheticTraffic *_tester)
-            : RequestPort(_name, _tester), tester(_tester)
+            : RequestPort(_name), tester(_tester)
         { }
 
       protected:

src/cpu/testers/gpu_ruby_test/protocol_tester.hh

@@ -74,7 +74,7 @@ class ProtocolTester : public ClockedObject
       public:
         SeqPort(const std::string &_name, ProtocolTester *_tester, PortID _id,
                 PortID _index)
-            : RequestPort(_name, _tester, _id)
+            : RequestPort(_name, _id)
         {}
 
       protected:

src/cpu/testers/memtest/memtest.hh

@@ -100,7 +100,7 @@ class MemTest : public ClockedObject
       public:
 
         CpuPort(const std::string &_name, MemTest &_memtest)
-            : RequestPort(_name, &_memtest), memtest(_memtest)
+            : RequestPort(_name), memtest(_memtest)
         { }
 
       protected:

src/cpu/testers/rubytest/RubyTester.hh

@@ -76,7 +76,7 @@ class RubyTester : public ClockedObject
 
         CpuPort(const std::string &_name, RubyTester *_tester, PortID _id,
                 PortID _index)
-            : RequestPort(_name, _tester, _id), tester(_tester),
+            : RequestPort(_name, _id), tester(_tester),
               globalIdx(_index)
         {}
 

src/cpu/testers/traffic_gen/base.hh

@@ -132,7 +132,7 @@ class BaseTrafficGen : public ClockedObject
       public:
 
         TrafficGenPort(const std::string& name, BaseTrafficGen& traffic_gen)
-            : RequestPort(name, &traffic_gen), trafficGen(traffic_gen)
+            : RequestPort(name), trafficGen(traffic_gen)
         { }
 
       protected:

src/cpu/testers/traffic_gen/gups_gen.hh

@@ -87,7 +87,7 @@ class GUPSGen : public ClockedObject
       public:
 
         GenPort(const std::string& name, GUPSGen *owner) :
-            RequestPort(name, owner), owner(owner), _blocked(false),
+            RequestPort(name), owner(owner), _blocked(false),
             blockedPacket(nullptr)
         {}
 

src/cpu/trace/trace_cpu.hh

@@ -218,7 +218,7 @@ class TraceCPU : public BaseCPU
       public:
         /** Default constructor. */
         IcachePort(TraceCPU* _cpu) :
-            RequestPort(_cpu->name() + ".icache_port", _cpu), owner(_cpu)
+            RequestPort(_cpu->name() + ".icache_port"), owner(_cpu)
         {}
 
       public:
@@ -258,7 +258,7 @@ class TraceCPU : public BaseCPU
       public:
         /** Default constructor. */
         DcachePort(TraceCPU* _cpu) :
-            RequestPort(_cpu->name() + ".dcache_port", _cpu), owner(_cpu)
+            RequestPort(_cpu->name() + ".dcache_port"), owner(_cpu)
         {}
 
       public:

src/dev/arm/gic_v3_its.hh

@@ -94,7 +94,7 @@ class Gicv3Its : public BasicPioDevice
 
       public:
         DataPort(const std::string &_name, Gicv3Its &_its) :
-            RequestPort(_name, &_its),
+            RequestPort(_name),
             its(_its)
         {}
 

src/dev/arm/smmu_v3_ports.cc

@@ -45,7 +45,7 @@ namespace gem5
 {
 
 SMMURequestPort::SMMURequestPort(const std::string &_name, SMMUv3 &_smmu) :
-    RequestPort(_name, &_smmu),
+    RequestPort(_name),
     smmu(_smmu)
 {}
 
@@ -63,7 +63,7 @@ SMMURequestPort::recvReqRetry()
 
 SMMUTableWalkPort::SMMUTableWalkPort(const std::string &_name,
                                                  SMMUv3 &_smmu) :
-    RequestPort(_name, &_smmu),
+    RequestPort(_name),
     smmu(_smmu)
 {}
 
@@ -83,7 +83,7 @@ SMMUDevicePort::SMMUDevicePort(const std::string &_name,
                              SMMUv3DeviceInterface &_ifc,
                              PortID _id)
 :
-    QueuedResponsePort(_name, &_ifc, respQueue, _id),
+    QueuedResponsePort(_name, respQueue, _id),
     ifc(_ifc),
     respQueue(_ifc, *this)
 {}
@@ -141,7 +141,7 @@ SMMUControlPort::getAddrRanges() const
 
 SMMUATSMemoryPort::SMMUATSMemoryPort(const std::string &_name,
                                      SMMUv3DeviceInterface &_ifc) :
-    QueuedRequestPort(_name, &_ifc, reqQueue, snoopRespQueue),
+    QueuedRequestPort(_name, reqQueue, snoopRespQueue),
     ifc(_ifc),
     reqQueue(_ifc, *this),
     snoopRespQueue(_ifc, *this)
@@ -155,7 +155,7 @@ SMMUATSMemoryPort::recvTimingResp(PacketPtr pkt)
 
 SMMUATSDevicePort::SMMUATSDevicePort(const std::string &_name,
                                    SMMUv3DeviceInterface &_ifc) :
-    QueuedResponsePort(_name, &_ifc, respQueue),
+    QueuedResponsePort(_name, respQueue),
     ifc(_ifc),
     respQueue(_ifc, *this)
 {}

src/dev/dma_device.cc

@@ -57,7 +57,7 @@ namespace gem5
 
 DmaPort::DmaPort(ClockedObject *dev, System *s,
                  uint32_t sid, uint32_t ssid)
-    : RequestPort(dev->name() + ".dma", dev),
+    : RequestPort(dev->name() + ".dma"),
       device(dev), sys(s), requestorId(s->getRequestorId(dev)),
       sendEvent([this]{ sendDma(); }, dev->name()),
       defaultSid(sid), defaultSSid(ssid), cacheLineSize(s->cacheLineSize())

src/dev/x86/intdev.hh

@@ -118,7 +118,7 @@ class IntRequestPort : public QueuedRequestPort
   public:
     IntRequestPort(const std::string& _name, SimObject* _parent,
                   Device* dev, Tick _latency) :
-        QueuedRequestPort(_name, _parent, reqQueue, snoopRespQueue),
+        QueuedRequestPort(_name, reqQueue, snoopRespQueue),
         reqQueue(*_parent, *this), snoopRespQueue(*_parent, *this),
         device(dev), latency(_latency)
     {

src/gpu-compute/compute_unit.hh

@@ -514,7 +514,7 @@ class ComputeUnit : public ClockedObject
     {
       public:
         DataPort(const std::string &_name, ComputeUnit *_cu, PortID id)
-            : RequestPort(_name, _cu, id), computeUnit(_cu) { }
+            : RequestPort(_name, id), computeUnit(_cu) { }
 
         bool snoopRangeSent;
 
@@ -586,7 +586,7 @@ class ComputeUnit : public ClockedObject
     {
       public:
         ScalarDataPort(const std::string &_name, ComputeUnit *_cu)
-            : RequestPort(_name, _cu), computeUnit(_cu)
+            : RequestPort(_name), computeUnit(_cu)
         {
         }
 
@@ -657,7 +657,7 @@ class ComputeUnit : public ClockedObject
     {
       public:
         SQCPort(const std::string &_name, ComputeUnit *_cu)
-            : RequestPort(_name, _cu), computeUnit(_cu) { }
+            : RequestPort(_name), computeUnit(_cu) { }
 
         bool snoopRangeSent;
 
@@ -698,7 +698,7 @@ class ComputeUnit : public ClockedObject
     {
       public:
         DTLBPort(const std::string &_name, ComputeUnit *_cu, PortID id)
-            : RequestPort(_name, _cu, id), computeUnit(_cu),
+            : RequestPort(_name, id), computeUnit(_cu),
               stalled(false)
         { }
 
@@ -745,7 +745,7 @@ class ComputeUnit : public ClockedObject
     {
       public:
         ScalarDTLBPort(const std::string &_name, ComputeUnit *_cu)
-            : RequestPort(_name, _cu), computeUnit(_cu), stalled(false)
+            : RequestPort(_name), computeUnit(_cu), stalled(false)
         {
         }
 
@@ -773,7 +773,7 @@ class ComputeUnit : public ClockedObject
     {
       public:
         ITLBPort(const std::string &_name, ComputeUnit *_cu)
-            : RequestPort(_name, _cu), computeUnit(_cu), stalled(false) { }
+            : RequestPort(_name), computeUnit(_cu), stalled(false) { }
 
 
         bool isStalled() { return stalled; }
@@ -815,7 +815,7 @@ class ComputeUnit : public ClockedObject
     {
       public:
         LDSPort(const std::string &_name, ComputeUnit *_cu)
-        : RequestPort(_name, _cu), computeUnit(_cu)
+        : RequestPort(_name), computeUnit(_cu)
         {
         }
 

src/gpu-compute/lds_state.hh

@@ -183,7 +183,7 @@ class LdsState: public ClockedObject
     {
       public:
         CuSidePort(const std::string &_name, LdsState *_ownerLds) :
-                ResponsePort(_name, _ownerLds), ownerLds(_ownerLds)
+                ResponsePort(_name), ownerLds(_ownerLds)
         {
         }
 

src/learning_gem5/part2/simple_cache.hh

@@ -74,7 +74,7 @@ class SimpleCache : public ClockedObject
          * Constructor. Just calls the superclass constructor.
          */
         CPUSidePort(const std::string& name, int id, SimpleCache *owner) :
-            ResponsePort(name, owner), id(id), owner(owner), needRetry(false),
+            ResponsePort(name), id(id), owner(owner), needRetry(false),
             blockedPacket(nullptr)
         { }
 
@@ -154,7 +154,7 @@ class SimpleCache : public ClockedObject
          * Constructor. Just calls the superclass constructor.
          */
         MemSidePort(const std::string& name, SimpleCache *owner) :
-            RequestPort(name, owner), owner(owner), blockedPacket(nullptr)
+            RequestPort(name), owner(owner), blockedPacket(nullptr)
         { }
 
         /**

src/learning_gem5/part2/simple_memobj.hh

@@ -68,7 +68,7 @@ class SimpleMemobj : public SimObject
          * Constructor. Just calls the superclass constructor.
          */
         CPUSidePort(const std::string& name, SimpleMemobj *owner) :
-            ResponsePort(name, owner), owner(owner), needRetry(false),
+            ResponsePort(name), owner(owner), needRetry(false),
             blockedPacket(nullptr)
         { }
 
@@ -147,7 +147,7 @@ class SimpleMemobj : public SimObject
          * Constructor. Just calls the superclass constructor.
          */
         MemSidePort(const std::string& name, SimpleMemobj *owner) :
-            RequestPort(name, owner), owner(owner), blockedPacket(nullptr)
+            RequestPort(name), owner(owner), blockedPacket(nullptr)
         { }
 
         /**

src/mem/addr_mapper.hh

@@ -101,7 +101,7 @@ class AddrMapper : public SimObject
     {
       public:
         MapperRequestPort(const std::string& _name, AddrMapper& _mapper)
-            : RequestPort(_name, &_mapper), mapper(_mapper)
+            : RequestPort(_name), mapper(_mapper)
         { }
 
       protected:
@@ -158,7 +158,7 @@ class AddrMapper : public SimObject
     {
       public:
         MapperResponsePort(const std::string& _name, AddrMapper& _mapper)
-            : ResponsePort(_name, &_mapper), mapper(_mapper)
+            : ResponsePort(_name), mapper(_mapper)
         {}
 
       protected:

src/mem/bridge.cc

@@ -58,7 +58,7 @@ Bridge::BridgeResponsePort::BridgeResponsePort(const std::string& _name,
                                          BridgeRequestPort& _memSidePort,
                                          Cycles _delay, int _resp_limit,
                                          std::vector<AddrRange> _ranges)
-    : ResponsePort(_name, &_bridge), bridge(_bridge),
+    : ResponsePort(_name), bridge(_bridge),
       memSidePort(_memSidePort), delay(_delay),
       ranges(_ranges.begin(), _ranges.end()),
       outstandingResponses(0), retryReq(false), respQueueLimit(_resp_limit),
@@ -70,7 +70,7 @@ Bridge::BridgeRequestPort::BridgeRequestPort(const std::string& _name,
                                            Bridge& _bridge,
                                            BridgeResponsePort& _cpuSidePort,
                                            Cycles _delay, int _req_limit)
-    : RequestPort(_name, &_bridge), bridge(_bridge),
+    : RequestPort(_name), bridge(_bridge),
       cpuSidePort(_cpuSidePort),
       delay(_delay), reqQueueLimit(_req_limit),
       sendEvent([this]{ trySendTiming(); }, _name)

src/mem/cache/base.cc

@@ -67,10 +67,11 @@ namespace gem5
 {
 
 BaseCache::CacheResponsePort::CacheResponsePort(const std::string &_name,
-                                          BaseCache *_cache,
+                                          BaseCache& _cache,
                                           const std::string &_label)
-    : QueuedResponsePort(_name, _cache, queue),
+    : QueuedResponsePort(_name, queue),
-      queue(*_cache, *this, true, _label),
+      cache{_cache},
+      queue(_cache, *this, true, _label),
       blocked(false), mustSendRetry(false),
       sendRetryEvent([this]{ processSendRetry(); }, _name)
 {
@@ -78,7 +79,7 @@ BaseCache::CacheResponsePort::CacheResponsePort(const std::string &_name,
 
 BaseCache::BaseCache(const BaseCacheParams &p, unsigned blk_size)
     : ClockedObject(p),
-      cpuSidePort (p.name + ".cpu_side_port", this, "CpuSidePort"),
+      cpuSidePort (p.name + ".cpu_side_port", *this, "CpuSidePort"),
       memSidePort(p.name + ".mem_side_port", this, "MemSidePort"),
       mshrQueue("MSHRs", p.mshrs, 0, p.demand_mshr_reserve, p.name),
       writeBuffer("write buffer", p.write_buffers, p.mshrs, p.name),
@@ -150,7 +151,7 @@ BaseCache::CacheResponsePort::setBlocked()
     // if we already scheduled a retry in this cycle, but it has not yet
     // happened, cancel it
     if (sendRetryEvent.scheduled()) {
-        owner.deschedule(sendRetryEvent);
+        cache.deschedule(sendRetryEvent);
         DPRINTF(CachePort, "Port descheduled retry\n");
         mustSendRetry = true;
     }
@@ -164,7 +165,7 @@ BaseCache::CacheResponsePort::clearBlocked()
     blocked = false;
     if (mustSendRetry) {
         // @TODO: need to find a better time (next cycle?)
-        owner.schedule(sendRetryEvent, curTick() + 1);
+        cache.schedule(sendRetryEvent, curTick() + 1);
     }
 }
 
@@ -2522,12 +2523,12 @@ bool
 BaseCache::CpuSidePort::recvTimingSnoopResp(PacketPtr pkt)
 {
     // Snoops shouldn't happen when bypassing caches
-    assert(!cache->system->bypassCaches());
+    assert(!cache.system->bypassCaches());
 
     assert(pkt->isResponse());
 
     // Express snoop responses from requestor to responder, e.g., from L1 to L2
-    cache->recvTimingSnoopResp(pkt);
+    cache.recvTimingSnoopResp(pkt);
     return true;
 }
 
@@ -2535,7 +2536,7 @@ BaseCache::CpuSidePort::recvTimingSnoopResp(PacketPtr pkt)
 bool
 BaseCache::CpuSidePort::tryTiming(PacketPtr pkt)
 {
-    if (cache->system->bypassCaches() || pkt->isExpressSnoop()) {
+    if (cache.system->bypassCaches() || pkt->isExpressSnoop()) {
         // always let express snoop packets through even if blocked
         return true;
     } else if (blocked || mustSendRetry) {
@@ -2552,14 +2553,14 @@ BaseCache::CpuSidePort::recvTimingReq(PacketPtr pkt)
 {
     assert(pkt->isRequest());
 
-    if (cache->system->bypassCaches()) {
+    if (cache.system->bypassCaches()) {
         // Just forward the packet if caches are disabled.
         // @todo This should really enqueue the packet rather
-        [[maybe_unused]] bool success = cache->memSidePort.sendTimingReq(pkt);
+        [[maybe_unused]] bool success = cache.memSidePort.sendTimingReq(pkt);
         assert(success);
         return true;
     } else if (tryTiming(pkt)) {
-        cache->recvTimingReq(pkt);
+        cache.recvTimingReq(pkt);
         return true;
     }
     return false;
@@ -2568,39 +2569,39 @@ BaseCache::CpuSidePort::recvTimingReq(PacketPtr pkt)
 Tick
 BaseCache::CpuSidePort::recvAtomic(PacketPtr pkt)
 {
-    if (cache->system->bypassCaches()) {
+    if (cache.system->bypassCaches()) {
         // Forward the request if the system is in cache bypass mode.
-        return cache->memSidePort.sendAtomic(pkt);
+        return cache.memSidePort.sendAtomic(pkt);
     } else {
-        return cache->recvAtomic(pkt);
+        return cache.recvAtomic(pkt);
     }
 }
 
 void
 BaseCache::CpuSidePort::recvFunctional(PacketPtr pkt)
 {
-    if (cache->system->bypassCaches()) {
+    if (cache.system->bypassCaches()) {
         // The cache should be flushed if we are in cache bypass mode,
         // so we don't need to check if we need to update anything.
-        cache->memSidePort.sendFunctional(pkt);
+        cache.memSidePort.sendFunctional(pkt);
         return;
     }
 
     // functional request
-    cache->functionalAccess(pkt, true);
+    cache.functionalAccess(pkt, true);
 }
 
 AddrRangeList
 BaseCache::CpuSidePort::getAddrRanges() const
 {
-    return cache->getAddrRanges();
+    return cache.getAddrRanges();
 }
 
 
 BaseCache::
-CpuSidePort::CpuSidePort(const std::string &_name, BaseCache *_cache,
+CpuSidePort::CpuSidePort(const std::string &_name, BaseCache& _cache,
                          const std::string &_label)
-    : CacheResponsePort(_name, _cache, _label), cache(_cache)
+    : CacheResponsePort(_name, _cache, _label)
 {
 }
 
@@ -2687,7 +2688,7 @@ BaseCache::CacheReqPacketQueue::sendDeferredPacket()
 BaseCache::MemSidePort::MemSidePort(const std::string &_name,
                                     BaseCache *_cache,
                                     const std::string &_label)
-    : CacheRequestPort(_name, _cache, _reqQueue, _snoopRespQueue),
+    : CacheRequestPort(_name, _reqQueue, _snoopRespQueue),
       _reqQueue(*_cache, *this, _snoopRespQueue, _label),
       _snoopRespQueue(*_cache, *this, true, _label), cache(_cache)
 {

src/mem/cache/base.hh

@@ -165,10 +165,10 @@ class BaseCache : public ClockedObject
 
       protected:
 
-        CacheRequestPort(const std::string &_name, BaseCache *_cache,
+        CacheRequestPort(const std::string &_name,
                         ReqPacketQueue &_reqQueue,
                         SnoopRespPacketQueue &_snoopRespQueue) :
-            QueuedRequestPort(_name, _cache, _reqQueue, _snoopRespQueue)
+            QueuedRequestPort(_name, _reqQueue, _snoopRespQueue)
         { }
 
         /**
@@ -285,9 +285,11 @@ class BaseCache : public ClockedObject
 
       protected:
 
-        CacheResponsePort(const std::string &_name, BaseCache *_cache,
+        CacheResponsePort(const std::string &_name, BaseCache& _cache,
                        const std::string &_label);
 
+        BaseCache& cache;
+
         /** A normal packet queue used to store responses. */
         RespPacketQueue queue;
 
@@ -309,11 +311,6 @@ class BaseCache : public ClockedObject
      */
     class CpuSidePort : public CacheResponsePort
     {
-      private:
-
-        // a pointer to our specific cache implementation
-        BaseCache *cache;
-
       protected:
         virtual bool recvTimingSnoopResp(PacketPtr pkt) override;
 
@@ -329,7 +326,7 @@ class BaseCache : public ClockedObject
 
       public:
 
-        CpuSidePort(const std::string &_name, BaseCache *_cache,
+        CpuSidePort(const std::string &_name, BaseCache& _cache,
                     const std::string &_label);
 
     };

src/mem/cfi_mem.cc

@@ -464,7 +464,7 @@ CfiMemory::unserialize(CheckpointIn &cp)
 
 CfiMemory::MemoryPort::MemoryPort(const std::string& _name,
                                      CfiMemory& _memory)
-    : ResponsePort(_name, &_memory), mem(_memory)
+    : ResponsePort(_name), mem(_memory)
 { }
 
 AddrRangeList

src/mem/coherent_xbar.hh

@@ -100,7 +100,7 @@ class CoherentXBar : public BaseXBar
 
         CoherentXBarResponsePort(const std::string &_name,
                              CoherentXBar &_xbar, PortID _id)
-            : QueuedResponsePort(_name, &_xbar, queue, _id), xbar(_xbar),
+            : QueuedResponsePort(_name, queue, _id), xbar(_xbar),
               queue(_xbar, *this)
         { }
 
@@ -166,7 +166,7 @@ class CoherentXBar : public BaseXBar
 
         CoherentXBarRequestPort(const std::string &_name,
                               CoherentXBar &_xbar, PortID _id)
-            : RequestPort(_name, &_xbar, _id), xbar(_xbar)
+            : RequestPort(_name, _id), xbar(_xbar)
         { }
 
       protected:
@@ -228,7 +228,7 @@ class CoherentXBar : public BaseXBar
          */
         SnoopRespPort(QueuedResponsePort& cpu_side_port,
                       CoherentXBar& _xbar) :
-            RequestPort(cpu_side_port.name() + ".snoopRespPort", &_xbar),
+            RequestPort(cpu_side_port.name() + ".snoopRespPort"),
             cpuSidePort(cpu_side_port) { }
 
         /**

src/mem/comm_monitor.hh

@@ -124,7 +124,7 @@ class CommMonitor : public SimObject
       public:
 
         MonitorRequestPort(const std::string& _name, CommMonitor& _mon)
-            : RequestPort(_name, &_mon), mon(_mon)
+            : RequestPort(_name), mon(_mon)
         { }
 
       protected:
@@ -190,7 +190,7 @@ class CommMonitor : public SimObject
       public:
 
         MonitorResponsePort(const std::string& _name, CommMonitor& _mon)
-            : ResponsePort(_name, &_mon), mon(_mon)
+            : ResponsePort(_name), mon(_mon)
         { }
 
       protected:

src/mem/dramsim2.cc

@@ -359,7 +359,7 @@ DRAMSim2::drain()
 
 DRAMSim2::MemoryPort::MemoryPort(const std::string& _name,
                                  DRAMSim2& _memory)
-    : ResponsePort(_name, &_memory), mem(_memory)
+    : ResponsePort(_name), mem(_memory)
 { }
 
 AddrRangeList

src/mem/dramsim3.cc

@@ -357,7 +357,7 @@ DRAMsim3::drain()
 
 DRAMsim3::MemoryPort::MemoryPort(const std::string& _name,
                                  DRAMsim3& _memory)
-    : ResponsePort(_name, &_memory), mem(_memory)
+    : ResponsePort(_name), mem(_memory)
 { }
 
 AddrRangeList

src/mem/external_master.hh

@@ -75,7 +75,7 @@ class ExternalMaster : public SimObject
       public:
         ExternalPort(const std::string &name_,
             ExternalMaster &owner_) :
-            RequestPort(name_, &owner_), owner(owner_)
+            RequestPort(name_), owner(owner_)
         { }
 
         ~ExternalPort() { }

src/mem/external_slave.hh

@@ -77,7 +77,7 @@ class ExternalSlave : public SimObject
       public:
         ExternalPort(const std::string &name_,
             ExternalSlave &owner_) :
-            ResponsePort(name_, &owner_), owner(owner_)
+            ResponsePort(name_), owner(owner_)
         { }
 
         ~ExternalPort() { }

src/mem/mem_checker_monitor.hh

@@ -95,7 +95,7 @@ class MemCheckerMonitor : public SimObject
       public:
 
         MonitorRequestPort(const std::string& _name, MemCheckerMonitor& _mon)
-            : RequestPort(_name, &_mon), mon(_mon)
+            : RequestPort(_name), mon(_mon)
         { }
 
       protected:
@@ -156,7 +156,7 @@ class MemCheckerMonitor : public SimObject
       public:
 
         MonitorResponsePort(const std::string& _name, MemCheckerMonitor& _mon)
-            : ResponsePort(_name, &_mon), mon(_mon)
+            : ResponsePort(_name), mon(_mon)
         { }
 
       protected:

src/mem/mem_ctrl.cc

@@ -1460,7 +1460,7 @@ MemCtrl::getAddrRanges()
 
 MemCtrl::MemoryPort::
 MemoryPort(const std::string& name, MemCtrl& _ctrl)
-    : QueuedResponsePort(name, &_ctrl, queue), queue(_ctrl, *this, true),
+    : QueuedResponsePort(name, queue), queue(_ctrl, *this, true),
       ctrl(_ctrl)
 { }
 

src/mem/mem_delay.cc

@@ -81,8 +81,7 @@ MemDelay::trySatisfyFunctional(PacketPtr pkt)
 }
 
 MemDelay::RequestPort::RequestPort(const std::string &_name, MemDelay &_parent)
-    : QueuedRequestPort(_name, &_parent,
+    : QueuedRequestPort(_name, _parent.reqQueue, _parent.snoopRespQueue),
-                       _parent.reqQueue, _parent.snoopRespQueue),
       parent(_parent)
 {
 }
@@ -129,7 +128,7 @@ MemDelay::RequestPort::recvTimingSnoopReq(PacketPtr pkt)
 
 MemDelay::ResponsePort::
 ResponsePort(const std::string &_name, MemDelay &_parent)
-    : QueuedResponsePort(_name, &_parent, _parent.respQueue),
+    : QueuedResponsePort(_name, _parent.respQueue),
       parent(_parent)
 {
 }

src/mem/noncoherent_xbar.hh

@@ -96,7 +96,7 @@ class NoncoherentXBar : public BaseXBar
 
         NoncoherentXBarResponsePort(const std::string &_name,
                                 NoncoherentXBar &_xbar, PortID _id)
-            : QueuedResponsePort(_name, &_xbar, queue, _id), xbar(_xbar),
+            : QueuedResponsePort(_name, queue, _id), xbar(_xbar),
               queue(_xbar, *this)
         { }
 
@@ -156,7 +156,7 @@ class NoncoherentXBar : public BaseXBar
 
         NoncoherentXBarRequestPort(const std::string &_name,
                                  NoncoherentXBar &_xbar, PortID _id)
-            : RequestPort(_name, &_xbar, _id), xbar(_xbar)
+            : RequestPort(_name, _id), xbar(_xbar)
         { }
 
       protected:

src/mem/port.cc

@@ -64,7 +64,7 @@ class DefaultRequestPort : public RequestPort
     }
 
   public:
-    DefaultRequestPort() : RequestPort("default_request_port", nullptr) {}
+    DefaultRequestPort() : RequestPort("default_request_port") {}
 
     // Atomic protocol.
     Tick recvAtomicSnoop(PacketPtr) override { blowUp(); }
@@ -89,7 +89,7 @@ class DefaultResponsePort : public ResponsePort
     }
 
   public:
-    DefaultResponsePort() : ResponsePort("default_response_port", nullptr) {}
+    DefaultResponsePort() : ResponsePort("default_response_port") {}
 
     // Atomic protocol.
     Tick recvAtomic(PacketPtr) override { blowUp(); }

src/mem/port.hh

@@ -480,9 +480,7 @@ class ResponsePort : public Port, public AtomicResponseProtocol,
 class [[deprecated]] SlavePort : public ResponsePort
 {
   public:
-    SlavePort(const std::string& name, SimObject* _owner,
+    using ResponsePort::ResponsePort;
-              PortID id=InvalidPortID) : ResponsePort(name, _owner, id)
-              {}
 };
 
 inline Tick

src/mem/port_terminator.cc

@@ -34,11 +34,11 @@ PortTerminator::PortTerminator(const PortTerminatorParams &params):
     SimObject(params)
 {
     for (int i = 0; i < params.port_req_ports_connection_count; ++i) {
-        reqPorts.emplace_back(name() + ".req_ports" + std::to_string(i), this);
+        reqPorts.emplace_back(name() + ".req_ports" + std::to_string(i));
     }
     for (int j = 0; j < params.port_resp_ports_connection_count; ++j) {
         reqPorts.emplace_back(name() + ".resp_ports" +
-                                std::to_string(j), this);
+                                std::to_string(j));
     }
 }
 

src/mem/port_terminator.hh

@@ -66,8 +66,8 @@ class PortTerminator : public SimObject
     class ReqPort : public RequestPort
     {
       public:
-        ReqPort(const std::string &name, PortTerminator *owner):
+        ReqPort(const std::string &name):
-            RequestPort(name, owner)
+            RequestPort(name)
         {}
       protected:
         bool recvTimingResp(PacketPtr pkt) override
@@ -97,8 +97,8 @@ class PortTerminator : public SimObject
     class RespPort : public ResponsePort
     {
       public:
-        RespPort(const std::string &name, PortTerminator *owner):
+        RespPort(const std::string &name):
-            ResponsePort(name, owner)
+            ResponsePort(name)
         {}
     };
 

src/mem/port_wrapper.cc

@@ -30,9 +30,8 @@
 namespace gem5
 {
 
-RequestPortWrapper::RequestPortWrapper(const std::string& name,
+RequestPortWrapper::RequestPortWrapper(const std::string& name, PortID id)
-                                       SimObject* _owner, PortID id)
+    : RequestPort(name, id)
-    : RequestPort(name, _owner, id)
 {
 }
 
@@ -74,9 +73,8 @@ RequestPortWrapper::setTimingCallbacks(RecvTimingRespCallback resp_cb,
     recvReqRetryCb = std::move(retry_cb);
 }
 
-ResponsePortWrapper::ResponsePortWrapper(const std::string& name,
+ResponsePortWrapper::ResponsePortWrapper(const std::string& name, PortID id)
-                                         SimObject* _owner, PortID id)
+    : ResponsePort(name, id)
-    : ResponsePort(name, _owner, id)
 {
 }
 

src/mem/port_wrapper.hh

@@ -80,8 +80,7 @@ class RequestPortWrapper : public RequestPort
     using RecvTimingRespCallback = std::function<bool(PacketPtr)>;
     using RecvReqRetryCallback = std::function<void()>;
 
-    RequestPortWrapper(const std::string& name, SimObject* _owner,
+    RequestPortWrapper(const std::string& name, PortID id = InvalidPortID);
-                       PortID id = InvalidPortID);
 
     void recvRangeChange() override;
 
@@ -120,8 +119,7 @@ class ResponsePortWrapper : public ResponsePort
 
     using RecvRespRetryCallback = std::function<void()>;
 
-    ResponsePortWrapper(const std::string& name, SimObject* _owner,
+    ResponsePortWrapper(const std::string& name, PortID id = InvalidPortID);
-                        PortID id = InvalidPortID);
 
     AddrRangeList getAddrRanges() const override;
 

src/mem/qos/mem_sink.cc

@@ -352,7 +352,7 @@ MemSinkCtrl::MemSinkCtrlStats::MemSinkCtrlStats(statistics::Group *parent)
 
 MemSinkCtrl::MemoryPort::MemoryPort(const std::string& n,
                                     MemSinkCtrl& m)
-  : QueuedResponsePort(n, &m, queue, true),
+  : QueuedResponsePort(n, queue, true),
    mem(m), queue(mem, *this, true)
 {}
 

src/mem/qport.hh

@@ -77,9 +77,10 @@ class QueuedResponsePort : public ResponsePort
      * behaviuor in a subclass, and provide the latter to the
      * QueuePort constructor.
      */
-    QueuedResponsePort(const std::string& name, SimObject* owner,
+    QueuedResponsePort(const std::string& name,
-                    RespPacketQueue &resp_queue, PortID id = InvalidPortID) :
+                       RespPacketQueue &resp_queue,
-        ResponsePort(name, owner, id), respQueue(resp_queue)
+                       PortID id = InvalidPortID) :
+        ResponsePort(name, id), respQueue(resp_queue)
     { }
 
     virtual ~QueuedResponsePort() { }
@@ -124,17 +125,17 @@ class QueuedRequestPort : public RequestPort
   public:
 
     /**
-     * Create a QueuedPort with a given name, owner, and a supplied
+     * Create a QueuedPort with a given name, and a supplied
      * implementation of two packet queues. The external definition of
      * the queues enables e.g. the cache to implement a specific queue
      * behaviuor in a subclass, and provide the latter to the
      * QueuePort constructor.
      */
-    QueuedRequestPort(const std::string& name, SimObject* owner,
+    QueuedRequestPort(const std::string& name,
                      ReqPacketQueue &req_queue,
                      SnoopRespPacketQueue &snoop_resp_queue,
                      PortID id = InvalidPortID) :
-        RequestPort(name, owner, id), reqQueue(req_queue),
+        RequestPort(name, id), reqQueue(req_queue),
         snoopRespQueue(snoop_resp_queue)
     { }
 

src/mem/ruby/slicc_interface/AbstractController.cc

@@ -455,7 +455,7 @@ AbstractController::MemoryPort::recvReqRetry()
 AbstractController::MemoryPort::MemoryPort(const std::string &_name,
                                            AbstractController *_controller,
                                            PortID id)
-    : RequestPort(_name, _controller, id), controller(_controller)
+    : RequestPort(_name, id), controller(_controller)
 {
 }
 

src/mem/ruby/system/RubyPort.cc

@@ -62,10 +62,10 @@ RubyPort::RubyPort(const Params &p)
     : ClockedObject(p), m_ruby_system(p.ruby_system), m_version(p.version),
       m_controller(NULL), m_mandatory_q_ptr(NULL),
       m_usingRubyTester(p.using_ruby_tester), system(p.system),
-      pioRequestPort(csprintf("%s.pio-request-port", name()), this),
+      pioRequestPort(csprintf("%s.pio-request-port", name()), *this),
-      pioResponsePort(csprintf("%s.pio-response-port", name()), this),
+      pioResponsePort(csprintf("%s.pio-response-port", name()), *this),
-      memRequestPort(csprintf("%s.mem-request-port", name()), this),
+      memRequestPort(csprintf("%s.mem-request-port", name()), *this),
-      memResponsePort(csprintf("%s-mem-response-port", name()), this,
+      memResponsePort(csprintf("%s-mem-response-port", name()), *this,
                    p.ruby_system->getAccessBackingStore(), -1,
                    p.no_retry_on_stall),
       gotAddrRanges(p.port_interrupt_out_port_connection_count),
@@ -76,7 +76,7 @@ RubyPort::RubyPort(const Params &p)
     // create the response ports based on the number of connected ports
     for (size_t i = 0; i < p.port_in_ports_connection_count; ++i) {
         response_ports.push_back(new MemResponsePort(csprintf
-            ("%s.response_ports%d", name(), i), this,
+            ("%s.response_ports%d", name(), i), *this,
             p.ruby_system->getAccessBackingStore(),
             i, p.no_retry_on_stall));
     }
@@ -84,7 +84,7 @@ RubyPort::RubyPort(const Params &p)
     // create the request ports based on the number of connected ports
     for (size_t i = 0; i < p.port_interrupt_out_port_connection_count; ++i) {
         request_ports.push_back(new PioRequestPort(csprintf(
-                    "%s.request_ports%d", name(), i), this));
+                    "%s.request_ports%d", name(), i), *this));
     }
 }
 
@@ -134,35 +134,41 @@ RubyPort::getPort(const std::string &if_name, PortID idx)
 }
 
 RubyPort::PioRequestPort::PioRequestPort(const std::string &_name,
-                           RubyPort *_port)
+                                         RubyPort& _port) :
-    : QueuedRequestPort(_name, _port, reqQueue, snoopRespQueue),
+    QueuedRequestPort(_name, reqQueue, snoopRespQueue),
-      reqQueue(*_port, *this), snoopRespQueue(*_port, *this)
+    owner{_port},
+    reqQueue(_port, *this),
+    snoopRespQueue(_port, *this)
 {
     DPRINTF(RubyPort, "Created request pioport on sequencer %s\n", _name);
 }
 
 RubyPort::PioResponsePort::PioResponsePort(const std::string &_name,
-                           RubyPort *_port)
+                                           RubyPort& _port)
-    : QueuedResponsePort(_name, _port, queue), queue(*_port, *this)
+    : QueuedResponsePort(_name, queue), owner{_port}, queue(_port, *this)
 {
     DPRINTF(RubyPort, "Created response pioport on sequencer %s\n", _name);
 }
 
 RubyPort::MemRequestPort::MemRequestPort(const std::string &_name,
-                           RubyPort *_port)
+                                         RubyPort& _port):
-    : QueuedRequestPort(_name, _port, reqQueue, snoopRespQueue),
+    QueuedRequestPort(_name, reqQueue, snoopRespQueue),
-      reqQueue(*_port, *this), snoopRespQueue(*_port, *this)
+    owner{_port},
+    reqQueue(_port, *this),
+    snoopRespQueue(_port, *this)
 {
     DPRINTF(RubyPort, "Created request memport on ruby sequencer %s\n", _name);
 }
 
 RubyPort::
-MemResponsePort::MemResponsePort(const std::string &_name, RubyPort *_port,
+MemResponsePort::MemResponsePort(const std::string &_name, RubyPort& _port,
-                                     bool _access_backing_store, PortID id,
+                                 bool _access_backing_store, PortID id,
-                                     bool _no_retry_on_stall)
+                                 bool _no_retry_on_stall):
-    : QueuedResponsePort(_name, _port, queue, id), queue(*_port, *this),
+    QueuedResponsePort(_name, queue, id),
-      access_backing_store(_access_backing_store),
+    owner{_port},
-      no_retry_on_stall(_no_retry_on_stall)
+    queue(_port, *this),
+    access_backing_store(_access_backing_store),
+    no_retry_on_stall(_no_retry_on_stall)
 {
     DPRINTF(RubyPort, "Created response memport on ruby sequencer %s\n",
             _name);
@@ -171,12 +177,11 @@ MemResponsePort::MemResponsePort(const std::string &_name, RubyPort *_port,
 bool
 RubyPort::PioRequestPort::recvTimingResp(PacketPtr pkt)
 {
-    RubyPort *rp = static_cast<RubyPort *>(&owner);
     DPRINTF(RubyPort, "Response for address: 0x%#x\n", pkt->getAddr());
 
     // send next cycle
-    rp->pioResponsePort.schedTimingResp(
+    owner.pioResponsePort.schedTimingResp(
-            pkt, curTick() + rp->m_ruby_system->clockPeriod());
+            pkt, curTick() + owner.m_ruby_system->clockPeriod());
     return true;
 }
 
@@ -199,8 +204,7 @@ bool RubyPort::MemRequestPort::recvTimingResp(PacketPtr pkt)
             pkt->getAddr(), port->name());
 
     // attempt to send the response in the next cycle
-    RubyPort *rp = static_cast<RubyPort *>(&owner);
+    port->schedTimingResp(pkt, curTick() + owner.m_ruby_system->clockPeriod());
-    port->schedTimingResp(pkt, curTick() + rp->m_ruby_system->clockPeriod());
 
     return true;
 }
@@ -208,16 +212,15 @@ bool RubyPort::MemRequestPort::recvTimingResp(PacketPtr pkt)
 bool
 RubyPort::PioResponsePort::recvTimingReq(PacketPtr pkt)
 {
-    RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
 
-    for (size_t i = 0; i < ruby_port->request_ports.size(); ++i) {
+    for (size_t i = 0; i < owner.request_ports.size(); ++i) {
-        AddrRangeList l = ruby_port->request_ports[i]->getAddrRanges();
+        AddrRangeList l = owner.request_ports[i]->getAddrRanges();
         for (auto it = l.begin(); it != l.end(); ++it) {
             if (it->contains(pkt->getAddr())) {
                 // generally it is not safe to assume success here as
                 // the port could be blocked
                 [[maybe_unused]] bool success =
-                    ruby_port->request_ports[i]->sendTimingReq(pkt);
+                    owner.request_ports[i]->sendTimingReq(pkt);
                 assert(success);
                 return true;
             }
@@ -229,17 +232,16 @@ RubyPort::PioResponsePort::recvTimingReq(PacketPtr pkt)
 Tick
 RubyPort::PioResponsePort::recvAtomic(PacketPtr pkt)
 {
-    RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
     // Only atomic_noncaching mode supported!
-    if (!ruby_port->system->bypassCaches()) {
+    if (!owner.system->bypassCaches()) {
         panic("Ruby supports atomic accesses only in noncaching mode\n");
     }
 
-    for (size_t i = 0; i < ruby_port->request_ports.size(); ++i) {
+    for (size_t i = 0; i < owner.request_ports.size(); ++i) {
-        AddrRangeList l = ruby_port->request_ports[i]->getAddrRanges();
+        AddrRangeList l = owner.request_ports[i]->getAddrRanges();
         for (auto it = l.begin(); it != l.end(); ++it) {
             if (it->contains(pkt->getAddr())) {
-                return ruby_port->request_ports[i]->sendAtomic(pkt);
+                return owner.request_ports[i]->sendAtomic(pkt);
             }
         }
     }
@@ -251,7 +253,6 @@ RubyPort::MemResponsePort::recvTimingReq(PacketPtr pkt)
 {
     DPRINTF(RubyPort, "Timing request for address %#x on port %d\n",
             pkt->getAddr(), id);
-    RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
 
     if (pkt->cacheResponding())
         panic("RubyPort should never see request with the "
@@ -269,7 +270,7 @@ RubyPort::MemResponsePort::recvTimingReq(PacketPtr pkt)
     // pio port.
     if (pkt->cmd != MemCmd::MemSyncReq) {
         if (!pkt->req->isMemMgmt() && !isPhysMemAddress(pkt)) {
-            assert(ruby_port->memRequestPort.isConnected());
+            assert(owner.memRequestPort.isConnected());
             DPRINTF(RubyPort, "Request address %#x assumed to be a "
                     "pio address\n", pkt->getAddr());
 
@@ -278,8 +279,8 @@ RubyPort::MemResponsePort::recvTimingReq(PacketPtr pkt)
             pkt->pushSenderState(new SenderState(this));
 
             // send next cycle
-            RubySystem *rs = ruby_port->m_ruby_system;
+            RubySystem *rs = owner.m_ruby_system;
-            ruby_port->memRequestPort.schedTimingReq(pkt,
+            owner.memRequestPort.schedTimingReq(pkt,
                 curTick() + rs->clockPeriod());
             return true;
         }
@@ -290,7 +291,7 @@ RubyPort::MemResponsePort::recvTimingReq(PacketPtr pkt)
     pkt->pushSenderState(new SenderState(this));
 
     // Submit the ruby request
-    RequestStatus requestStatus = ruby_port->makeRequest(pkt);
+    RequestStatus requestStatus = owner.makeRequest(pkt);
 
     // If the request successfully issued then we should return true.
     // Otherwise, we need to tell the port to retry at a later point
@@ -320,9 +321,8 @@ RubyPort::MemResponsePort::recvTimingReq(PacketPtr pkt)
 Tick
 RubyPort::MemResponsePort::recvAtomic(PacketPtr pkt)
 {
-    RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
     // Only atomic_noncaching mode supported!
-    if (!ruby_port->system->bypassCaches()) {
+    if (!owner.system->bypassCaches()) {
         panic("Ruby supports atomic accesses only in noncaching mode\n");
     }
 
@@ -330,7 +330,7 @@ RubyPort::MemResponsePort::recvAtomic(PacketPtr pkt)
     // pio port.
     if (pkt->cmd != MemCmd::MemSyncReq) {
         if (!isPhysMemAddress(pkt)) {
-            assert(ruby_port->memRequestPort.isConnected());
+            assert(owner.memRequestPort.isConnected());
             DPRINTF(RubyPort, "Request address %#x assumed to be a "
                     "pio address\n", pkt->getAddr());
 
@@ -339,8 +339,8 @@ RubyPort::MemResponsePort::recvAtomic(PacketPtr pkt)
             pkt->pushSenderState(new SenderState(this));
 
             // send next cycle
-            Tick req_ticks = ruby_port->memRequestPort.sendAtomic(pkt);
+            Tick req_ticks = owner.memRequestPort.sendAtomic(pkt);
-            return ruby_port->ticksToCycles(req_ticks);
+            return owner.ticksToCycles(req_ticks);
         }
 
         assert(getOffset(pkt->getAddr()) + pkt->getSize() <=
@@ -348,7 +348,7 @@ RubyPort::MemResponsePort::recvAtomic(PacketPtr pkt)
     }
 
     // Find the machine type of memory controller interface
-    RubySystem *rs = ruby_port->m_ruby_system;
+    RubySystem *rs = owner.m_ruby_system;
     static int mem_interface_type = -1;
     if (mem_interface_type == -1) {
         if (rs->m_abstract_controls[MachineType_Directory].size() != 0) {
@@ -363,7 +363,7 @@ RubyPort::MemResponsePort::recvAtomic(PacketPtr pkt)
     }
 
     // Find the controller for the target address
-    MachineID id = ruby_port->m_controller->mapAddressToMachine(
+    MachineID id = owner.m_controller->mapAddressToMachine(
                     pkt->getAddr(), (MachineType)mem_interface_type);
     AbstractController *mem_interface =
         rs->m_abstract_controls[mem_interface_type][id.getNum()];
@@ -376,15 +376,14 @@ RubyPort::MemResponsePort::recvAtomic(PacketPtr pkt)
 void
 RubyPort::MemResponsePort::addToRetryList()
 {
-    RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
 
     //
     // Unless the request port do not want retries (e.g., the Ruby tester),
     // record the stalled M5 port for later retry when the sequencer
     // becomes free.
     //
-    if (!no_retry_on_stall && !ruby_port->onRetryList(this)) {
+    if (!no_retry_on_stall && !owner.onRetryList(this)) {
-        ruby_port->addToRetryList(this);
+        owner.addToRetryList(this);
     }
 }
 
@@ -393,15 +392,14 @@ RubyPort::MemResponsePort::recvFunctional(PacketPtr pkt)
 {
     DPRINTF(RubyPort, "Functional access for address: %#x\n", pkt->getAddr());
 
-    [[maybe_unused]] RubyPort *rp = static_cast<RubyPort *>(&owner);
+    RubySystem *rs = owner.m_ruby_system;
-    RubySystem *rs = rp->m_ruby_system;
 
     // Check for pio requests and directly send them to the dedicated
     // pio port.
     if (!isPhysMemAddress(pkt)) {
         DPRINTF(RubyPort, "Pio Request for address: 0x%#x\n", pkt->getAddr());
-        assert(rp->pioRequestPort.isConnected());
+        assert(owner.pioRequestPort.isConnected());
-        rp->pioRequestPort.sendFunctional(pkt);
+        owner.pioRequestPort.sendFunctional(pkt);
         return;
     }
 
@@ -626,15 +624,14 @@ RubyPort::MemResponsePort::hitCallback(PacketPtr pkt)
 
     DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse);
 
-    RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
+    RubySystem *rs = owner.m_ruby_system;
-    RubySystem *rs = ruby_port->m_ruby_system;
     if (accessPhysMem) {
         // We must check device memory first in case it overlaps with the
         // system memory range.
-        if (ruby_port->system->isDeviceMemAddr(pkt)) {
+        if (owner.system->isDeviceMemAddr(pkt)) {
-            auto dmem = ruby_port->system->getDeviceMemory(pkt);
+            auto dmem = owner.system->getDeviceMemory(pkt);
             dmem->access(pkt);
-        } else if (ruby_port->system->isMemAddr(pkt->getAddr())) {
+        } else if (owner.system->isMemAddr(pkt->getAddr())) {
             rs->getPhysMem()->access(pkt);
         } else {
             panic("Packet is in neither device nor system memory!");
@@ -662,11 +659,10 @@ RubyPort::PioResponsePort::getAddrRanges() const
 {
     // at the moment the assumption is that the request port does not care
     AddrRangeList ranges;
-    RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
 
-    for (size_t i = 0; i < ruby_port->request_ports.size(); ++i) {
+    for (size_t i = 0; i < owner.request_ports.size(); ++i) {
         ranges.splice(ranges.begin(),
-                ruby_port->request_ports[i]->getAddrRanges());
+                owner.request_ports[i]->getAddrRanges());
     }
     for ([[maybe_unused]] const auto &r : ranges)
         DPRINTF(RubyPort, "%s\n", r.to_string());
@@ -676,8 +672,7 @@ RubyPort::PioResponsePort::getAddrRanges() const
 bool
 RubyPort::MemResponsePort::isShadowRomAddress(Addr addr) const
 {
-    RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
+    AddrRangeList ranges = owner.system->getShadowRomRanges();
-    AddrRangeList ranges = ruby_port->system->getShadowRomRanges();
 
     for (auto it = ranges.begin(); it != ranges.end(); ++it) {
         if (it->contains(addr)) {
@@ -691,10 +686,9 @@ RubyPort::MemResponsePort::isShadowRomAddress(Addr addr) const
 bool
 RubyPort::MemResponsePort::isPhysMemAddress(PacketPtr pkt) const
 {
-    RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
     Addr addr = pkt->getAddr();
-    return (ruby_port->system->isMemAddr(addr) && !isShadowRomAddress(addr))
+    return (owner.system->isMemAddr(addr) && !isShadowRomAddress(addr))
-           || ruby_port->system->isDeviceMemAddr(pkt);
+           || owner.system->isDeviceMemAddr(pkt);
 }
 
 void

src/mem/ruby/system/RubyPort.hh

@@ -67,11 +67,12 @@ class RubyPort : public ClockedObject
     class MemRequestPort : public QueuedRequestPort
     {
       private:
+        RubyPort& owner;
         ReqPacketQueue reqQueue;
         SnoopRespPacketQueue snoopRespQueue;
 
       public:
-        MemRequestPort(const std::string &_name, RubyPort *_port);
+        MemRequestPort(const std::string &_name, RubyPort& _port);
 
       protected:
         bool recvTimingResp(PacketPtr pkt);
@@ -81,14 +82,16 @@ class RubyPort : public ClockedObject
     class MemResponsePort : public QueuedResponsePort
     {
       private:
+        RubyPort& owner;
         RespPacketQueue queue;
         bool access_backing_store;
         bool no_retry_on_stall;
 
       public:
-        MemResponsePort(const std::string &_name, RubyPort *_port,
+        MemResponsePort(const std::string &_name,
-                     bool _access_backing_store,
+                        RubyPort& _port,
-                     PortID id, bool _no_retry_on_stall);
+                        bool _access_backing_store,
+                        PortID id, bool _no_retry_on_stall);
         void hitCallback(PacketPtr pkt);
         void evictionCallback(Addr address);
 
@@ -112,11 +115,12 @@ class RubyPort : public ClockedObject
     class PioRequestPort : public QueuedRequestPort
     {
       private:
+        RubyPort& owner;
         ReqPacketQueue reqQueue;
         SnoopRespPacketQueue snoopRespQueue;
 
       public:
-        PioRequestPort(const std::string &_name, RubyPort *_port);
+        PioRequestPort(const std::string &_name, RubyPort& _port);
 
       protected:
         bool recvTimingResp(PacketPtr pkt);
@@ -126,10 +130,11 @@ class RubyPort : public ClockedObject
     class PioResponsePort : public QueuedResponsePort
     {
       private:
+        RubyPort& owner;
         RespPacketQueue queue;
 
       public:
-        PioResponsePort(const std::string &_name, RubyPort *_port);
+        PioResponsePort(const std::string &_name, RubyPort& _port);
 
       protected:
         bool recvTimingReq(PacketPtr pkt);

src/mem/serial_link.cc

@@ -61,7 +61,7 @@ SerialLinkResponsePort(const std::string& _name,
                                          Cycles _delay, int _resp_limit,
                                          const std::vector<AddrRange>&
                                          _ranges)
-    : ResponsePort(_name, &_serial_link), serial_link(_serial_link),
+    : ResponsePort(_name), serial_link(_serial_link),
       mem_side_port(_mem_side_port), delay(_delay),
       ranges(_ranges.begin(), _ranges.end()),
       outstandingResponses(0), retryReq(false),
@@ -75,7 +75,7 @@ SerialLink::SerialLinkRequestPort::SerialLinkRequestPort(const std::string&
                                            SerialLinkResponsePort&
                                            _cpu_side_port, Cycles _delay,
                                            int _req_limit)
-    : RequestPort(_name, &_serial_link), serial_link(_serial_link),
+    : RequestPort(_name), serial_link(_serial_link),
       cpu_side_port(_cpu_side_port), delay(_delay), reqQueueLimit(_req_limit),
       sendEvent([this]{ trySendTiming(); }, _name)
 {

src/mem/simple_mem.cc

@@ -271,7 +271,7 @@ SimpleMemory::drain()
 
 SimpleMemory::MemoryPort::MemoryPort(const std::string& _name,
                                      SimpleMemory& _memory)
-    : ResponsePort(_name, &_memory), mem(_memory)
+    : ResponsePort(_name), mem(_memory)
 { }
 
 AddrRangeList

src/mem/sys_bridge.cc

@@ -43,9 +43,9 @@ SysBridge::BridgingPort::replaceReqID(PacketPtr pkt)
 }
 
 SysBridge::SysBridge(const SysBridgeParams &p) : SimObject(p),
-    sourcePort(p.name + ".source_port", this, &targetPort,
+    sourcePort(p.name + ".source_port", &targetPort,
             p.target->getRequestorId(this)),
-    targetPort(p.name + ".target_port", this, &sourcePort,
+    targetPort(p.name + ".target_port", &sourcePort,
             p.source->getRequestorId(this))
 {}
 

src/mem/sys_bridge.hh

@@ -130,9 +130,9 @@ class SysBridge : public SimObject
         SysBridgeSourcePort *sourcePort;
 
       public:
-        SysBridgeTargetPort(const std::string &_name, SimObject *owner,
+        SysBridgeTargetPort(const std::string &_name,
                 SysBridgeSourcePort *source_port, RequestorID _id) :
-            RequestPort(_name, owner), BridgingPort(_id),
+            RequestPort(_name), BridgingPort(_id),
             sourcePort(source_port)
         {
             DPRINTF(SysBridge, "Target side requestor ID = %s.\n", _id);
@@ -223,9 +223,9 @@ class SysBridge : public SimObject
         SysBridgeTargetPort *targetPort;
 
       public:
-        SysBridgeSourcePort(const std::string &_name, SimObject *owner,
+        SysBridgeSourcePort(const std::string &_name,
                 SysBridgeTargetPort *target_port, RequestorID _id) :
-            ResponsePort(_name, owner), BridgingPort(_id),
+            ResponsePort(_name), BridgingPort(_id),
             targetPort(target_port)
         {
             DPRINTF(SysBridge, "Source side requestor ID = %s.\n", _id);

src/mem/thread_bridge.cc

@@ -40,7 +40,7 @@ ThreadBridge::ThreadBridge(const ThreadBridgeParams &p)
 
 ThreadBridge::IncomingPort::IncomingPort(const std::string &name,
                                          ThreadBridge &device)
-    : ResponsePort(name, &device), device_(device)
+    : ResponsePort(name), device_(device)
 {
 }
 
@@ -94,7 +94,7 @@ ThreadBridge::IncomingPort::recvMemBackdoorReq(const MemBackdoorReq &req,
 
 ThreadBridge::OutgoingPort::OutgoingPort(const std::string &name,
                                          ThreadBridge &device)
-    : RequestPort(name, &device), device_(device)
+    : RequestPort(name), device_(device)
 {
 }
 

src/mem/token_port.hh

@@ -50,7 +50,7 @@ class TokenRequestPort : public RequestPort
   public:
     TokenRequestPort(const std::string& name, SimObject* owner,
                     PortID id = InvalidPortID) :
-        RequestPort(name, owner, id), tokenManager(nullptr)
+        RequestPort(name, id), tokenManager(nullptr)
     { }
 
     /**
@@ -98,9 +98,9 @@ class TokenResponsePort : public ResponsePort
     void recvRespRetry() override;
 
   public:
-    TokenResponsePort(const std::string& name, ClockedObject *owner,
+    TokenResponsePort(const std::string& name,
                    PortID id = InvalidPortID) :
-        ResponsePort(name, owner, id), tokenRequestPort(nullptr)
+        ResponsePort(name, id), tokenRequestPort(nullptr)
     { }
     ~TokenResponsePort() { }
 

src/mem/tport.cc

@@ -46,7 +46,7 @@ namespace gem5
 
 SimpleTimingPort::SimpleTimingPort(const std::string& _name,
                                    SimObject* _owner) :
-    QueuedResponsePort(_name, _owner, queueImpl), queueImpl(*_owner, *this)
+    QueuedResponsePort(_name, queueImpl), queueImpl(*_owner, *this)
 {
 }
 

src/sim/system.cc

@@ -165,7 +165,7 @@ System::Threads::quiesceTick(ContextID id, Tick when)
 int System::numSystemsRunning = 0;
 
 System::System(const Params &p)
-    : SimObject(p), _systemPort("system_port", this),
+    : SimObject(p), _systemPort("system_port"),
       multiThread(p.multi_thread),
       init_param(p.init_param),
       physProxy(_systemPort, p.cache_line_size),

src/sim/system.hh

@@ -87,8 +87,8 @@ class System : public SimObject, public PCEventScope
         /**
          * Create a system port with a name and an owner.
          */
-        SystemPort(const std::string &_name, SimObject *_owner)
+        SystemPort(const std::string &_name)
-            : RequestPort(_name, _owner)
+            : RequestPort(_name)
         { }
 
         bool

src/sst/outgoing_request_bridge.cc

@@ -52,7 +52,7 @@ OutgoingRequestBridge::~OutgoingRequestBridge()
 OutgoingRequestBridge::
 OutgoingRequestPort::OutgoingRequestPort(const std::string &name_,
                                          OutgoingRequestBridge* owner_) :
-    ResponsePort(name_, owner_)
+    ResponsePort(name_)
 {
     owner = owner_;
 }

src/systemc/tlm_bridge/gem5_to_tlm.hh

@@ -145,7 +145,7 @@ class Gem5ToTlmBridge : public Gem5ToTlmBridgeBase
       public:
         BridgeResponsePort(const std::string &name_,
                         Gem5ToTlmBridge<BITWIDTH> &bridge_) :
-            ResponsePort(name_, nullptr), bridge(bridge_)
+            ResponsePort(name_), bridge(bridge_)
         {}
     };
 

src/systemc/tlm_bridge/tlm_to_gem5.hh

@@ -109,7 +109,7 @@ class TlmToGem5Bridge : public TlmToGem5BridgeBase
       public:
         BridgeRequestPort(const std::string &name_,
                          TlmToGem5Bridge<BITWIDTH> &bridge_) :
-            RequestPort(name_, nullptr), bridge(bridge_)
+            RequestPort(name_), bridge(bridge_)
         {}
     };