derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

mem,arch-arm,mem-ruby,cpu: Remove use of deprecated base port owner

Browse Source 
Change-Id: I29214278c3dd4829c89a6f7c93214b8123912e74
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67452
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
This commit is contained in:
Gabriel Busnot
2023-01-06 11:22:26 +00:00
committed by Gabriel B.
parent d40ed0f826
commit 7f4c92c910
70 changed files with 223 additions and 232 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/cpu/kvm/base.hh
View File

@@ -601,7 +601,7 @@ class BaseKvmCPU : public BaseCPU
public:
KVMCpuPort(const std::string &_name, BaseKvmCPU *_cpu)
: RequestPort(_name, _cpu), cpu(_cpu), activeMMIOReqs(0)
: RequestPort(_name), cpu(_cpu), activeMMIOReqs(0)
{ }
/**
* Interface to send Atomic or Timing IO request. Assumes that the pkt

2
src/cpu/minor/cpu.hh
View File

@@ -110,7 +110,7 @@ class MinorCPU : public BaseCPU
public:
MinorCPUPort(const std::string& name_, MinorCPU &cpu_)
: RequestPort(name_, &cpu_), cpu(cpu_)
: RequestPort(name_), cpu(cpu_)
{ }
};

2
src/cpu/o3/fetch.cc
View File

@@ -76,7 +76,7 @@ namespace o3
{
Fetch::IcachePort::IcachePort(Fetch *_fetch, CPU *_cpu) :
RequestPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch)
RequestPort(_cpu->name() + ".icache_port"), fetch(_fetch)
{}

2
src/cpu/o3/lsq.cc
View File

@@ -65,7 +65,7 @@ namespace o3
{
LSQ::DcachePort::DcachePort(LSQ *_lsq, CPU *_cpu) :
RequestPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq), cpu(_cpu)
RequestPort(_cpu->name() + ".dcache_port"), lsq(_lsq), cpu(_cpu)
{}
LSQ::LSQ(CPU *cpu_ptr, IEW *iew_ptr, const BaseO3CPUParams &params)

5
src/cpu/simple/atomic.cc
View File

@@ -78,7 +78,7 @@ AtomicSimpleCPU::AtomicSimpleCPU(const BaseAtomicSimpleCPUParams &p)
width(p.width), locked(false),
simulate_data_stalls(p.simulate_data_stalls),
simulate_inst_stalls(p.simulate_inst_stalls),
icachePort(name() + ".icache_port", this),
icachePort(name() + ".icache_port"),
dcachePort(name() + ".dcache_port", this),
dcache_access(false), dcache_latency(0),
ppCommit(nullptr)
@@ -281,8 +281,6 @@ AtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(PacketPtr pkt)
__func__, pkt->getAddr(), pkt->cmdString());
// X86 ISA: Snooping an invalidation for monitor/mwait
AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner);
for (ThreadID tid = 0; tid < cpu->numThreads; tid++) {
if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) {
cpu->wakeup(tid);
@@ -312,7 +310,6 @@ AtomicSimpleCPU::AtomicCPUDPort::recvFunctionalSnoop(PacketPtr pkt)
__func__, pkt->getAddr(), pkt->cmdString());
// X86 ISA: Snooping an invalidation for monitor/mwait
AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner);
for (ThreadID tid = 0; tid < cpu->numThreads; tid++) {
if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) {
cpu->wakeup(tid);

6
src/cpu/simple/atomic.hh
View File

@@ -117,8 +117,8 @@ class AtomicSimpleCPU : public BaseSimpleCPU
public:
AtomicCPUPort(const std::string &_name, BaseSimpleCPU* _cpu)
: RequestPort(_name, _cpu)
AtomicCPUPort(const std::string &_name)
: RequestPort(_name)
{ }
protected:
@@ -142,7 +142,7 @@ class AtomicSimpleCPU : public BaseSimpleCPU
public:
AtomicCPUDPort(const std::string &_name, BaseSimpleCPU *_cpu)
: AtomicCPUPort(_name, _cpu), cpu(_cpu)
: AtomicCPUPort(_name), cpu(_cpu)
{
cacheBlockMask = ~(cpu->cacheLineSize() - 1);
}

2
src/cpu/simple/timing.hh
View File

@@ -164,7 +164,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
public:
TimingCPUPort(const std::string& _name, TimingSimpleCPU* _cpu)
: RequestPort(_name, _cpu), cpu(_cpu),
: RequestPort(_name), cpu(_cpu),
retryRespEvent([this]{ sendRetryResp(); }, name())
{ }

2
src/cpu/testers/directedtest/RubyDirectedTester.hh
View File

@@ -58,7 +58,7 @@ class RubyDirectedTester : public ClockedObject
public:
CpuPort(const std::string &_name, RubyDirectedTester *_tester,
PortID _id)
: RequestPort(_name, _tester, _id), tester(_tester)
: RequestPort(_name, _id), tester(_tester)
{}
protected:

2
src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.hh
View File

@@ -84,7 +84,7 @@ class GarnetSyntheticTraffic : public ClockedObject
public:
CpuPort(const std::string &_name, GarnetSyntheticTraffic *_tester)
: RequestPort(_name, _tester), tester(_tester)
: RequestPort(_name), tester(_tester)
{ }
protected:

2
src/cpu/testers/gpu_ruby_test/protocol_tester.hh
View File

@@ -74,7 +74,7 @@ class ProtocolTester : public ClockedObject
public:
SeqPort(const std::string &_name, ProtocolTester *_tester, PortID _id,
PortID _index)
: RequestPort(_name, _tester, _id)
: RequestPort(_name, _id)
{}
protected:

2
src/cpu/testers/memtest/memtest.hh
View File

@@ -100,7 +100,7 @@ class MemTest : public ClockedObject
public:
CpuPort(const std::string &_name, MemTest &_memtest)
: RequestPort(_name, &_memtest), memtest(_memtest)
: RequestPort(_name), memtest(_memtest)
{ }
protected:

2
src/cpu/testers/rubytest/RubyTester.hh
View File

@@ -76,7 +76,7 @@ class RubyTester : public ClockedObject
CpuPort(const std::string &_name, RubyTester *_tester, PortID _id,
PortID _index)
: RequestPort(_name, _tester, _id), tester(_tester),
: RequestPort(_name, _id), tester(_tester),
globalIdx(_index)
{}

2
src/cpu/testers/traffic_gen/base.hh
View File

@@ -132,7 +132,7 @@ class BaseTrafficGen : public ClockedObject
public:
TrafficGenPort(const std::string& name, BaseTrafficGen& traffic_gen)
: RequestPort(name, &traffic_gen), trafficGen(traffic_gen)
: RequestPort(name), trafficGen(traffic_gen)
{ }
protected:

2
src/cpu/testers/traffic_gen/gups_gen.hh
View File

@@ -87,7 +87,7 @@ class GUPSGen : public ClockedObject
public:
GenPort(const std::string& name, GUPSGen *owner) :
RequestPort(name, owner), owner(owner), _blocked(false),
RequestPort(name), owner(owner), _blocked(false),
blockedPacket(nullptr)
{}

4
src/cpu/trace/trace_cpu.hh
View File

@@ -218,7 +218,7 @@ class TraceCPU : public BaseCPU
public:
/** Default constructor. */
IcachePort(TraceCPU* _cpu) :
RequestPort(_cpu->name() + ".icache_port", _cpu), owner(_cpu)
RequestPort(_cpu->name() + ".icache_port"), owner(_cpu)
{}
public:
@@ -258,7 +258,7 @@ class TraceCPU : public BaseCPU
public:
/** Default constructor. */
DcachePort(TraceCPU* _cpu) :
RequestPort(_cpu->name() + ".dcache_port", _cpu), owner(_cpu)
RequestPort(_cpu->name() + ".dcache_port"), owner(_cpu)
{}
public: