misc: Fix coding style for enum's opening braces

The systemc dir was not included in this fix.

First it was identified that there were only occurrences
at 0, 1, and 2 levels of indentation (and 2 of 2 spaces,
1 of 3 spaces and 2 of 12 spaces), using:

    grep -nrE --exclude-dir=systemc \
        "^ *enum [A-Za-z].* {$" src/

Then the following commands were run to replace:

    <indent level>enum X ... {

by:

    <indent level>enum X ...
    <indent level>{

Level 0:
    grep -nrl --exclude-dir=systemc \
        "^enum [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^enum ([A-Za-z].*) \{$/enum \1\n\{/g'

Level 1:
    grep -nrl --exclude-dir=systemc \
        "^    enum [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^    enum ([A-Za-z].*) \{$/    enum \1\n    \{/g'

and so on.

Change-Id: Ib186cf379049098ceaec20dfe4d1edcedd5f940d
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43326
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/dev/arm/energy_ctrl.hh

@@ -97,7 +97,8 @@ class EnergyCtrl : public BasicPioDevice
      *       while (!read(PERF_LEVEL_ACK));
      */
 
-    enum Registers {
+    enum Registers
+    {
         DVFS_HANDLER_STATUS = 0,
         DVFS_NUM_DOMAINS,
         DVFS_DOMAINID_AT_INDEX,

src/dev/arm/flash_device.hh

@@ -68,7 +68,8 @@ class FlashDevice : public AbstractNVM
 
   private:
     /** Defines the possible actions to the flash*/
-    enum Actions {
+    enum Actions
+    {
         ActionRead,
         ActionWrite,
         ActionErase,

src/dev/arm/fvp_base_pwr_ctrl.hh

@@ -106,7 +106,8 @@ class FVPBasePwrCtrl : public BasicPioDevice
         Bitfield<0> pwk;
     EndBitUnion(PwrStatus)
 
-    enum Offset : Addr {
+    enum Offset : Addr
+    {
         PPOFFR = 0x00,
         PPONR  = 0x04,
         PCOFFR = 0x08,

src/dev/arm/hdlcd.hh

@@ -115,7 +115,8 @@ class HDLcd: public AmbaDmaDevice
 
   protected: // Register handling
     /** ARM HDLcd register offsets */
-    enum RegisterOffset {
+    enum RegisterOffset
+    {
         Version          = 0x0000,
         Int_RawStat      = 0x0010,
         Int_Clear        = 0x0014,

src/dev/arm/pl111.hh

@@ -97,7 +97,8 @@ class Pl111: public AmbaDmaDevice
 
     static const int buffer_size = LcdMaxWidth * LcdMaxHeight * sizeof(uint32_t);
 
-    enum LcdMode {
+    enum LcdMode
+    {
         bpp1 = 0,
         bpp2,
         bpp4,

src/dev/arm/rv_ctrl.hh

@@ -51,7 +51,8 @@
 class RealViewCtrl : public BasicPioDevice
 {
   public:
-    enum DeviceFunc {
+    enum DeviceFunc
+    {
         FUNC_OSC      = 1,
         FUNC_VOLT     = 2,
         FUNC_AMP      = 3,

src/dev/arm/smmu_v3_caches.hh

@@ -94,7 +94,8 @@ class SMMUv3BaseCache
 class SMMUTLB : public SMMUv3BaseCache
 {
   public:
-    enum AllocPolicy {
+    enum AllocPolicy
+    {
         ALLOC_ANY_WAY,
         ALLOC_ANY_BUT_LAST_WAY,
         ALLOC_LAST_WAY,

src/dev/arm/smmu_v3_defs.hh

@@ -318,7 +318,8 @@ enum {
     CR0_VMW_MASK = 0x1C0,
 };
 
-enum SMMUCommandType {
+enum SMMUCommandType
+{
     CMD_PRF_CONFIG     = 0x01,
     CMD_PRF_ADDR       = 0x02,
     CMD_CFGI_STE       = 0x03,
@@ -373,11 +374,13 @@ struct SMMUCommand
     }
 };
 
-enum SMMUEventTypes {
+enum SMMUEventTypes
+{
     EVT_FAULT = 0x0001,
 };
 
-enum SMMUEventFlags {
+enum SMMUEventFlags
+{
     EVF_WRITE = 0x0001,
 };
 

src/dev/arm/smmu_v3_proc.hh

@@ -52,7 +52,8 @@ class SMMUv3DeviceInterface;
  * The meaning of these becomes apparent when you
  * look at runProcessAtomic()/runProcessTiming().
  */
-enum SMMUActionType {
+enum SMMUActionType
+{
     ACTION_INITIAL_NOP,
     ACTION_SEND_REQ,
     ACTION_SEND_REQ_FINAL,

src/dev/arm/ufs_device.hh

@@ -776,7 +776,8 @@ class UFSHostDevice : public DmaDevice
          * SCSI command set; defined in
          * http://www.jedec.org/standards-documents/results/jesd220
          */
-        enum SCSICommandSet {
+        enum SCSICommandSet
+        {
             SCSIInquiry = 0x12,
             SCSIRead6 = 0x08,
             SCSIRead10 = 0x28,
@@ -809,7 +810,8 @@ class UFSHostDevice : public DmaDevice
          * SCSI status codes; defined in
          * http://www.jedec.org/standards-documents/results/jesd220
          */
-        enum SCSIStatusCodes {
+        enum SCSIStatusCodes
+        {
             SCSIGood = 0x00,
             SCSICheckCondition = 0x02,
             SCSIConditionGood = 0x04,
@@ -827,7 +829,8 @@ class UFSHostDevice : public DmaDevice
          * SCSI sense codes; defined in
          * http://www.jedec.org/standards-documents/results/jesd220
          */
-        enum SCSISenseCodes {
+        enum SCSISenseCodes
+        {
             SCSINoSense = 0x00,
             SCSIRecoverdError = 0x01,
             SCSINotReady = 0x02,
@@ -1197,7 +1200,8 @@ class UFSHostDevice : public DmaDevice
      * http://www.jedec.org/standards-documents/results/jesd223
      * for their definition.
      */
-    enum UFSHCIRegisters {
+    enum UFSHCIRegisters
+    {
         regControllerCapabilities = 0x00,
         regUFSVersion = 0x08,
         regControllerDEVID = 0x10,

src/dev/arm/watchdog_sp805.hh

@@ -62,7 +62,8 @@ class Sp805 : public AmbaIntDevice
     Tick write(PacketPtr pkt) override;
 
   private:
-    enum Offset : Addr {
+    enum Offset : Addr
+    {
         WDOGLOAD      = 0x000,
         WDOGVALUE     = 0x004,
         WDOGCONTROL   = 0x008,