misc: Fix coding style for enum's opening braces

The systemc dir was not included in this fix.

First it was identified that there were only occurrences
at 0, 1, and 2 levels of indentation (and 2 of 2 spaces,
1 of 3 spaces and 2 of 12 spaces), using:

    grep -nrE --exclude-dir=systemc \
        "^ *enum [A-Za-z].* {$" src/

Then the following commands were run to replace:

    <indent level>enum X ... {

by:

    <indent level>enum X ...
    <indent level>{

Level 0:
    grep -nrl --exclude-dir=systemc \
        "^enum [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^enum ([A-Za-z].*) \{$/enum \1\n\{/g'

Level 1:
    grep -nrl --exclude-dir=systemc \
        "^    enum [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^    enum ([A-Za-z].*) \{$/    enum \1\n    \{/g'

and so on.

Change-Id: Ib186cf379049098ceaec20dfe4d1edcedd5f940d
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43326
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/dev/arm/energy_ctrl.hh

@@ -97,7 +97,8 @@ class EnergyCtrl : public BasicPioDevice
      *       while (!read(PERF_LEVEL_ACK));
      */
 
-    enum Registers {
+    enum Registers
+    {
         DVFS_HANDLER_STATUS = 0,
         DVFS_NUM_DOMAINS,
         DVFS_DOMAINID_AT_INDEX,

src/dev/arm/flash_device.hh

@@ -68,7 +68,8 @@ class FlashDevice : public AbstractNVM
 
   private:
     /** Defines the possible actions to the flash*/
-    enum Actions {
+    enum Actions
+    {
         ActionRead,
         ActionWrite,
         ActionErase,

src/dev/arm/fvp_base_pwr_ctrl.hh

@@ -106,7 +106,8 @@ class FVPBasePwrCtrl : public BasicPioDevice
         Bitfield<0> pwk;
     EndBitUnion(PwrStatus)
 
-    enum Offset : Addr {
+    enum Offset : Addr
+    {
         PPOFFR = 0x00,
         PPONR  = 0x04,
         PCOFFR = 0x08,

src/dev/arm/hdlcd.hh

@@ -115,7 +115,8 @@ class HDLcd: public AmbaDmaDevice
 
   protected: // Register handling
     /** ARM HDLcd register offsets */
-    enum RegisterOffset {
+    enum RegisterOffset
+    {
         Version          = 0x0000,
         Int_RawStat      = 0x0010,
         Int_Clear        = 0x0014,

src/dev/arm/pl111.hh

@@ -97,7 +97,8 @@ class Pl111: public AmbaDmaDevice
 
     static const int buffer_size = LcdMaxWidth * LcdMaxHeight * sizeof(uint32_t);
 
-    enum LcdMode {
+    enum LcdMode
+    {
         bpp1 = 0,
         bpp2,
         bpp4,

src/dev/arm/rv_ctrl.hh

@@ -51,7 +51,8 @@
 class RealViewCtrl : public BasicPioDevice
 {
   public:
-    enum DeviceFunc {
+    enum DeviceFunc
+    {
         FUNC_OSC      = 1,
         FUNC_VOLT     = 2,
         FUNC_AMP      = 3,

src/dev/arm/smmu_v3_caches.hh

@@ -94,7 +94,8 @@ class SMMUv3BaseCache
 class SMMUTLB : public SMMUv3BaseCache
 {
   public:
-    enum AllocPolicy {
+    enum AllocPolicy
+    {
         ALLOC_ANY_WAY,
         ALLOC_ANY_BUT_LAST_WAY,
         ALLOC_LAST_WAY,

src/dev/arm/smmu_v3_defs.hh

@@ -318,7 +318,8 @@ enum {
     CR0_VMW_MASK = 0x1C0,
 };
 
-enum SMMUCommandType {
+enum SMMUCommandType
+{
     CMD_PRF_CONFIG     = 0x01,
     CMD_PRF_ADDR       = 0x02,
     CMD_CFGI_STE       = 0x03,
@@ -373,11 +374,13 @@ struct SMMUCommand
     }
 };
 
-enum SMMUEventTypes {
+enum SMMUEventTypes
+{
     EVT_FAULT = 0x0001,
 };
 
-enum SMMUEventFlags {
+enum SMMUEventFlags
+{
     EVF_WRITE = 0x0001,
 };
 

src/dev/arm/smmu_v3_proc.hh

@@ -52,7 +52,8 @@ class SMMUv3DeviceInterface;
  * The meaning of these becomes apparent when you
  * look at runProcessAtomic()/runProcessTiming().
  */
-enum SMMUActionType {
+enum SMMUActionType
+{
     ACTION_INITIAL_NOP,
     ACTION_SEND_REQ,
     ACTION_SEND_REQ_FINAL,

src/dev/arm/ufs_device.hh

@@ -776,7 +776,8 @@ class UFSHostDevice : public DmaDevice
          * SCSI command set; defined in
          * http://www.jedec.org/standards-documents/results/jesd220
          */
-        enum SCSICommandSet {
+        enum SCSICommandSet
+        {
             SCSIInquiry = 0x12,
             SCSIRead6 = 0x08,
             SCSIRead10 = 0x28,
@@ -809,7 +810,8 @@ class UFSHostDevice : public DmaDevice
          * SCSI status codes; defined in
          * http://www.jedec.org/standards-documents/results/jesd220
          */
-        enum SCSIStatusCodes {
+        enum SCSIStatusCodes
+        {
             SCSIGood = 0x00,
             SCSICheckCondition = 0x02,
             SCSIConditionGood = 0x04,
@@ -827,7 +829,8 @@ class UFSHostDevice : public DmaDevice
          * SCSI sense codes; defined in
          * http://www.jedec.org/standards-documents/results/jesd220
          */
-        enum SCSISenseCodes {
+        enum SCSISenseCodes
+        {
             SCSINoSense = 0x00,
             SCSIRecoverdError = 0x01,
             SCSINotReady = 0x02,
@@ -1197,7 +1200,8 @@ class UFSHostDevice : public DmaDevice
      * http://www.jedec.org/standards-documents/results/jesd223
      * for their definition.
      */
-    enum UFSHCIRegisters {
+    enum UFSHCIRegisters
+    {
         regControllerCapabilities = 0x00,
         regUFSVersion = 0x08,
         regControllerDEVID = 0x10,

src/dev/arm/watchdog_sp805.hh

@@ -62,7 +62,8 @@ class Sp805 : public AmbaIntDevice
     Tick write(PacketPtr pkt) override;
 
   private:
-    enum Offset : Addr {
+    enum Offset : Addr
+    {
         WDOGLOAD      = 0x000,
         WDOGVALUE     = 0x004,
         WDOGCONTROL   = 0x008,

src/dev/hsa/hsa_signal.hh

@@ -35,7 +35,8 @@
 
 // AMD Signal Kind Enumeration Values.
 typedef int64_t amd_signal_kind64_t;
-enum amd_signal_kind_t {
+enum amd_signal_kind_t
+{
   AMD_SIGNAL_KIND_INVALID = 0,
   AMD_SIGNAL_KIND_USER = 1,
   AMD_SIGNAL_KIND_DOORBELL = -1,

src/dev/i2c/bus.hh

@@ -54,7 +54,8 @@ class I2CBus : public BasicPioDevice
 {
   protected:
 
-    enum I2CState {
+    enum I2CState
+    {
         IDLE,
         RECEIVING_ADDR,
         RECEIVING_DATA,

src/dev/intel_8254_timer.hh

@@ -50,21 +50,24 @@ class Intel8254Timer : public EventManager
         Bitfield<0> bcd;
     EndBitUnion(CtrlReg)
 
-    enum SelectVal {
+    enum SelectVal
+    {
         SelectCounter0,
         SelectCounter1,
         SelectCounter2,
         ReadBackCommand
     };
 
-    enum ReadWriteVal {
+    enum ReadWriteVal
+    {
         LatchCommand,
         LsbOnly,
         MsbOnly,
         TwoPhase
     };
 
-    enum ModeVal {
+    enum ModeVal
+    {
         InitTc,
         OneShot,
         RateGen,

src/dev/net/ns_gige_reg.h

@@ -35,7 +35,8 @@
 #define __DEV_NS_GIGE_REG_H__
 
 /* Device Register Address Map */
-enum DeviceRegisterAddress {
+enum DeviceRegisterAddress
+{
     CR =                0x00,
     CFGR =              0x04,
     MEAR =              0x08,
@@ -78,7 +79,8 @@ enum DeviceRegisterAddress {
 };
 
 /* Chip Command Register */
-enum ChipCommandRegister {
+enum ChipCommandRegister
+{
      CR_TXE =           0x00000001,
      CR_TXD =           0x00000002,
      CR_RXE =           0x00000004,
@@ -90,7 +92,8 @@ enum ChipCommandRegister {
 };
 
 /* configuration register */
-enum ConfigurationRegisters {
+enum ConfigurationRegisters
+{
      CFGR_ZERO =        0x00000000,
      CFGR_LNKSTS =      0x80000000,
      CFGR_SPDSTS =      0x60000000,
@@ -126,7 +129,8 @@ enum ConfigurationRegisters {
 };
 
 /* EEPROM access register */
-enum EEPROMAccessRegister {
+enum EEPROMAccessRegister
+{
      MEAR_EEDI =        0x00000001,
      MEAR_EEDO =        0x00000002,
      MEAR_EECLK =       0x00000004,
@@ -137,7 +141,8 @@ enum EEPROMAccessRegister {
 };
 
 /* PCI test control register */
-enum PCITestControlRegister {
+enum PCITestControlRegister
+{
      PTSCR_EEBIST_FAIL =        0x00000001,
      PTSCR_EEBIST_EN =          0x00000002,
      PTSCR_EELOAD_EN =          0x00000004,
@@ -149,7 +154,8 @@ enum PCITestControlRegister {
 };
 
 /* interrupt status register */
-enum InterruptStatusRegister {
+enum InterruptStatusRegister
+{
      ISR_RESERVE =      0x80000000,
      ISR_TXDESC3 =      0x40000000,
      ISR_TXDESC2 =      0x20000000,
@@ -192,7 +198,8 @@ enum InterruptStatusRegister {
 };
 
 /* transmit configuration register */
-enum TransmitConfigurationRegister {
+enum TransmitConfigurationRegister
+{
      TX_CFG_CSI =       0x80000000,
      TX_CFG_HBI =       0x40000000,
      TX_CFG_MLB =       0x20000000,
@@ -214,7 +221,8 @@ enum TransmitConfigurationRegister {
 };
 
 /*general purpose I/O control register */
-enum GeneralPurposeIOControlRegister {
+enum GeneralPurposeIOControlRegister
+{
      GPIOR_UNUSED =     0xffff8000,
      GPIOR_GP5_IN =     0x00004000,
      GPIOR_GP4_IN =     0x00002000,
@@ -234,7 +242,8 @@ enum GeneralPurposeIOControlRegister {
 };
 
 /* receive configuration register */
-enum ReceiveConfigurationRegister {
+enum ReceiveConfigurationRegister
+{
      RX_CFG_AEP =       0x80000000,
      RX_CFG_ARP =       0x40000000,
      RX_CFG_STRIPCRC =  0x20000000,
@@ -248,7 +257,8 @@ enum ReceiveConfigurationRegister {
 };
 
 /* pause control status register */
-enum PauseControlStatusRegister {
+enum PauseControlStatusRegister
+{
      PCR_PSEN =         (1 << 31),
      PCR_PS_MCAST =     (1 << 30),
      PCR_PS_DA =        (1 << 29),
@@ -260,7 +270,8 @@ enum PauseControlStatusRegister {
 };
 
 /*receive filter/match control register */
-enum ReceiveFilterMatchControlRegister {
+enum ReceiveFilterMatchControlRegister
+{
      RFCR_RFEN =        0x80000000,
      RFCR_AAB =         0x40000000,
      RFCR_AAM =         0x20000000,
@@ -279,14 +290,16 @@ enum ReceiveFilterMatchControlRegister {
 };
 
 /* receive filter/match data register */
-enum ReceiveFilterMatchDataRegister {
+enum ReceiveFilterMatchDataRegister
+{
      RFDR_BMASK =       0x00030000,
      RFDR_RFDATA0 =     0x000000ff,
      RFDR_RFDATA1 =     0x0000ff00
 };
 
 /* management information base control register */
-enum ManagementInformationBaseControlRegister {
+enum ManagementInformationBaseControlRegister
+{
      MIBC_MIBS =        0x00000008,
      MIBC_ACLR =        0x00000004,
      MIBC_FRZ =         0x00000002,
@@ -294,7 +307,8 @@ enum ManagementInformationBaseControlRegister {
 };
 
 /* VLAN/IP receive control register */
-enum VLANIPReceiveControlRegister {
+enum VLANIPReceiveControlRegister
+{
      VRCR_RUDPE =       0x00000080,
      VRCR_RTCPE =       0x00000040,
      VRCR_RIPE =        0x00000020,
@@ -306,7 +320,8 @@ enum VLANIPReceiveControlRegister {
 };
 
 /* VLAN/IP transmit control register */
-enum VLANIPTransmitControlRegister {
+enum VLANIPTransmitControlRegister
+{
      VTCR_PPCHK =       0x00000008,
      VTCR_GCHK =        0x00000004,
      VTCR_VPPTI =       0x00000002,
@@ -314,25 +329,29 @@ enum VLANIPTransmitControlRegister {
 };
 
 /* Clockrun Control/Status Register */
-enum ClockrunControlStatusRegister {
+enum ClockrunControlStatusRegister
+{
      CCSR_CLKRUN_EN =   0x00000001
 };
 
 /* TBI control register */
-enum TBIControlRegister {
+enum TBIControlRegister
+{
      TBICR_MR_LOOPBACK =        0x00004000,
      TBICR_MR_AN_ENABLE =       0x00001000,
      TBICR_MR_RESTART_AN =      0x00000200
 };
 
 /* TBI status register */
-enum TBIStatusRegister {
+enum TBIStatusRegister
+{
      TBISR_MR_LINK_STATUS =     0x00000020,
      TBISR_MR_AN_COMPLETE =     0x00000004
 };
 
 /* TBI auto-negotiation advertisement register */
-enum TBIAutoNegotiationAdvertisementRegister {
+enum TBIAutoNegotiationAdvertisementRegister
+{
      TANAR_NP =         0x00008000,
      TANAR_RF2 =        0x00002000,
      TANAR_RF1 =        0x00001000,
@@ -344,7 +363,8 @@ enum TBIAutoNegotiationAdvertisementRegister {
 };
 
 /* M5 control register */
-enum M5ControlRegister {
+enum M5ControlRegister
+{
      M5REG_RESERVED =   0xfffffffc,
      M5REG_RSS =        0x00000004,
      M5REG_RX_THREAD =  0x00000002,
@@ -368,7 +388,8 @@ struct ns_desc64
 };
 
 /* cmdsts flags for descriptors */
-enum CMDSTSFlatsForDescriptors {
+enum CMDSTSFlatsForDescriptors
+{
      CMDSTS_OWN =       0x80000000,
      CMDSTS_MORE =      0x40000000,
      CMDSTS_INTR =      0x20000000,
@@ -382,7 +403,8 @@ enum CMDSTSFlatsForDescriptors {
 };
 
 /* extended flags for descriptors */
-enum ExtendedFlagsForDescriptors {
+enum ExtendedFlagsForDescriptors
+{
      EXTSTS_UDPERR =    0x00400000,
      EXTSTS_UDPPKT =    0x00200000,
      EXTSTS_TCPERR =    0x00100000,

src/dev/net/sinic.hh

@@ -84,7 +84,8 @@ class Device : public Base
 {
   protected:
     /** Receive State Machine States */
-    enum RxState {
+    enum RxState
+    {
         rxIdle,
         rxFifoBlock,
         rxBeginCopy,
@@ -93,7 +94,8 @@ class Device : public Base
     };
 
     /** Transmit State Machine states */
-    enum TxState {
+    enum TxState
+    {
         txIdle,
         txFifoBlock,
         txBeginCopy,

src/dev/pci/copy_engine.hh

@@ -78,7 +78,8 @@ class CopyEngine : public PciDevice
 
         uint64_t completionDataReg;
 
-        enum ChannelState {
+        enum ChannelState
+        {
             Idle,
             AddressFetch,
             DescriptorFetch,

src/dev/ps2/touchkit.hh

@@ -46,12 +46,14 @@ struct PS2TouchKitParams;
 class PS2TouchKit : public PS2Device, public VncMouse
 {
   protected:
-    enum PS2Commands {
+    enum PS2Commands
+    {
         TpReadId = 0xE1,
         TouchKitDiag = 0x0A,
     };
 
-    enum TKCommands {
+    enum TKCommands
+    {
         TouchKitActive = 'A',
         TouchKitFWRev = 'D',
         TouchKitCtrlType = 'E',

src/dev/reg_bank.test.cc

@@ -896,7 +896,8 @@ class RegisterBankTest : public testing::Test
         {}
     };
 
-    enum AccessType {
+    enum AccessType
+    {
         Read,
         Write,
         PartialRead,

src/dev/serial/uart8250.hh

@@ -80,7 +80,8 @@ class Uart8250 : public Uart
         Bitfield<7> unused;
     EndBitUnion(Lsr)
 
-    enum class InterruptIds {
+    enum class InterruptIds
+    {
         Modem = 0, // Modem Status (lowest priority).
         Tx = 1,    // Tx Data.
         Rx = 2,    // Rx Data.

src/dev/sparc/iob.hh

@@ -78,7 +78,8 @@ class Iob : public PioDevice
     Addr iobJBusSize;
     Tick pioDelay;
 
-    enum DeviceId {
+    enum DeviceId
+    {
         Interal = 0,
         Error = 1,
         SSI = 2,
@@ -104,7 +105,8 @@ class Iob : public PioDevice
         int source;
     };
 
-    enum Type {
+    enum Type
+    {
         Interrupt,
         Reset,
         Idle,

src/dev/storage/ide_ctrl.cc

@@ -56,7 +56,8 @@
 using std::string;
 
 // Bus master IDE registers
-enum BMIRegOffset {
+enum BMIRegOffset
+{
     BMICommand = 0x0,
     BMIStatus = 0x2,
     BMIDescTablePtr = 0x4