misc: Fix coding style for enum's opening braces

The systemc dir was not included in this fix.

First it was identified that there were only occurrences
at 0, 1, and 2 levels of indentation (and 2 of 2 spaces,
1 of 3 spaces and 2 of 12 spaces), using:

    grep -nrE --exclude-dir=systemc \
        "^ *enum [A-Za-z].* {$" src/

Then the following commands were run to replace:

    <indent level>enum X ... {

by:

    <indent level>enum X ...
    <indent level>{

Level 0:
    grep -nrl --exclude-dir=systemc \
        "^enum [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^enum ([A-Za-z].*) \{$/enum \1\n\{/g'

Level 1:
    grep -nrl --exclude-dir=systemc \
        "^    enum [A-Za-z].* {$" src/ | \
        xargs sed -Ei \
        's/^    enum ([A-Za-z].*) \{$/    enum \1\n    \{/g'

and so on.

Change-Id: Ib186cf379049098ceaec20dfe4d1edcedd5f940d
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/43326
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/cpu/base.hh

@@ -520,7 +520,8 @@ class BaseCPU : public ClockedObject
     ProbePointArg<bool> *ppSleeping;
     /** @} */
 
-    enum CPUState {
+    enum CPUState
+    {
         CPU_STATE_ON,
         CPU_STATE_SLEEP,
         CPU_STATE_WAKEUP

src/cpu/base_dyn_inst.hh

@@ -92,7 +92,8 @@ class BaseDynInst : public ExecContext, public RefCounted
     typedef typename std::list<DynInstPtr>::iterator ListIt;
 
   protected:
-    enum Status {
+    enum Status
+    {
         IqEntry,                 /// Instruction is in the IQ
         RobEntry,                /// Instruction is in the ROB
         LsqEntry,                /// Instruction is in the LSQ
@@ -121,7 +122,8 @@ class BaseDynInst : public ExecContext, public RefCounted
         NumStatus
     };
 
-    enum Flags {
+    enum Flags
+    {
         NotAnInst,
         TranslationStarted,
         TranslationCompleted,

src/cpu/inst_res.hh

@@ -55,7 +55,8 @@ class InstResult
         MultiResult() {}
     };
 
-    enum class ResultType {
+    enum class ResultType
+    {
         Scalar,
         VecElem,
         VecReg,

src/cpu/kvm/base.hh

@@ -175,7 +175,8 @@ class BaseKvmCPU : public BaseCPU
      *   }
      * @enddot
      */
-    enum Status {
+    enum Status
+    {
         /** Context not scheduled in KVM.
          *
          * The CPU generally enters this state when the guest execute

src/cpu/o3/commit.hh

@@ -108,7 +108,8 @@ class DefaultCommit
     };
 
     /** Individual thread status. */
-    enum ThreadStatus {
+    enum ThreadStatus
+    {
         Running,
         Idle,
         ROBSquashing,

src/cpu/o3/cpu.hh

@@ -104,7 +104,8 @@ class FullO3CPU : public BaseO3CPU
     friend class O3ThreadContext<Impl>;
 
   public:
-    enum Status {
+    enum Status
+    {
         Running,
         Idle,
         Halted,
@@ -537,7 +538,8 @@ class FullO3CPU : public BaseO3CPU
      *  activateStage() or deactivateStage(), they can specify which stage
      *  is being activated/deactivated.
      */
-    enum StageIdx {
+    enum StageIdx
+    {
         FetchIdx,
         DecodeIdx,
         RenameIdx,

src/cpu/o3/decode.hh

@@ -73,13 +73,15 @@ class DefaultDecode
     /** Overall decode stage status. Used to determine if the CPU can
      * deschedule itself due to a lack of activity.
      */
-    enum DecodeStatus {
+    enum DecodeStatus
+    {
         Active,
         Inactive
     };
 
     /** Individual thread status. */
-    enum ThreadStatus {
+    enum ThreadStatus
+    {
         Running,
         Idle,
         StartSquash,

src/cpu/o3/fetch.hh

@@ -172,13 +172,15 @@ class DefaultFetch
     /** Overall fetch status. Used to determine if the CPU can
      * deschedule itsef due to a lack of activity.
      */
-    enum FetchStatus {
+    enum FetchStatus
+    {
         Active,
         Inactive
     };
 
     /** Individual thread status. */
-    enum ThreadStatus {
+    enum ThreadStatus
+    {
         Running,
         Idle,
         Squashing,

src/cpu/o3/iew.hh

@@ -96,13 +96,15 @@ class DefaultIEW
     /** Overall IEW stage status. Used to determine if the CPU can
      * deschedule itself due to a lack of activity.
      */
-    enum Status {
+    enum Status
+    {
         Active,
         Inactive
     };
 
     /** Status for Issue, Execute, and Writeback stages. */
-    enum StageStatus {
+    enum StageStatus
+    {
         Running,
         Blocked,
         Idle,

src/cpu/o3/rename.hh

@@ -93,13 +93,15 @@ class DefaultRename
     /** Overall rename status. Used to determine if the CPU can
      * deschedule itself due to a lack of activity.
      */
-    enum RenameStatus {
+    enum RenameStatus
+    {
         Active,
         Inactive
     };
 
     /** Individual thread status. */
-    enum ThreadStatus {
+    enum ThreadStatus
+    {
         Running,
         Idle,
         StartSquash,
@@ -468,7 +470,8 @@ class DefaultRename
     /** Enum to record the source of a structure full stall.  Can come from
      * either ROB, IQ, LSQ, and it is priortized in that order.
      */
-    enum FullSource {
+    enum FullSource
+    {
         ROB,
         IQ,
         LQ,

src/cpu/o3/rob.hh

@@ -67,7 +67,8 @@ class ROB
     typedef typename std::list<DynInstPtr>::iterator InstIt;
 
     /** Possible ROB statuses. */
-    enum Status {
+    enum Status
+    {
         Running,
         Idle,
         ROBSquashing

src/cpu/reg_class.hh

@@ -49,7 +49,8 @@
 #include "config/the_isa.hh"
 
 /** Enumerate the classes of registers. */
-enum RegClass {
+enum RegClass
+{
     IntRegClass,        ///< Integer register
     FloatRegClass,      ///< Floating-point register
     /** Vector Register. */

src/cpu/simple/base.hh

@@ -104,7 +104,8 @@ class BaseSimpleCPU : public BaseCPU
     StaticInstPtr curMacroStaticInst;
 
   protected:
-    enum Status {
+    enum Status
+    {
         Idle,
         Running,
         Faulting,

src/cpu/testers/gpu_ruby_test/episode.hh

@@ -50,7 +50,8 @@ class Episode
     class Action
     {
       public:
-        enum class Type {
+        enum class Type
+        {
             ACQUIRE,
             RELEASE,
             ATOMIC,