mem: hmc: serial link model

This changeset adds a serial link model for the Hybrid Memory Cube (HMC).
SerialLink is a simple variation of the Bridge class, with the ability to
account for the latency of packet serialization. Also trySendTiming has been
modified to correctly model bandwidth.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

src/mem/SConscript

@@ -43,6 +43,7 @@ SimObject('MemObject.py')
 SimObject('SimpleMemory.py')
 SimObject('XBar.py')
 SimObject('HMCController.py')
+SimObject('SerialLink.py')
 
 Source('abstract_mem.cc')
 Source('addr_mapper.cc')
@@ -66,6 +67,7 @@ Source('stack_dist_calc.cc')
 Source('tport.cc')
 Source('xbar.cc')
 Source('hmc_controller.cc')
+Source('serial_link.cc')
 
 if env['TARGET_ISA'] != 'null':
     Source('fs_translating_port_proxy.cc')
@@ -104,6 +106,7 @@ DebugFlag('PacketQueue')
 DebugFlag('StackDist')
 DebugFlag("DRAMSim2")
 DebugFlag('HMCController')
+DebugFlag('SerialLink')
 
 DebugFlag("MemChecker")
 DebugFlag("MemCheckerMonitor")