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tlb: Don't separate the TLB classes into an instruction TLB and a data TLB

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This commit is contained in:
Gabe Black
2009-04-08 22:21:27 -07:00
parent 08043c777f
commit 7b5a96f06b
34 changed files with 309 additions and 600 deletions
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26
src/cpu/BaseCPU.py
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@@ -38,19 +38,19 @@ import sys
default_tracer = ExeTracer()
if build_env['TARGET_ISA'] == 'alpha':
from AlphaTLB import AlphaDTB, AlphaITB
from AlphaTLB import AlphaTLB
if build_env['FULL_SYSTEM']:
from AlphaInterrupts import AlphaInterrupts
elif build_env['TARGET_ISA'] == 'sparc':
from SparcTLB import SparcDTB, SparcITB
from SparcTLB import SparcTLB
if build_env['FULL_SYSTEM']:
from SparcInterrupts import SparcInterrupts
elif build_env['TARGET_ISA'] == 'x86':
from X86TLB import X86DTB, X86ITB
from X86TLB import X86TLB
if build_env['FULL_SYSTEM']:
from X86LocalApic import X86LocalApic
elif build_env['TARGET_ISA'] == 'mips':
from MipsTLB import MipsTLB,MipsDTB, MipsITB, MipsUTB
from MipsTLB import MipsTLB
if build_env['FULL_SYSTEM']:
from MipsInterrupts import MipsInterrupts
elif build_env['TARGET_ISA'] == 'arm':
@@ -83,29 +83,27 @@ class BaseCPU(MemObject):
workload = VectorParam.Process("processes to run")
if build_env['TARGET_ISA'] == 'sparc':
dtb = Param.SparcDTB(SparcDTB(), "Data TLB")
itb = Param.SparcITB(SparcITB(), "Instruction TLB")
dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
if build_env['FULL_SYSTEM']:
interrupts = Param.SparcInterrupts(
SparcInterrupts(), "Interrupt Controller")
elif build_env['TARGET_ISA'] == 'alpha':
dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB")
itb = Param.AlphaITB(AlphaITB(), "Instruction TLB")
dtb = Param.AlphaTLB(AlphaTLB(size=64), "Data TLB")
itb = Param.AlphaTLB(AlphaTLB(size=48), "Instruction TLB")
if build_env['FULL_SYSTEM']:
interrupts = Param.AlphaInterrupts(
AlphaInterrupts(), "Interrupt Controller")
elif build_env['TARGET_ISA'] == 'x86':
dtb = Param.X86DTB(X86DTB(), "Data TLB")
itb = Param.X86ITB(X86ITB(), "Instruction TLB")
dtb = Param.X86TLB(X86TLB(), "Data TLB")
itb = Param.X86TLB(X86TLB(), "Instruction TLB")
if build_env['FULL_SYSTEM']:
_localApic = X86LocalApic(pio_addr=0x2000000000000000)
interrupts = \
Param.X86LocalApic(_localApic, "Interrupt Controller")
elif build_env['TARGET_ISA'] == 'mips':
UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
dtb = Param.MipsDTB(MipsDTB(), "Data TLB")
itb = Param.MipsITB(MipsITB(), "Instruction TLB")
tlb = Param.MipsUTB(MipsUTB(), "Unified TLB")
dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
if build_env['FULL_SYSTEM']:
interrupts = Param.MipsInterrupts(
MipsInterrupts(), "Interrupt Controller")

7
src/cpu/checker/cpu.hh
View File

@@ -49,8 +49,7 @@
#if FULL_SYSTEM
namespace TheISA
{
class ITB;
class DTB;
class TLB;
}
class Processor;
class PhysicalMemory;
@@ -130,8 +129,8 @@ class CheckerCPU : public BaseCPU
ThreadContext *tc;
TheISA::ITB *itb;
TheISA::DTB *dtb;
TheISA::TLB *itb;
TheISA::TLB *dtb;
#if FULL_SYSTEM
Addr dbg_vtophys(Addr addr);

4
src/cpu/checker/thread_context.hh
View File

@@ -84,9 +84,9 @@ class CheckerThreadContext : public ThreadContext
int cpuId() { return actualTC->cpuId(); }
TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); }
TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); }
TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); }
TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
#if FULL_SYSTEM
System *getSystemPtr() { return actualTC->getSystemPtr(); }

4
src/cpu/inorder/cpu.hh
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@@ -103,8 +103,8 @@ class InOrderCPU : public BaseCPU
Params *cpu_params;
TheISA::ITB * itb;
TheISA::DTB * dtb;
TheISA::TLB * itb;
TheISA::TLB * dtb;
public:
enum Status {

2
src/cpu/inorder/resources/tlb_unit.cc
View File

@@ -99,7 +99,7 @@ TLBUnit::execute(int slot_idx)
{
tlb_req->fault =
this->cpu->itb->translateAtomic(tlb_req->memReq,
cpu->thread[tid]->getTC());
cpu->thread[tid]->getTC(), false, true);
if (tlb_req->fault != NoFault) {
DPRINTF(InOrderTLB, "[tid:%i]: %s encountered while translating "

4
src/cpu/inorder/thread_context.hh
View File

@@ -65,10 +65,10 @@ class InOrderThreadContext : public ThreadContext
/** Returns a pointer to the ITB. */
TheISA::ITB *getITBPtr() { return cpu->itb; }
TheISA::TLB *getITBPtr() { return cpu->itb; }
/** Returns a pointer to the DTB. */
TheISA::DTB *getDTBPtr() { return cpu->dtb; }
TheISA::TLB *getDTBPtr() { return cpu->dtb; }
System *getSystemPtr() { return cpu->system; }

4
src/cpu/o3/cpu.hh
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@@ -106,8 +106,8 @@ class FullO3CPU : public BaseO3CPU
SwitchedOut
};
TheISA::ITB * itb;
TheISA::DTB * dtb;
TheISA::TLB * itb;
TheISA::TLB * dtb;
/** Overall CPU status. */
Status _status;

3
src/cpu/o3/fetch_impl.hh
View File

@@ -601,7 +601,8 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid
memReq[tid] = mem_req;
// Translate the instruction request.
fault = cpu->itb->translateAtomic(mem_req, cpu->thread[tid]->getTC());
fault = cpu->itb->translateAtomic(mem_req, cpu->thread[tid]->getTC(),
false, true);
// In the case of faults, the fetch stage may need to stall and wait
// for the ITB miss to be handled.

4
src/cpu/o3/thread_context.hh
View File

@@ -67,10 +67,10 @@ class O3ThreadContext : public ThreadContext
O3ThreadState<Impl> *thread;
/** Returns a pointer to the ITB. */
TheISA::ITB *getITBPtr() { return cpu->itb; }
TheISA::TLB *getITBPtr() { return cpu->itb; }
/** Returns a pointer to the DTB. */
TheISA::DTB *getDTBPtr() { return cpu->dtb; }
TheISA::TLB *getDTBPtr() { return cpu->dtb; }
/** Returns a pointer to this CPU. */
virtual BaseCPU *getCpuPtr() { return cpu; }

11
src/cpu/ozone/cpu.hh
View File

@@ -53,8 +53,7 @@
namespace TheISA
{
class ITB;
class DTB;
class TLB;
}
class PhysicalMemory;
class MemoryController;
@@ -116,9 +115,9 @@ class OzoneCPU : public BaseCPU
BaseCPU *getCpuPtr();
TheISA::ITB *getITBPtr() { return cpu->itb; }
TheISA::TLB *getITBPtr() { return cpu->itb; }
TheISA::DTB * getDTBPtr() { return cpu->dtb; }
TheISA::TLB * getDTBPtr() { return cpu->dtb; }
#if FULL_SYSTEM
System *getSystemPtr() { return cpu->system; }
@@ -349,8 +348,8 @@ class OzoneCPU : public BaseCPU
bool interval_stats;
TheISA::ITB *itb;
TheISA::DTB *dtb;
TheISA::TLB *itb;
TheISA::TLB *dtb;
System *system;
PhysicalMemory *physmem;
#endif

2
src/cpu/ozone/front_end_impl.hh
View File

@@ -480,7 +480,7 @@ FrontEnd<Impl>::fetchCacheLine()
PC, cpu->thread->contextId());
// Translate the instruction request.
fault = cpu->itb->translateAtomic(memReq, thread);
fault = cpu->itb->translateAtomic(memReq, thread, false, true);
// Now do the timing access to see whether or not the instruction
// exists within the cache.

5
src/cpu/ozone/simple_params.hh
View File

@@ -36,8 +36,7 @@
//Forward declarations
namespace TheISA
{
class DTB;
class ITB;
class TLB;
}
class FUPool;
class MemObject;
@@ -55,7 +54,7 @@ class SimpleParams : public BaseCPU::Params
{
public:
TheISA::ITB *itb; TheISA::DTB *dtb;
TheISA::TLB *itb; TheISA::TLB *dtb;
#if !FULL_SYSTEM
std::vector<Process *> workload;
#endif // FULL_SYSTEM

2
src/cpu/simple/atomic.cc
View File

@@ -609,7 +609,7 @@ AtomicSimpleCPU::tick()
bool fromRom = isRomMicroPC(thread->readMicroPC());
if (!fromRom && !curMacroStaticInst) {
setupFetchRequest(&ifetch_req);
fault = thread->itb->translateAtomic(&ifetch_req, tc);
fault = thread->itb->translateAtomic(&ifetch_req, tc, false, true);
}
if (fault == NoFault) {

2
src/cpu/simple/timing.cc
View File

@@ -672,7 +672,7 @@ TimingSimpleCPU::fetch()
ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0);
setupFetchRequest(ifetch_req);
thread->itb->translateTiming(ifetch_req, tc,
&fetchTranslation);
&fetchTranslation, false, true);
} else {
_status = IcacheWaitResponse;
completeIfetch(NULL);

6
src/cpu/simple/timing.hh
View File

@@ -106,7 +106,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
{}
void finish(Fault fault, RequestPtr req,
ThreadContext *tc, bool write)
ThreadContext *tc, bool write, bool execute)
{
cpu->sendFetch(fault, req, tc);
}
@@ -129,7 +129,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
void
finish(Fault fault, RequestPtr req,
ThreadContext *tc, bool write)
ThreadContext *tc, bool write, bool execute)
{
cpu->sendData(fault, req, data, res, read);
delete this;
@@ -173,7 +173,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
void
finish(Fault fault, RequestPtr req,
ThreadContext *tc, bool write)
ThreadContext *tc, bool write, bool execute)
{
assert(state);
assert(state->outstanding);

4
src/cpu/simple_thread.cc
View File

@@ -61,7 +61,7 @@ using namespace std;
// constructor
#if FULL_SYSTEM
SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
TheISA::ITB *_itb, TheISA::DTB *_dtb,
TheISA::TLB *_itb, TheISA::TLB *_dtb,
bool use_kernel_stats)
: ThreadState(_cpu, _thread_num), cpu(_cpu), system(_sys), itb(_itb),
dtb(_dtb)
@@ -92,7 +92,7 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
}
#else
SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
TheISA::ITB *_itb, TheISA::DTB *_dtb, int _asid)
TheISA::TLB *_itb, TheISA::TLB *_dtb, int _asid)
: ThreadState(_cpu, _thread_num, _process, _asid),
cpu(_cpu), itb(_itb), dtb(_dtb)
{

12
src/cpu/simple_thread.hh
View File

@@ -108,17 +108,17 @@ class SimpleThread : public ThreadState
System *system;
TheISA::ITB *itb;
TheISA::DTB *dtb;
TheISA::TLB *itb;
TheISA::TLB *dtb;
// constructor: initialize SimpleThread from given process structure
#if FULL_SYSTEM
SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
TheISA::ITB *_itb, TheISA::DTB *_dtb,
TheISA::TLB *_itb, TheISA::TLB *_dtb,
bool use_kernel_stats = true);
#else
SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
TheISA::ITB *_itb, TheISA::DTB *_dtb, int _asid);
TheISA::TLB *_itb, TheISA::TLB *_dtb, int _asid);
#endif
SimpleThread();
@@ -181,9 +181,9 @@ class SimpleThread : public ThreadState
BaseCPU *getCpuPtr() { return cpu; }
TheISA::ITB *getITBPtr() { return itb; }
TheISA::TLB *getITBPtr() { return itb; }
TheISA::DTB *getDTBPtr() { return dtb; }
TheISA::TLB *getDTBPtr() { return dtb; }
System *getSystemPtr() { return system; }

11
src/cpu/thread_context.hh
View File

@@ -44,8 +44,7 @@
// DTB pointers.
namespace TheISA
{
class DTB;
class ITB;
class TLB;
}
class BaseCPU;
class EndQuiesceEvent;
@@ -124,9 +123,9 @@ class ThreadContext
virtual void setContextId(int id) = 0;
virtual TheISA::ITB *getITBPtr() = 0;
virtual TheISA::TLB *getITBPtr() = 0;
virtual TheISA::DTB *getDTBPtr() = 0;
virtual TheISA::TLB *getDTBPtr() = 0;
virtual System *getSystemPtr() = 0;
@@ -306,9 +305,9 @@ class ProxyThreadContext : public ThreadContext
void setContextId(int id) { actualTC->setContextId(id); }
TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); }
TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); }
TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); }
TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
System *getSystemPtr() { return actualTC->getSystemPtr(); }