diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index a66a938606..4033d0ff4f 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -280,8 +280,6 @@ ISA::initID32(const ArmISAParams &p)
     miscRegs[MISCREG_ID_ISAR2] = p.id_isar2;
     miscRegs[MISCREG_ID_ISAR3] = p.id_isar3;
     miscRegs[MISCREG_ID_ISAR4] = p.id_isar4;
-    miscRegs[MISCREG_ID_ISAR5] = p.id_isar5;
-    miscRegs[MISCREG_ID_ISAR6] = p.id_isar6;
 
     miscRegs[MISCREG_ID_MMFR0] = p.id_mmfr0;
     miscRegs[MISCREG_ID_MMFR1] = p.id_mmfr1;
@@ -289,24 +287,25 @@ ISA::initID32(const ArmISAParams &p)
     miscRegs[MISCREG_ID_MMFR3] = p.id_mmfr3;
     miscRegs[MISCREG_ID_MMFR4] = p.id_mmfr4;
 
-    /** MISCREG_ID_ISAR5 */
-    // Crypto
-    miscRegs[MISCREG_ID_ISAR5] = insertBits(
-        miscRegs[MISCREG_ID_ISAR5], 19, 4,
-        release->has(ArmExtension::CRYPTO) ? 0x1112 : 0x0);
-    // RDM
-    miscRegs[MISCREG_ID_ISAR5] = insertBits(
-        miscRegs[MISCREG_ID_ISAR5], 27, 24,
-        release->has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0);
-    // FCMA
-    miscRegs[MISCREG_ID_ISAR5] = insertBits(
-        miscRegs[MISCREG_ID_ISAR5], 31, 28,
-        release->has(ArmExtension::FEAT_FCMA) ? 0x1 : 0x0);
+    ISAR5 isar5 = p.id_isar5;
+    if (release->has(ArmExtension::CRYPTO)) {
+        isar5.crc32 = 1;
+        isar5.sha2 = 1;
+        isar5.sha1 = 1;
+        isar5.aes = 2;
+    } else {
+        isar5.crc32 = 0;
+        isar5.sha2 = 0;
+        isar5.sha1 = 0;
+        isar5.aes = 0;
+    }
+    isar5.rdm = release->has(ArmExtension::FEAT_RDM) ? 0x1 : 0x0;
+    isar5.vcma = release->has(ArmExtension::FEAT_FCMA) ? 0x1 : 0x0;
+    miscRegs[MISCREG_ID_ISAR5] = isar5;
 
-    /** ID_ISAR6 */
-    miscRegs[MISCREG_ID_ISAR6] = insertBits(
-        miscRegs[MISCREG_ID_ISAR6], 3, 0,
-        release->has(ArmExtension::FEAT_JSCVT) ? 0x1 : 0x0);
+    ISAR6 isar6 = p.id_isar6;
+    isar6.jscvt = release->has(ArmExtension::FEAT_JSCVT) ? 0x1 : 0x0;
+    miscRegs[MISCREG_ID_ISAR6] = isar6;
 }
 
 void
diff --git a/src/arch/arm/regs/misc_types.hh b/src/arch/arm/regs/misc_types.hh
index 0fe5a00ae8..9af5337a33 100644
--- a/src/arch/arm/regs/misc_types.hh
+++ b/src/arch/arm/regs/misc_types.hh
@@ -75,6 +75,27 @@ namespace ArmISA
         Bitfield<0> sp;         // AArch64
     EndBitUnion(CPSR)
 
+    BitUnion32(ISAR5)
+        Bitfield<31, 28> vcma;
+        Bitfield<27, 24> rdm;
+        Bitfield<19, 16> crc32;
+        Bitfield<15, 12> sha2;
+        Bitfield<11, 8> sha1;
+        Bitfield<7, 4> aes;
+        Bitfield<3, 0> sevl;
+    EndBitUnion(ISAR5)
+
+    BitUnion32(ISAR6)
+        Bitfield<31, 28> clrbhb;
+        Bitfield<27, 24> i8mm;
+        Bitfield<23, 20> bf16;
+        Bitfield<19, 16> specres;
+        Bitfield<15, 12> sb;
+        Bitfield<11, 8> fhm;
+        Bitfield<7, 4> dp;
+        Bitfield<3, 0> jscvt;
+    EndBitUnion(ISAR6)
+
     BitUnion64(AA64DFR0)
         Bitfield<43, 40> tracefilt;
         Bitfield<39, 36> doublelock;