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style: [patch 1/22] use /r/3648/ to reorganize includes

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This commit is contained in:
Brandon Potter
2016-11-09 14:27:37 -06:00
parent 63bb17e4bd
commit 7a8dda49a4
353 changed files with 700 additions and 383 deletions
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3
src/mem/abstract_mem.cc
View File

@@ -42,13 +42,14 @@
* Andreas Hansson
*/
#include "mem/abstract_mem.hh"
#include <vector>
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/LLSC.hh"
#include "debug/MemoryAccess.hh"
#include "mem/abstract_mem.hh"
#include "mem/packet_access.hh"
#include "sim/system.hh"

3
src/mem/bridge.cc
View File

@@ -48,9 +48,10 @@
* and a slave through a request and response queue.
*/
#include "mem/bridge.hh"
#include "base/trace.hh"
#include "debug/Bridge.hh"
#include "mem/bridge.hh"
#include "params/Bridge.hh"
Bridge::BridgeSlavePort::BridgeSlavePort(const std::string& _name,

3
src/mem/cache/prefetch/base.cc vendored
View File

@@ -46,10 +46,11 @@
* Hardware Prefetcher Definition.
*/
#include "mem/cache/prefetch/base.hh"
#include <list>
#include "base/intmath.hh"
#include "mem/cache/prefetch/base.hh"
#include "mem/cache/base.hh"
#include "sim/system.hh"

3
src/mem/cache/prefetch/queued.cc vendored
View File

@@ -37,8 +37,9 @@
* Authors: Mitch Hayenga
*/
#include "debug/HWPrefetch.hh"
#include "mem/cache/prefetch/queued.hh"
#include "debug/HWPrefetch.hh"
#include "mem/cache/base.hh"
QueuedPrefetcher::QueuedPrefetcher(const QueuedPrefetcherParams *p)

3
src/mem/cache/prefetch/stride.cc vendored
View File

@@ -46,9 +46,10 @@
* Stride Prefetcher template instantiations.
*/
#include "mem/cache/prefetch/stride.hh"
#include "base/random.hh"
#include "debug/HWPrefetch.hh"
#include "mem/cache/prefetch/stride.hh"
StridePrefetcher::StridePrefetcher(const StridePrefetcherParams *p)
: QueuedPrefetcher(p),

3
src/mem/coherent_xbar.cc
View File

@@ -47,11 +47,12 @@
* Definition of a crossbar object.
*/
#include "mem/coherent_xbar.hh"
#include "base/misc.hh"
#include "base/trace.hh"
#include "debug/AddrRanges.hh"
#include "debug/CoherentXBar.hh"
#include "mem/coherent_xbar.hh"
#include "sim/system.hh"
CoherentXBar::CoherentXBar(const CoherentXBarParams *p)

3
src/mem/comm_monitor.cc
View File

@@ -38,9 +38,10 @@
* Andreas Hansson
*/
#include "mem/comm_monitor.hh"
#include "base/trace.hh"
#include "debug/CommMonitor.hh"
#include "mem/comm_monitor.hh"
#include "sim/stats.hh"
CommMonitor::CommMonitor(Params* params)

3
src/mem/dram_ctrl.cc
View File

@@ -44,13 +44,14 @@
* Wendy Elsasser
*/
#include "mem/dram_ctrl.hh"
#include "base/bitfield.hh"
#include "base/trace.hh"
#include "debug/DRAM.hh"
#include "debug/DRAMPower.hh"
#include "debug/DRAMState.hh"
#include "debug/Drain.hh"
#include "mem/dram_ctrl.hh"
#include "sim/system.hh"
using namespace std;

3
src/mem/drampower.cc
View File

@@ -37,8 +37,9 @@
* Authors: Omar Naji
*/
#include "base/intmath.hh"
#include "mem/drampower.hh"
#include "base/intmath.hh"
#include "sim/core.hh"
using namespace Data;

3
src/mem/dramsim2.cc
View File

@@ -37,12 +37,13 @@
* Authors: Andreas Hansson
*/
#include "mem/dramsim2.hh"
#include "DRAMSim2/Callback.h"
#include "base/callback.hh"
#include "base/trace.hh"
#include "debug/DRAMSim2.hh"
#include "debug/Drain.hh"
#include "mem/dramsim2.hh"
#include "sim/system.hh"
DRAMSim2::DRAMSim2(const Params* p) :

3
src/mem/dramsim2_wrapper.cc
View File

@@ -48,12 +48,13 @@
#undef DEBUG
#endif
#include "mem/dramsim2_wrapper.hh"
#include <fstream>
#include "DRAMSim2/MultiChannelMemorySystem.h"
#include "base/compiler.hh"
#include "base/misc.hh"
#include "mem/dramsim2_wrapper.hh"
/**
* DRAMSim2 requires SHOW_SIM_OUTPUT to be defined (declared extern in

3
src/mem/external_master.cc
View File

@@ -38,11 +38,12 @@
* Curtis Dunham
*/
#include "mem/external_master.hh"
#include <cctype>
#include <iomanip>
#include "debug/ExternalPort.hh"
#include "mem/external_master.hh"
std::map<std::string, ExternalMaster::Handler *>
ExternalMaster::portHandlers;

3
src/mem/external_slave.cc
View File

@@ -37,11 +37,12 @@
* Authors: Andrew Bardsley
*/
#include "mem/external_slave.hh"
#include <cctype>
#include <iomanip>
#include "debug/ExternalPort.hh"
#include "mem/external_slave.hh"
/** Implement a `stub' port which just responds to requests by printing
* a message. The stub port can be used to configure and test a system

3
src/mem/fs_translating_port_proxy.cc
View File

@@ -46,11 +46,12 @@
* Port object definitions.
*/
#include "mem/fs_translating_port_proxy.hh"
#include "arch/vtophys.hh"
#include "base/chunk_generator.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "mem/fs_translating_port_proxy.hh"
#include "sim/system.hh"
using namespace TheISA;

3
src/mem/hmc_controller.cc
View File

@@ -1,6 +1,7 @@
#include "mem/hmc_controller.hh"
#include "base/random.hh"
#include "debug/HMCController.hh"
#include "mem/hmc_controller.hh"
HMCController::HMCController(const HMCControllerParams* p) :
NoncoherentXBar(p),

4
src/mem/mem_checker.cc
View File

@@ -38,10 +38,10 @@
* Marco Elver
*/
#include <cassert>
#include "mem/mem_checker.hh"
#include <cassert>
void
MemChecker::WriteCluster::startWrite(MemChecker::Serial serial, Tick _start,
uint8_t data)

3
src/mem/mem_checker_monitor.cc
View File

@@ -39,12 +39,13 @@
* Marco Elver
*/
#include "mem/mem_checker_monitor.hh"
#include <memory>
#include "base/output.hh"
#include "base/trace.hh"
#include "debug/MemCheckerMonitor.hh"
#include "mem/mem_checker_monitor.hh"
using namespace std;

3
src/mem/noncoherent_xbar.cc
View File

@@ -47,11 +47,12 @@
* Definition of a non-coherent crossbar object.
*/
#include "mem/noncoherent_xbar.hh"
#include "base/misc.hh"
#include "base/trace.hh"
#include "debug/NoncoherentXBar.hh"
#include "debug/XBar.hh"
#include "mem/noncoherent_xbar.hh"
NoncoherentXBar::NoncoherentXBar(const NoncoherentXBarParams *p)
: BaseXBar(p)

3
src/mem/packet.cc
View File

@@ -48,13 +48,14 @@
* between a single level of the memory heirarchy (ie L1->L2).
*/
#include "mem/packet.hh"
#include <cstring>
#include <iostream>
#include "base/cprintf.hh"
#include "base/misc.hh"
#include "base/trace.hh"
#include "mem/packet.hh"
using namespace std;

3
src/mem/packet_queue.cc
View File

@@ -41,10 +41,11 @@
* Andreas Hansson
*/
#include "mem/packet_queue.hh"
#include "base/trace.hh"
#include "debug/Drain.hh"
#include "debug/PacketQueue.hh"
#include "mem/packet_queue.hh"
using namespace std;

3
src/mem/page_table.cc
View File

@@ -35,6 +35,8 @@
* @file
* Definitions of functional page table.
*/
#include "mem/page_table.hh"
#include <fstream>
#include <map>
#include <memory>
@@ -45,7 +47,6 @@
#include "base/trace.hh"
#include "config/the_isa.hh"
#include "debug/MMU.hh"
#include "mem/page_table.hh"
#include "sim/faults.hh"
#include "sim/sim_object.hh"

5
src/mem/physical.cc
View File

@@ -37,10 +37,12 @@
* Authors: Andreas Hansson
*/
#include "mem/physical.hh"
#include <fcntl.h>
#include <sys/mman.h>
#include <sys/types.h>
#include <sys/user.h>
#include <fcntl.h>
#include <unistd.h>
#include <zlib.h>
@@ -54,7 +56,6 @@
#include "debug/AddrRanges.hh"
#include "debug/Checkpoint.hh"
#include "mem/abstract_mem.hh"
#include "mem/physical.hh"
/**
* On Linux, MAP_NORESERVE allow us to simulate a very large memory

3
src/mem/port.cc
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@@ -46,9 +46,10 @@
* @file
* Port object definitions.
*/
#include "mem/port.hh"
#include "base/trace.hh"
#include "mem/mem_object.hh"
#include "mem/port.hh"
Port::Port(const std::string &_name, MemObject& _owner, PortID _id)
: portName(_name), id(_id), owner(_owner)

3
src/mem/port_proxy.cc
View File

@@ -37,9 +37,10 @@
* Authors: Andreas Hansson
*/
#include "base/chunk_generator.hh"
#include "mem/port_proxy.hh"
#include "base/chunk_generator.hh"
void
PortProxy::readBlob(Addr addr, uint8_t *p, int size) const
{

1
src/mem/probes/base.cc
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@@ -41,7 +41,6 @@
#include "params/BaseMemProbe.hh"
BaseMemProbe::BaseMemProbe(BaseMemProbeParams *p)
: SimObject(p)
{

3
src/mem/ruby/common/Histogram.cc
View File

@@ -26,11 +26,12 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "mem/ruby/common/Histogram.hh"
#include <cmath>
#include <iomanip>
#include "base/intmath.hh"
#include "mem/ruby/common/Histogram.hh"
using namespace std;

4
src/mem/ruby/common/NetDest.cc
View File

@@ -26,10 +26,10 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <algorithm>
#include "mem/ruby/common/NetDest.hh"
#include <algorithm>
NetDest::NetDest()
{
resize();

3
src/mem/ruby/common/SubBlock.cc
View File

@@ -26,9 +26,10 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "base/stl_helpers.hh"
#include "mem/ruby/common/SubBlock.hh"
#include "base/stl_helpers.hh"
using m5::stl_helpers::operator<<;
SubBlock::SubBlock(Addr addr, int size)

3
src/mem/ruby/filters/BlockBloomFilter.cc
View File

@@ -26,9 +26,10 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "mem/ruby/filters/BlockBloomFilter.hh"
#include "base/intmath.hh"
#include "base/str.hh"
#include "mem/ruby/filters/BlockBloomFilter.hh"
#include "mem/ruby/system/RubySystem.hh"
using namespace std;

3
src/mem/ruby/filters/BulkBloomFilter.cc
View File

@@ -26,11 +26,12 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "mem/ruby/filters/BulkBloomFilter.hh"
#include <cassert>
#include "base/intmath.hh"
#include "base/str.hh"
#include "mem/ruby/filters/BulkBloomFilter.hh"
#include "mem/ruby/system/RubySystem.hh"
using namespace std;

3
src/mem/ruby/filters/H3BloomFilter.cc
View File

@@ -26,9 +26,10 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "base/intmath.hh"
#include "mem/ruby/filters/H3BloomFilter.hh"
#include "base/intmath.hh"
using namespace std;
static int H3[64][16] = {

3
src/mem/ruby/filters/LSB_CountingBloomFilter.cc
View File

@@ -26,8 +26,9 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "base/intmath.hh"
#include "mem/ruby/filters/LSB_CountingBloomFilter.hh"
#include "base/intmath.hh"
#include "mem/ruby/system/RubySystem.hh"
using namespace std;

3
src/mem/ruby/filters/MultiBitSelBloomFilter.cc
View File

@@ -26,11 +26,12 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "mem/ruby/filters/MultiBitSelBloomFilter.hh"
#include <vector>
#include "base/intmath.hh"
#include "base/str.hh"
#include "mem/ruby/filters/MultiBitSelBloomFilter.hh"
using namespace std;

3
src/mem/ruby/filters/MultiGrainBloomFilter.cc
View File

@@ -26,9 +26,10 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "mem/ruby/filters/MultiGrainBloomFilter.hh"
#include "base/intmath.hh"
#include "base/str.hh"
#include "mem/ruby/filters/MultiGrainBloomFilter.hh"
#include "mem/ruby/system/RubySystem.hh"
using namespace std;

3
src/mem/ruby/filters/NonCountingBloomFilter.cc
View File

@@ -26,9 +26,10 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "mem/ruby/filters/NonCountingBloomFilter.hh"
#include "base/intmath.hh"
#include "base/str.hh"
#include "mem/ruby/filters/NonCountingBloomFilter.hh"
#include "mem/ruby/system/RubySystem.hh"
using namespace std;

3
src/mem/ruby/network/MessageBuffer.cc
View File

@@ -26,6 +26,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "mem/ruby/network/MessageBuffer.hh"
#include <cassert>
#include "base/cprintf.hh"
@@ -33,7 +35,6 @@
#include "base/random.hh"
#include "base/stl_helpers.hh"
#include "debug/RubyQueue.hh"
#include "mem/ruby/network/MessageBuffer.hh"
#include "mem/ruby/system/RubySystem.hh"
using namespace std;

3
src/mem/ruby/network/Network.cc
View File

@@ -26,9 +26,10 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "mem/ruby/network/Network.hh"
#include "base/misc.hh"
#include "mem/ruby/network/BasicLink.hh"
#include "mem/ruby/network/Network.hh"
#include "mem/ruby/system/RubySystem.hh"
uint32_t Network::m_virtual_networks;

4
src/mem/ruby/network/Topology.cc
View File

@@ -26,13 +26,15 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "mem/ruby/network/Topology.hh"
#include <cassert>
#include "base/trace.hh"
#include "debug/RubyNetwork.hh"
#include "mem/ruby/common/NetDest.hh"
#include "mem/ruby/network/BasicLink.hh"
#include "mem/ruby/network/Topology.hh"
#include "mem/ruby/network/Network.hh"
#include "mem/ruby/slicc_interface/AbstractController.hh"
using namespace std;

3
src/mem/ruby/network/simple/PerfectSwitch.cc
View File

@@ -26,13 +26,14 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "mem/ruby/network/simple/PerfectSwitch.hh"
#include <algorithm>
#include "base/cast.hh"
#include "base/random.hh"
#include "debug/RubyNetwork.hh"
#include "mem/ruby/network/MessageBuffer.hh"
#include "mem/ruby/network/simple/PerfectSwitch.hh"
#include "mem/ruby/network/simple/SimpleNetwork.hh"
#include "mem/ruby/network/simple/Switch.hh"
#include "mem/ruby/slicc_interface/Message.hh"

1
src/mem/ruby/network/simple/PerfectSwitch.hh
View File

@@ -41,6 +41,7 @@
#include <vector>
#include "mem/ruby/common/Consumer.hh"
#include "mem/ruby/common/TypeDefines.hh"
class MessageBuffer;
class NetDest;

3
src/mem/ruby/network/simple/SimpleNetwork.cc
View File

@@ -26,6 +26,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "mem/ruby/network/simple/SimpleNetwork.hh"
#include <cassert>
#include <numeric>
@@ -34,7 +36,6 @@
#include "mem/ruby/common/NetDest.hh"
#include "mem/ruby/network/MessageBuffer.hh"
#include "mem/ruby/network/simple/SimpleLink.hh"
#include "mem/ruby/network/simple/SimpleNetwork.hh"
#include "mem/ruby/network/simple/Switch.hh"
#include "mem/ruby/network/simple/Throttle.hh"
#include "mem/ruby/profiler/Profiler.hh"

3
src/mem/ruby/network/simple/Switch.cc
View File

@@ -26,6 +26,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "mem/ruby/network/simple/Switch.hh"
#include <numeric>
#include "base/cast.hh"
@@ -33,7 +35,6 @@
#include "mem/ruby/network/MessageBuffer.hh"
#include "mem/ruby/network/simple/PerfectSwitch.hh"
#include "mem/ruby/network/simple/SimpleNetwork.hh"
#include "mem/ruby/network/simple/Switch.hh"
#include "mem/ruby/network/simple/Throttle.hh"
using namespace std;

5
src/mem/ruby/network/simple/Throttle.cc
View File

@@ -26,15 +26,16 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "mem/ruby/network/simple/Throttle.hh"
#include <cassert>
#include "base/cast.hh"
#include "base/cprintf.hh"
#include "debug/RubyNetwork.hh"
#include "mem/ruby/network/simple/Switch.hh"
#include "mem/ruby/network/simple/Throttle.hh"
#include "mem/ruby/network/MessageBuffer.hh"
#include "mem/ruby/network/Network.hh"
#include "mem/ruby/network/simple/Switch.hh"
#include "mem/ruby/slicc_interface/Message.hh"
#include "mem/ruby/system/RubySystem.hh"

3
src/mem/ruby/profiler/AccessTraceForAddress.cc
View File

@@ -26,9 +26,10 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "mem/ruby/common/Histogram.hh"
#include "mem/ruby/profiler/AccessTraceForAddress.hh"
#include "mem/ruby/common/Histogram.hh"
AccessTraceForAddress::~AccessTraceForAddress()
{
if (m_histogram_ptr) {

3
src/mem/ruby/profiler/AddressProfiler.cc
View File

@@ -26,11 +26,12 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "mem/ruby/profiler/AddressProfiler.hh"
#include <vector>
#include "base/stl_helpers.hh"
#include "mem/protocol/RubyRequest.hh"
#include "mem/ruby/profiler/AddressProfiler.hh"
#include "mem/ruby/profiler/Profiler.hh"
using namespace std;

1
src/mem/ruby/profiler/StoreTrace.cc
View File

@@ -27,6 +27,7 @@
*/
#include "mem/ruby/profiler/StoreTrace.hh"
#include "sim/core.hh"
using namespace std;

3
src/mem/ruby/slicc_interface/AbstractController.cc
View File

@@ -30,9 +30,10 @@
#include "debug/RubyQueue.hh"
#include "mem/protocol/MemoryMsg.hh"
#include "mem/ruby/network/Network.hh"
#include "mem/ruby/system/GPUCoalescer.hh"
#include "mem/ruby/system/RubySystem.hh"
#include "mem/ruby/system/Sequencer.hh"
#include "mem/ruby/system/GPUCoalescer.hh"
#include "sim/system.hh"
AbstractController::AbstractController(const Params *p)

1
src/mem/ruby/slicc_interface/AbstractController.hh
View File

@@ -41,7 +41,6 @@
#include "mem/ruby/common/Histogram.hh"
#include "mem/ruby/common/MachineID.hh"
#include "mem/ruby/network/MessageBuffer.hh"
#include "mem/ruby/network/Network.hh"
#include "mem/ruby/system/CacheRecorder.hh"
#include "mem/packet.hh"
#include "mem/qport.hh"

4
src/mem/ruby/slicc_interface/RubyRequest.cc
View File

@@ -26,10 +26,10 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <iostream>
#include "mem/ruby/slicc_interface/RubyRequest.hh"
#include <iostream>
using namespace std;
void

3
src/mem/ruby/structures/BankedArray.cc
View File

@@ -29,8 +29,9 @@
*
*/
#include "base/intmath.hh"
#include "mem/ruby/structures/BankedArray.hh"
#include "base/intmath.hh"
#include "mem/ruby/system/RubySystem.hh"
BankedArray::BankedArray(unsigned int banks, Cycles accessLatency,

3
src/mem/ruby/structures/CacheMemory.cc
View File

@@ -27,13 +27,14 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "mem/ruby/structures/CacheMemory.hh"
#include "base/intmath.hh"
#include "debug/RubyCache.hh"
#include "debug/RubyCacheTrace.hh"
#include "debug/RubyResourceStalls.hh"
#include "debug/RubyStats.hh"
#include "mem/protocol/AccessPermission.hh"
#include "mem/ruby/structures/CacheMemory.hh"
#include "mem/ruby/system/RubySystem.hh"
#include "mem/ruby/system/WeightedLRUPolicy.hh"

3
src/mem/ruby/structures/DirectoryMemory.cc
View File

@@ -26,11 +26,12 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "mem/ruby/structures/DirectoryMemory.hh"
#include "base/intmath.hh"
#include "debug/RubyCache.hh"
#include "debug/RubyStats.hh"
#include "mem/ruby/slicc_interface/RubySlicc_Util.hh"
#include "mem/ruby/structures/DirectoryMemory.hh"
#include "mem/ruby/system/RubySystem.hh"
using namespace std;

2
src/mem/ruby/structures/LRUPolicy.cc
View File

@@ -30,8 +30,6 @@
#include "mem/ruby/structures/LRUPolicy.hh"
LRUPolicy::LRUPolicy(const Params * p)
: AbstractReplacementPolicy(p)
{

3
src/mem/ruby/structures/Prefetcher.cc
View File

@@ -26,9 +26,10 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "mem/ruby/structures/Prefetcher.hh"
#include "debug/RubyPrefetcher.hh"
#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh"
#include "mem/ruby/structures/Prefetcher.hh"
#include "mem/ruby/system/RubySystem.hh"
Prefetcher*

2
src/mem/ruby/structures/PseudoLRUPolicy.cc
View File

@@ -30,8 +30,6 @@
#include "mem/ruby/structures/PseudoLRUPolicy.hh"
PseudoLRUPolicy::PseudoLRUPolicy(const Params * p)
: AbstractReplacementPolicy(p)
{

3
src/mem/ruby/structures/WireBuffer.cc
View File

@@ -29,12 +29,13 @@
*
*/
#include "mem/ruby/structures/WireBuffer.hh"
#include <algorithm>
#include <functional>
#include "base/cprintf.hh"
#include "base/stl_helpers.hh"
#include "mem/ruby/structures/WireBuffer.hh"
#include "mem/ruby/system/RubySystem.hh"
using namespace std;

3
src/mem/ruby/system/CacheRecorder.cc
View File

@@ -27,8 +27,9 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "debug/RubyCacheTrace.hh"
#include "mem/ruby/system/CacheRecorder.hh"
#include "debug/RubyCacheTrace.hh"
#include "mem/ruby/system/RubySystem.hh"
#include "mem/ruby/system/Sequencer.hh"

3
src/mem/ruby/system/DMASequencer.cc
View File

@@ -26,13 +26,14 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "mem/ruby/system/DMASequencer.hh"
#include <memory>
#include "debug/RubyDma.hh"
#include "debug/RubyStats.hh"
#include "mem/protocol/SequencerMsg.hh"
#include "mem/protocol/SequencerRequestType.hh"
#include "mem/ruby/system/DMASequencer.hh"
#include "mem/ruby/system/RubySystem.hh"
DMARequest::DMARequest(uint64_t start_paddr, int len, bool write,

3
src/mem/ruby/system/RubyPort.cc
View File

@@ -39,13 +39,14 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "mem/ruby/system/RubyPort.hh"
#include "cpu/testers/rubytest/RubyTester.hh"
#include "debug/Config.hh"
#include "debug/Drain.hh"
#include "debug/Ruby.hh"
#include "mem/protocol/AccessPermission.hh"
#include "mem/ruby/slicc_interface/AbstractController.hh"
#include "mem/ruby/system/RubyPort.hh"
#include "mem/simple_mem.hh"
#include "sim/full_system.hh"
#include "sim/system.hh"

5
src/mem/ruby/system/Sequencer.cc
View File

@@ -26,6 +26,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "mem/ruby/system/Sequencer.hh"
#include "arch/x86/ldstflags.hh"
#include "base/misc.hh"
#include "base/str.hh"
@@ -34,13 +36,12 @@
#include "debug/ProtocolTrace.hh"
#include "debug/RubySequencer.hh"
#include "debug/RubyStats.hh"
#include "mem/packet.hh"
#include "mem/protocol/PrefetchBit.hh"
#include "mem/protocol/RubyAccessMode.hh"
#include "mem/ruby/profiler/Profiler.hh"
#include "mem/ruby/slicc_interface/RubyRequest.hh"
#include "mem/ruby/system/RubySystem.hh"
#include "mem/ruby/system/Sequencer.hh"
#include "mem/packet.hh"
#include "sim/system.hh"
using namespace std;

3
src/mem/se_translating_port_proxy.cc
View File

@@ -42,13 +42,14 @@
* Andreas Hansson
*/
#include "mem/se_translating_port_proxy.hh"
#include <string>
#include "arch/isa_traits.hh"
#include "base/chunk_generator.hh"
#include "config/the_isa.hh"
#include "mem/page_table.hh"
#include "mem/se_translating_port_proxy.hh"
#include "sim/process.hh"
#include "sim/system.hh"

1
src/mem/serial_link.cc
View File

@@ -56,7 +56,6 @@
#include "debug/SerialLink.hh"
#include "params/SerialLink.hh"
SerialLink::SerialLinkSlavePort::SerialLinkSlavePort(const std::string& _name,
SerialLink& _serial_link,
SerialLinkMasterPort& _masterPort,

3
src/mem/simple_mem.cc
View File

@@ -42,8 +42,9 @@
* Andreas Hansson
*/
#include "base/random.hh"
#include "mem/simple_mem.hh"
#include "base/random.hh"
#include "debug/Drain.hh"
using namespace std;

1
src/mem/slicc/symbols/StateMachine.py
View File

@@ -470,6 +470,7 @@ void unset_tbe(${{self.TBEType.c_ident}}*& m_tbe_ptr);
#include "mem/protocol/${ident}_Event.hh"
#include "mem/protocol/${ident}_State.hh"
#include "mem/protocol/Types.hh"
#include "mem/ruby/network/Network.hh"
#include "mem/ruby/system/RubySystem.hh"
''')

3
src/mem/snoop_filter.cc
View File

@@ -42,10 +42,11 @@
* Implementation of a snoop filter.
*/
#include "mem/snoop_filter.hh"
#include "base/misc.hh"
#include "base/trace.hh"
#include "debug/SnoopFilter.hh"
#include "mem/snoop_filter.hh"
#include "sim/system.hh"
void

3
src/mem/tport.cc
View File

@@ -41,9 +41,10 @@
* Andreas Hansson
*/
#include "mem/mem_object.hh"
#include "mem/tport.hh"
#include "mem/mem_object.hh"
SimpleTimingPort::SimpleTimingPort(const std::string& _name,
MemObject* _owner) :
QueuedSlavePort(_name, _owner, queueImpl), queueImpl(*_owner, *this)

3
src/mem/xbar.cc
View File

@@ -47,12 +47,13 @@
* Definition of a crossbar object.
*/
#include "mem/xbar.hh"
#include "base/misc.hh"
#include "base/trace.hh"
#include "debug/AddrRanges.hh"
#include "debug/Drain.hh"
#include "debug/XBar.hh"
#include "mem/xbar.hh"
BaseXBar::BaseXBar(const BaseXBarParams *p)
: MemObject(p),