From 79d407280ca0d7553b1f29a9533f64664b8ecb65 Mon Sep 17 00:00:00 2001
From: Alex Richardson <alexrichardson@google.com>
Date: Mon, 27 Feb 2023 16:58:44 +0000
Subject: [PATCH] arch-riscv: Fix invalid std::map access

The CSRData map uses a RISC-V CSR number as the key rather than one of
the MISCREG_* enumerators. Use MiscRegNames[] instead to stringify the
argument for the debug message.

Change-Id: I2533bc29d148d3b34c01022eeaeedf64c39a99b9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68759
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---
 src/arch/riscv/isa.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index d778957b9e..7964de51ec 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -510,7 +510,7 @@ ISA::setMiscReg(RegIndex idx, RegVal val)
 {
     if (idx >= MISCREG_CYCLE && idx <= MISCREG_HPMCOUNTER31) {
         // Ignore writes to HPM counters for now
-        warn("Ignoring write to %s.\n", CSRData.at(idx).name);
+        warn("Ignoring write to miscreg %s.\n", MiscRegNames[idx]);
     } else {
         switch (idx) {