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O3: Send instruction back to fetch on squash to seed predecoder correctly.

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This commit is contained in:
Ali Saidi
2011-03-17 19:20:19 -05:00
parent 30143baf7e
commit 799c3da8d0
10 changed files with 58 additions and 5 deletions
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5
src/cpu/o3/cpu.cc
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@@ -808,8 +808,9 @@ FullO3CPU<Impl>::removeThread(ThreadID tid)
}
// Squash Throughout Pipeline
InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum;
fetch.squash(0, squash_seq_num, tid);
DynInstPtr inst = commit.rob->readHeadInst(tid);
InstSeqNum squash_seq_num = inst->seqNum;
fetch.squash(0, squash_seq_num, inst, tid);
decode.squash(tid);
rename.squash(squash_seq_num, tid);
iew.squash(tid);

4
src/cpu/o3/fetch.hh
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@@ -312,8 +312,8 @@ class DefaultFetch
* remove any instructions that are not in the ROB. The source of this
* squash should be the commit stage.
*/
void squash(const TheISA::PCState &newPC,
const InstSeqNum &seq_num, ThreadID tid);
void squash(const TheISA::PCState &newPC, const InstSeqNum &seq_num,
DynInstPtr &squashInst, ThreadID tid);
/** Ticks the fetch stage, processing all inputs signals and fetching
* as many instructions as possible.

5
src/cpu/o3/fetch_impl.hh
View File

@@ -815,11 +815,14 @@ DefaultFetch<Impl>::updateFetchStatus()
template <class Impl>
void
DefaultFetch<Impl>::squash(const TheISA::PCState &newPC,
const InstSeqNum &seq_num, ThreadID tid)
const InstSeqNum &seq_num, DynInstPtr &squashInst,
ThreadID tid)
{
DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n", tid);
doSquash(newPC, tid);
if (squashInst)
predecoder.reset(squashInst->staticInst->machInst);
// Tell the CPU to remove any instructions that are not in the ROB.
cpu->removeInstsNotInROB(tid);