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Change Packet parameters on Port methods from references to pointers.

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--HG--
extra : convert_revision : 7193e70304d4cbe1e4cbe16ce0d8527b2754d066
This commit is contained in:
Steve Reinhardt
2006-05-18 22:32:21 -04:00
parent 381c4f6720
commit 796fa429fe
38 changed files with 528 additions and 528 deletions
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12
cpu/simple/atomic.cc
View File

@@ -78,21 +78,21 @@ AtomicSimpleCPU::init()
}
bool
AtomicSimpleCPU::CpuPort::recvTiming(Packet &pkt)
AtomicSimpleCPU::CpuPort::recvTiming(Packet *pkt)
{
panic("AtomicSimpleCPU doesn't expect recvAtomic callback!");
return true;
}
Tick
AtomicSimpleCPU::CpuPort::recvAtomic(Packet &pkt)
AtomicSimpleCPU::CpuPort::recvAtomic(Packet *pkt)
{
panic("AtomicSimpleCPU doesn't expect recvAtomic callback!");
return curTick;
}
void
AtomicSimpleCPU::CpuPort::recvFunctional(Packet &pkt)
AtomicSimpleCPU::CpuPort::recvFunctional(Packet *pkt)
{
panic("AtomicSimpleCPU doesn't expect recvFunctional callback!");
}
@@ -263,7 +263,7 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
data_read_pkt->addr = data_read_req->getPaddr();
data_read_pkt->size = sizeof(T);
dcache_complete = dcachePort.sendAtomic(*data_read_pkt);
dcache_complete = dcachePort.sendAtomic(data_read_pkt);
dcache_access = true;
assert(data_read_pkt->result == Success);
@@ -345,7 +345,7 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
data_write_pkt->addr = data_write_req->getPaddr();
data_write_pkt->size = sizeof(T);
dcache_complete = dcachePort.sendAtomic(*data_write_pkt);
dcache_complete = dcachePort.sendAtomic(data_write_pkt);
dcache_access = true;
assert(data_write_pkt->result == Success);
@@ -430,7 +430,7 @@ AtomicSimpleCPU::tick()
Fault fault = setupFetchPacket(ifetch_pkt);
if (fault == NoFault) {
Tick icache_complete = icachePort.sendAtomic(*ifetch_pkt);
Tick icache_complete = icachePort.sendAtomic(ifetch_pkt);
// ifetch_req is initialized to read the instruction directly
// into the CPU object's inst field.

6
cpu/simple/atomic.hh
View File

@@ -90,11 +90,11 @@ class AtomicSimpleCPU : public BaseSimpleCPU
protected:
virtual bool recvTiming(Packet &pkt);
virtual bool recvTiming(Packet *pkt);
virtual Tick recvAtomic(Packet &pkt);
virtual Tick recvAtomic(Packet *pkt);
virtual void recvFunctional(Packet &pkt);
virtual void recvFunctional(Packet *pkt);
virtual void recvStatusChange(Status status);

16
cpu/simple/timing.cc
View File

@@ -60,14 +60,14 @@ TimingSimpleCPU::init()
}
Tick
TimingSimpleCPU::CpuPort::recvAtomic(Packet &pkt)
TimingSimpleCPU::CpuPort::recvAtomic(Packet *pkt)
{
panic("TimingSimpleCPU doesn't expect recvAtomic callback!");
return curTick;
}
void
TimingSimpleCPU::CpuPort::recvFunctional(Packet &pkt)
TimingSimpleCPU::CpuPort::recvFunctional(Packet *pkt)
{
panic("TimingSimpleCPU doesn't expect recvFunctional callback!");
}
@@ -192,7 +192,7 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
data_read_pkt->size = sizeof(T);
data_read_pkt->dest = Packet::Broadcast;
if (!dcachePort.sendTiming(*data_read_pkt)) {
if (!dcachePort.sendTiming(data_read_pkt)) {
_status = DcacheRetry;
dcache_pkt = data_read_pkt;
} else {
@@ -274,7 +274,7 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
data_write_pkt->addr = data_write_req->getPaddr();
data_write_pkt->dest = Packet::Broadcast;
if (!dcachePort.sendTiming(*data_write_pkt)) {
if (!dcachePort.sendTiming(data_write_pkt)) {
_status = DcacheRetry;
dcache_pkt = data_write_pkt;
} else {
@@ -354,7 +354,7 @@ TimingSimpleCPU::fetch()
Fault fault = setupFetchPacket(ifetch_pkt);
if (fault == NoFault) {
if (!icachePort.sendTiming(*ifetch_pkt)) {
if (!icachePort.sendTiming(ifetch_pkt)) {
// Need to wait for retry
_status = IcacheRetry;
} else {
@@ -406,7 +406,7 @@ TimingSimpleCPU::completeIfetch()
bool
TimingSimpleCPU::IcachePort::recvTiming(Packet &pkt)
TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
{
cpu->completeIfetch();
return true;
@@ -442,9 +442,9 @@ TimingSimpleCPU::completeDataAccess(Packet *pkt)
bool
TimingSimpleCPU::DcachePort::recvTiming(Packet &pkt)
TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt)
{
cpu->completeDataAccess(&pkt);
cpu->completeDataAccess(pkt);
return true;
}

8
cpu/simple/timing.hh
View File

@@ -77,9 +77,9 @@ class TimingSimpleCPU : public BaseSimpleCPU
protected:
virtual Tick recvAtomic(Packet &pkt);
virtual Tick recvAtomic(Packet *pkt);
virtual void recvFunctional(Packet &pkt);
virtual void recvFunctional(Packet *pkt);
virtual void recvStatusChange(Status status);
@@ -98,7 +98,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
protected:
virtual bool recvTiming(Packet &pkt);
virtual bool recvTiming(Packet *pkt);
virtual Packet *recvRetry();
};
@@ -113,7 +113,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
protected:
virtual bool recvTiming(Packet &pkt);
virtual bool recvTiming(Packet *pkt);
virtual Packet *recvRetry();
};